1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * linux/arch/arm/plat-omap/dmtimer.c 4 * 5 * OMAP Dual-Mode Timers 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ 8 * Tarun Kanti DebBarma <tarun.kanti@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * dmtimer adaptation to platform_driver. 12 * 13 * Copyright (C) 2005 Nokia Corporation 14 * OMAP2 support by Juha Yrjola 15 * API improvements and OMAP2 clock framework support by Timo Teras 16 * 17 * Copyright (C) 2009 Texas Instruments 18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/cpu_pm.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/device.h> 27 #include <linux/err.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/platform_device.h> 32 #include <linux/platform_data/dmtimer-omap.h> 33 34 #include <clocksource/timer-ti-dm.h> 35 36 static u32 omap_reserved_systimers; 37 static LIST_HEAD(omap_timer_list); 38 static DEFINE_SPINLOCK(dm_timer_lock); 39 40 enum { 41 REQUEST_ANY = 0, 42 REQUEST_BY_ID, 43 REQUEST_BY_CAP, 44 REQUEST_BY_NODE, 45 }; 46 47 /** 48 * dmtimer_read - read timer registers in posted and non-posted mode 49 * @timer: timer pointer over which read operation to perform 50 * @reg: lowest byte holds the register offset 51 * 52 * The posted mode bit is encoded in reg. Note that in posted mode, write 53 * pending bit must be checked. Otherwise a read of a non completed write 54 * will produce an error. 55 */ 56 static inline u32 dmtimer_read(struct omap_dm_timer *timer, u32 reg) 57 { 58 u16 wp, offset; 59 60 wp = reg >> WPSHIFT; 61 offset = reg & 0xff; 62 63 /* Wait for a possible write pending bit in posted mode */ 64 if (wp && timer->posted) 65 while (readl_relaxed(timer->pend) & wp) 66 cpu_relax(); 67 68 return readl_relaxed(timer->func_base + offset); 69 } 70 71 /** 72 * dmtimer_write - write timer registers in posted and non-posted mode 73 * @timer: timer pointer over which write operation is to perform 74 * @reg: lowest byte holds the register offset 75 * @value: data to write into the register 76 * 77 * The posted mode bit is encoded in reg. Note that in posted mode, the write 78 * pending bit must be checked. Otherwise a write on a register which has a 79 * pending write will be lost. 80 */ 81 static inline void dmtimer_write(struct omap_dm_timer *timer, u32 reg, u32 val) 82 { 83 u16 wp, offset; 84 85 wp = reg >> WPSHIFT; 86 offset = reg & 0xff; 87 88 /* Wait for a possible write pending bit in posted mode */ 89 if (wp && timer->posted) 90 while (readl_relaxed(timer->pend) & wp) 91 cpu_relax(); 92 93 writel_relaxed(val, timer->func_base + offset); 94 } 95 96 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) 97 { 98 u32 tidr; 99 100 /* Assume v1 ip if bits [31:16] are zero */ 101 tidr = readl_relaxed(timer->io_base); 102 if (!(tidr >> 16)) { 103 timer->revision = 1; 104 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET; 105 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; 106 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET; 107 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; 108 timer->func_base = timer->io_base; 109 } else { 110 timer->revision = 2; 111 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET; 112 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET; 113 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET; 114 timer->pend = timer->io_base + 115 _OMAP_TIMER_WRITE_PEND_OFFSET + 116 OMAP_TIMER_V2_FUNC_OFFSET; 117 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; 118 } 119 } 120 121 /* 122 * __omap_dm_timer_enable_posted - enables write posted mode 123 * @timer: pointer to timer instance handle 124 * 125 * Enables the write posted mode for the timer. When posted mode is enabled 126 * writes to certain timer registers are immediately acknowledged by the 127 * internal bus and hence prevents stalling the CPU waiting for the write to 128 * complete. Enabling this feature can improve performance for writing to the 129 * timer registers. 130 */ 131 static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer) 132 { 133 if (timer->posted) 134 return; 135 136 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { 137 timer->posted = OMAP_TIMER_NONPOSTED; 138 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0); 139 return; 140 } 141 142 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED); 143 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; 144 timer->posted = OMAP_TIMER_POSTED; 145 } 146 147 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, 148 unsigned long rate) 149 { 150 u32 l; 151 152 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 153 if (l & OMAP_TIMER_CTRL_ST) { 154 l &= ~0x1; 155 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 156 #ifdef CONFIG_ARCH_OMAP2PLUS 157 /* Readback to make sure write has completed */ 158 dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 159 /* 160 * Wait for functional clock period x 3.5 to make sure that 161 * timer is stopped 162 */ 163 udelay(3500000 / rate + 1); 164 #endif 165 } 166 167 /* Ack possibly pending interrupt */ 168 dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW); 169 } 170 171 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, 172 unsigned int value) 173 { 174 dmtimer_write(timer, timer->irq_ena, value); 175 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value); 176 } 177 178 static inline unsigned int 179 __omap_dm_timer_read_counter(struct omap_dm_timer *timer) 180 { 181 return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG); 182 } 183 184 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, 185 unsigned int value) 186 { 187 dmtimer_write(timer, timer->irq_stat, value); 188 } 189 190 static void omap_timer_restore_context(struct omap_dm_timer *timer) 191 { 192 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg); 193 194 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); 195 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr); 196 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr); 197 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar); 198 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); 199 dmtimer_write(timer, timer->irq_ena, timer->context.tier); 200 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); 201 } 202 203 static void omap_timer_save_context(struct omap_dm_timer *timer) 204 { 205 timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); 206 207 timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 208 timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG); 209 timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG); 210 timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG); 211 timer->context.tier = dmtimer_read(timer, timer->irq_ena); 212 timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG); 213 } 214 215 static int omap_timer_context_notifier(struct notifier_block *nb, 216 unsigned long cmd, void *v) 217 { 218 struct omap_dm_timer *timer; 219 220 timer = container_of(nb, struct omap_dm_timer, nb); 221 222 switch (cmd) { 223 case CPU_CLUSTER_PM_ENTER: 224 if ((timer->capability & OMAP_TIMER_ALWON) || 225 !atomic_read(&timer->enabled)) 226 break; 227 omap_timer_save_context(timer); 228 break; 229 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 230 break; 231 case CPU_CLUSTER_PM_EXIT: 232 if ((timer->capability & OMAP_TIMER_ALWON) || 233 !atomic_read(&timer->enabled)) 234 break; 235 omap_timer_restore_context(timer); 236 break; 237 } 238 239 return NOTIFY_OK; 240 } 241 242 static int omap_dm_timer_reset(struct omap_dm_timer *timer) 243 { 244 u32 l, timeout = 100000; 245 246 if (timer->revision != 1) 247 return -EINVAL; 248 249 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 250 251 do { 252 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET); 253 } while (!l && timeout--); 254 255 if (!timeout) { 256 dev_err(&timer->pdev->dev, "Timer failed to reset\n"); 257 return -ETIMEDOUT; 258 } 259 260 /* Configure timer for smart-idle mode */ 261 l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); 262 l |= 0x2 << 0x3; 263 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l); 264 265 timer->posted = 0; 266 267 return 0; 268 } 269 270 static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 271 { 272 int ret; 273 const char *parent_name; 274 struct clk *parent; 275 struct dmtimer_platform_data *pdata; 276 277 if (unlikely(!timer) || IS_ERR(timer->fclk)) 278 return -EINVAL; 279 280 switch (source) { 281 case OMAP_TIMER_SRC_SYS_CLK: 282 parent_name = "timer_sys_ck"; 283 break; 284 case OMAP_TIMER_SRC_32_KHZ: 285 parent_name = "timer_32k_ck"; 286 break; 287 case OMAP_TIMER_SRC_EXT_CLK: 288 parent_name = "timer_ext_ck"; 289 break; 290 default: 291 return -EINVAL; 292 } 293 294 pdata = timer->pdev->dev.platform_data; 295 296 /* 297 * FIXME: Used for OMAP1 devices only because they do not currently 298 * use the clock framework to set the parent clock. To be removed 299 * once OMAP1 migrated to using clock framework for dmtimers 300 */ 301 if (pdata && pdata->set_timer_src) 302 return pdata->set_timer_src(timer->pdev, source); 303 304 #if defined(CONFIG_COMMON_CLK) 305 /* Check if the clock has configurable parents */ 306 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) 307 return 0; 308 #endif 309 310 parent = clk_get(&timer->pdev->dev, parent_name); 311 if (IS_ERR(parent)) { 312 pr_err("%s: %s not found\n", __func__, parent_name); 313 return -EINVAL; 314 } 315 316 ret = clk_set_parent(timer->fclk, parent); 317 if (ret < 0) 318 pr_err("%s: failed to set %s as parent\n", __func__, 319 parent_name); 320 321 clk_put(parent); 322 323 return ret; 324 } 325 326 static void omap_dm_timer_enable(struct omap_dm_timer *timer) 327 { 328 pm_runtime_get_sync(&timer->pdev->dev); 329 } 330 331 static void omap_dm_timer_disable(struct omap_dm_timer *timer) 332 { 333 pm_runtime_put_sync(&timer->pdev->dev); 334 } 335 336 static int omap_dm_timer_prepare(struct omap_dm_timer *timer) 337 { 338 int rc; 339 340 /* 341 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so 342 * do not call clk_get() for these devices. 343 */ 344 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { 345 timer->fclk = clk_get(&timer->pdev->dev, "fck"); 346 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { 347 dev_err(&timer->pdev->dev, ": No fclk handle.\n"); 348 return -EINVAL; 349 } 350 } 351 352 omap_dm_timer_enable(timer); 353 354 if (timer->capability & OMAP_TIMER_NEEDS_RESET) { 355 rc = omap_dm_timer_reset(timer); 356 if (rc) { 357 omap_dm_timer_disable(timer); 358 return rc; 359 } 360 } 361 362 __omap_dm_timer_enable_posted(timer); 363 omap_dm_timer_disable(timer); 364 365 return 0; 366 } 367 368 static inline u32 omap_dm_timer_reserved_systimer(int id) 369 { 370 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; 371 } 372 373 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) 374 { 375 struct omap_dm_timer *timer = NULL, *t; 376 struct device_node *np = NULL; 377 unsigned long flags; 378 u32 cap = 0; 379 int id = 0; 380 381 switch (req_type) { 382 case REQUEST_BY_ID: 383 id = *(int *)data; 384 break; 385 case REQUEST_BY_CAP: 386 cap = *(u32 *)data; 387 break; 388 case REQUEST_BY_NODE: 389 np = (struct device_node *)data; 390 break; 391 default: 392 /* REQUEST_ANY */ 393 break; 394 } 395 396 spin_lock_irqsave(&dm_timer_lock, flags); 397 list_for_each_entry(t, &omap_timer_list, node) { 398 if (t->reserved) 399 continue; 400 401 switch (req_type) { 402 case REQUEST_BY_ID: 403 if (id == t->pdev->id) { 404 timer = t; 405 timer->reserved = 1; 406 goto found; 407 } 408 break; 409 case REQUEST_BY_CAP: 410 if (cap == (t->capability & cap)) { 411 /* 412 * If timer is not NULL, we have already found 413 * one timer. But it was not an exact match 414 * because it had more capabilities than what 415 * was required. Therefore, unreserve the last 416 * timer found and see if this one is a better 417 * match. 418 */ 419 if (timer) 420 timer->reserved = 0; 421 timer = t; 422 timer->reserved = 1; 423 424 /* Exit loop early if we find an exact match */ 425 if (t->capability == cap) 426 goto found; 427 } 428 break; 429 case REQUEST_BY_NODE: 430 if (np == t->pdev->dev.of_node) { 431 timer = t; 432 timer->reserved = 1; 433 goto found; 434 } 435 break; 436 default: 437 /* REQUEST_ANY */ 438 timer = t; 439 timer->reserved = 1; 440 goto found; 441 } 442 } 443 found: 444 spin_unlock_irqrestore(&dm_timer_lock, flags); 445 446 if (timer && omap_dm_timer_prepare(timer)) { 447 timer->reserved = 0; 448 timer = NULL; 449 } 450 451 if (!timer) 452 pr_debug("%s: timer request failed!\n", __func__); 453 454 return timer; 455 } 456 457 static struct omap_dm_timer *omap_dm_timer_request(void) 458 { 459 return _omap_dm_timer_request(REQUEST_ANY, NULL); 460 } 461 462 static struct omap_dm_timer *omap_dm_timer_request_specific(int id) 463 { 464 /* Requesting timer by ID is not supported when device tree is used */ 465 if (of_have_populated_dt()) { 466 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", 467 __func__); 468 return NULL; 469 } 470 471 return _omap_dm_timer_request(REQUEST_BY_ID, &id); 472 } 473 474 /** 475 * omap_dm_timer_request_by_node - Request a timer by device-tree node 476 * @np: Pointer to device-tree timer node 477 * 478 * Request a timer based upon a device node pointer. Returns pointer to 479 * timer handle on success and a NULL pointer on failure. 480 */ 481 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) 482 { 483 if (!np) 484 return NULL; 485 486 return _omap_dm_timer_request(REQUEST_BY_NODE, np); 487 } 488 489 static int omap_dm_timer_free(struct omap_dm_timer *timer) 490 { 491 if (unlikely(!timer)) 492 return -EINVAL; 493 494 clk_put(timer->fclk); 495 496 WARN_ON(!timer->reserved); 497 timer->reserved = 0; 498 return 0; 499 } 500 501 int omap_dm_timer_get_irq(struct omap_dm_timer *timer) 502 { 503 if (timer) 504 return timer->irq; 505 return -EINVAL; 506 } 507 508 #if defined(CONFIG_ARCH_OMAP1) 509 #include <linux/soc/ti/omap1-io.h> 510 511 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 512 { 513 return NULL; 514 } 515 516 /** 517 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 518 * @inputmask: current value of idlect mask 519 */ 520 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 521 { 522 int i = 0; 523 struct omap_dm_timer *timer = NULL; 524 unsigned long flags; 525 526 /* If ARMXOR cannot be idled this function call is unnecessary */ 527 if (!(inputmask & (1 << 1))) 528 return inputmask; 529 530 /* If any active timer is using ARMXOR return modified mask */ 531 spin_lock_irqsave(&dm_timer_lock, flags); 532 list_for_each_entry(timer, &omap_timer_list, node) { 533 u32 l; 534 535 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 536 if (l & OMAP_TIMER_CTRL_ST) { 537 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) 538 inputmask &= ~(1 << 1); 539 else 540 inputmask &= ~(1 << 2); 541 } 542 i++; 543 } 544 spin_unlock_irqrestore(&dm_timer_lock, flags); 545 546 return inputmask; 547 } 548 549 #else 550 551 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 552 { 553 if (timer && !IS_ERR(timer->fclk)) 554 return timer->fclk; 555 return NULL; 556 } 557 558 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 559 { 560 BUG(); 561 562 return 0; 563 } 564 565 #endif 566 567 static int omap_dm_timer_start(struct omap_dm_timer *timer) 568 { 569 u32 l; 570 571 if (unlikely(!timer)) 572 return -EINVAL; 573 574 omap_dm_timer_enable(timer); 575 576 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 577 if (!(l & OMAP_TIMER_CTRL_ST)) { 578 l |= OMAP_TIMER_CTRL_ST; 579 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 580 } 581 582 return 0; 583 } 584 585 static int omap_dm_timer_stop(struct omap_dm_timer *timer) 586 { 587 unsigned long rate = 0; 588 589 if (unlikely(!timer)) 590 return -EINVAL; 591 592 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) 593 rate = clk_get_rate(timer->fclk); 594 595 __omap_dm_timer_stop(timer, rate); 596 597 omap_dm_timer_disable(timer); 598 return 0; 599 } 600 601 static int omap_dm_timer_set_load(struct omap_dm_timer *timer, 602 unsigned int load) 603 { 604 if (unlikely(!timer)) 605 return -EINVAL; 606 607 omap_dm_timer_enable(timer); 608 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load); 609 610 omap_dm_timer_disable(timer); 611 return 0; 612 } 613 614 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, 615 unsigned int match) 616 { 617 u32 l; 618 619 if (unlikely(!timer)) 620 return -EINVAL; 621 622 omap_dm_timer_enable(timer); 623 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 624 if (enable) 625 l |= OMAP_TIMER_CTRL_CE; 626 else 627 l &= ~OMAP_TIMER_CTRL_CE; 628 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match); 629 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 630 631 omap_dm_timer_disable(timer); 632 return 0; 633 } 634 635 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, 636 int toggle, int trigger, int autoreload) 637 { 638 u32 l; 639 640 if (unlikely(!timer)) 641 return -EINVAL; 642 643 omap_dm_timer_enable(timer); 644 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 645 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | 646 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); 647 if (def_on) 648 l |= OMAP_TIMER_CTRL_SCPWM; 649 if (toggle) 650 l |= OMAP_TIMER_CTRL_PT; 651 l |= trigger << 10; 652 if (autoreload) 653 l |= OMAP_TIMER_CTRL_AR; 654 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 655 656 omap_dm_timer_disable(timer); 657 return 0; 658 } 659 660 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) 661 { 662 u32 l; 663 664 if (unlikely(!timer)) 665 return -EINVAL; 666 667 omap_dm_timer_enable(timer); 668 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 669 omap_dm_timer_disable(timer); 670 671 return l; 672 } 673 674 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, 675 int prescaler) 676 { 677 u32 l; 678 679 if (unlikely(!timer) || prescaler < -1 || prescaler > 7) 680 return -EINVAL; 681 682 omap_dm_timer_enable(timer); 683 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 684 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); 685 if (prescaler >= 0) { 686 l |= OMAP_TIMER_CTRL_PRE; 687 l |= prescaler << 2; 688 } 689 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 690 691 omap_dm_timer_disable(timer); 692 return 0; 693 } 694 695 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 696 unsigned int value) 697 { 698 if (unlikely(!timer)) 699 return -EINVAL; 700 701 omap_dm_timer_enable(timer); 702 __omap_dm_timer_int_enable(timer, value); 703 704 omap_dm_timer_disable(timer); 705 return 0; 706 } 707 708 /** 709 * omap_dm_timer_set_int_disable - disable timer interrupts 710 * @timer: pointer to timer handle 711 * @mask: bit mask of interrupts to be disabled 712 * 713 * Disables the specified timer interrupts for a timer. 714 */ 715 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) 716 { 717 u32 l = mask; 718 719 if (unlikely(!timer)) 720 return -EINVAL; 721 722 omap_dm_timer_enable(timer); 723 724 if (timer->revision == 1) 725 l = dmtimer_read(timer, timer->irq_ena) & ~mask; 726 727 dmtimer_write(timer, timer->irq_dis, l); 728 l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; 729 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l); 730 731 omap_dm_timer_disable(timer); 732 return 0; 733 } 734 735 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 736 { 737 unsigned int l; 738 739 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 740 pr_err("%s: timer not available or enabled.\n", __func__); 741 return 0; 742 } 743 744 l = dmtimer_read(timer, timer->irq_stat); 745 746 return l; 747 } 748 749 static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 750 { 751 if (unlikely(!timer || !atomic_read(&timer->enabled))) 752 return -EINVAL; 753 754 __omap_dm_timer_write_status(timer, value); 755 756 return 0; 757 } 758 759 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 760 { 761 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 762 pr_err("%s: timer not iavailable or enabled.\n", __func__); 763 return 0; 764 } 765 766 return __omap_dm_timer_read_counter(timer); 767 } 768 769 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) 770 { 771 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 772 pr_err("%s: timer not available or enabled.\n", __func__); 773 return -EINVAL; 774 } 775 776 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value); 777 778 /* Save the context */ 779 timer->context.tcrr = value; 780 return 0; 781 } 782 783 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) 784 { 785 struct omap_dm_timer *timer = dev_get_drvdata(dev); 786 787 atomic_set(&timer->enabled, 0); 788 789 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) 790 return 0; 791 792 omap_timer_save_context(timer); 793 794 return 0; 795 } 796 797 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) 798 { 799 struct omap_dm_timer *timer = dev_get_drvdata(dev); 800 801 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) 802 omap_timer_restore_context(timer); 803 804 atomic_set(&timer->enabled, 1); 805 806 return 0; 807 } 808 809 static const struct dev_pm_ops omap_dm_timer_pm_ops = { 810 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, 811 omap_dm_timer_runtime_resume, NULL) 812 }; 813 814 static const struct of_device_id omap_timer_match[]; 815 816 /** 817 * omap_dm_timer_probe - probe function called for every registered device 818 * @pdev: pointer to current timer platform device 819 * 820 * Called by driver framework at the end of device registration for all 821 * timer devices. 822 */ 823 static int omap_dm_timer_probe(struct platform_device *pdev) 824 { 825 unsigned long flags; 826 struct omap_dm_timer *timer; 827 struct device *dev = &pdev->dev; 828 const struct dmtimer_platform_data *pdata; 829 int ret; 830 831 pdata = of_device_get_match_data(dev); 832 if (!pdata) 833 pdata = dev_get_platdata(dev); 834 else 835 dev->platform_data = (void *)pdata; 836 837 if (!pdata) { 838 dev_err(dev, "%s: no platform data.\n", __func__); 839 return -ENODEV; 840 } 841 842 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); 843 if (!timer) 844 return -ENOMEM; 845 846 timer->irq = platform_get_irq(pdev, 0); 847 if (timer->irq < 0) 848 return timer->irq; 849 850 timer->fclk = ERR_PTR(-ENODEV); 851 timer->io_base = devm_platform_ioremap_resource(pdev, 0); 852 if (IS_ERR(timer->io_base)) 853 return PTR_ERR(timer->io_base); 854 855 platform_set_drvdata(pdev, timer); 856 857 if (dev->of_node) { 858 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) 859 timer->capability |= OMAP_TIMER_ALWON; 860 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) 861 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; 862 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) 863 timer->capability |= OMAP_TIMER_HAS_PWM; 864 if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) 865 timer->capability |= OMAP_TIMER_SECURE; 866 } else { 867 timer->id = pdev->id; 868 timer->capability = pdata->timer_capability; 869 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 870 } 871 872 if (!(timer->capability & OMAP_TIMER_ALWON)) { 873 timer->nb.notifier_call = omap_timer_context_notifier; 874 cpu_pm_register_notifier(&timer->nb); 875 } 876 877 timer->errata = pdata->timer_errata; 878 879 timer->pdev = pdev; 880 881 pm_runtime_enable(dev); 882 883 if (!timer->reserved) { 884 ret = pm_runtime_get_sync(dev); 885 if (ret < 0) { 886 dev_err(dev, "%s: pm_runtime_get_sync failed!\n", 887 __func__); 888 goto err_get_sync; 889 } 890 __omap_dm_timer_init_regs(timer); 891 pm_runtime_put(dev); 892 } 893 894 /* add the timer element to the list */ 895 spin_lock_irqsave(&dm_timer_lock, flags); 896 list_add_tail(&timer->node, &omap_timer_list); 897 spin_unlock_irqrestore(&dm_timer_lock, flags); 898 899 dev_dbg(dev, "Device Probed.\n"); 900 901 return 0; 902 903 err_get_sync: 904 pm_runtime_put_noidle(dev); 905 pm_runtime_disable(dev); 906 return ret; 907 } 908 909 /** 910 * omap_dm_timer_remove - cleanup a registered timer device 911 * @pdev: pointer to current timer platform device 912 * 913 * Called by driver framework whenever a timer device is unregistered. 914 * In addition to freeing platform resources it also deletes the timer 915 * entry from the local list. 916 */ 917 static int omap_dm_timer_remove(struct platform_device *pdev) 918 { 919 struct omap_dm_timer *timer; 920 unsigned long flags; 921 int ret = -EINVAL; 922 923 spin_lock_irqsave(&dm_timer_lock, flags); 924 list_for_each_entry(timer, &omap_timer_list, node) 925 if (!strcmp(dev_name(&timer->pdev->dev), 926 dev_name(&pdev->dev))) { 927 if (!(timer->capability & OMAP_TIMER_ALWON)) 928 cpu_pm_unregister_notifier(&timer->nb); 929 list_del(&timer->node); 930 ret = 0; 931 break; 932 } 933 spin_unlock_irqrestore(&dm_timer_lock, flags); 934 935 pm_runtime_disable(&pdev->dev); 936 937 return ret; 938 } 939 940 static const struct omap_dm_timer_ops dmtimer_ops = { 941 .request_by_node = omap_dm_timer_request_by_node, 942 .request_specific = omap_dm_timer_request_specific, 943 .request = omap_dm_timer_request, 944 .set_source = omap_dm_timer_set_source, 945 .get_irq = omap_dm_timer_get_irq, 946 .set_int_enable = omap_dm_timer_set_int_enable, 947 .set_int_disable = omap_dm_timer_set_int_disable, 948 .free = omap_dm_timer_free, 949 .enable = omap_dm_timer_enable, 950 .disable = omap_dm_timer_disable, 951 .get_fclk = omap_dm_timer_get_fclk, 952 .start = omap_dm_timer_start, 953 .stop = omap_dm_timer_stop, 954 .set_load = omap_dm_timer_set_load, 955 .set_match = omap_dm_timer_set_match, 956 .set_pwm = omap_dm_timer_set_pwm, 957 .get_pwm_status = omap_dm_timer_get_pwm_status, 958 .set_prescaler = omap_dm_timer_set_prescaler, 959 .read_counter = omap_dm_timer_read_counter, 960 .write_counter = omap_dm_timer_write_counter, 961 .read_status = omap_dm_timer_read_status, 962 .write_status = omap_dm_timer_write_status, 963 }; 964 965 static const struct dmtimer_platform_data omap3plus_pdata = { 966 .timer_errata = OMAP_TIMER_ERRATA_I103_I767, 967 .timer_ops = &dmtimer_ops, 968 }; 969 970 static const struct dmtimer_platform_data am6_pdata = { 971 .timer_ops = &dmtimer_ops, 972 }; 973 974 static const struct of_device_id omap_timer_match[] = { 975 { 976 .compatible = "ti,omap2420-timer", 977 }, 978 { 979 .compatible = "ti,omap3430-timer", 980 .data = &omap3plus_pdata, 981 }, 982 { 983 .compatible = "ti,omap4430-timer", 984 .data = &omap3plus_pdata, 985 }, 986 { 987 .compatible = "ti,omap5430-timer", 988 .data = &omap3plus_pdata, 989 }, 990 { 991 .compatible = "ti,am335x-timer", 992 .data = &omap3plus_pdata, 993 }, 994 { 995 .compatible = "ti,am335x-timer-1ms", 996 .data = &omap3plus_pdata, 997 }, 998 { 999 .compatible = "ti,dm816-timer", 1000 .data = &omap3plus_pdata, 1001 }, 1002 { 1003 .compatible = "ti,am654-timer", 1004 .data = &am6_pdata, 1005 }, 1006 {}, 1007 }; 1008 MODULE_DEVICE_TABLE(of, omap_timer_match); 1009 1010 static struct platform_driver omap_dm_timer_driver = { 1011 .probe = omap_dm_timer_probe, 1012 .remove = omap_dm_timer_remove, 1013 .driver = { 1014 .name = "omap_timer", 1015 .of_match_table = of_match_ptr(omap_timer_match), 1016 .pm = &omap_dm_timer_pm_ops, 1017 }, 1018 }; 1019 1020 module_platform_driver(omap_dm_timer_driver); 1021 1022 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); 1023 MODULE_LICENSE("GPL"); 1024 MODULE_AUTHOR("Texas Instruments Inc"); 1025