1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * linux/arch/arm/plat-omap/dmtimer.c 4 * 5 * OMAP Dual-Mode Timers 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ 8 * Tarun Kanti DebBarma <tarun.kanti@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * dmtimer adaptation to platform_driver. 12 * 13 * Copyright (C) 2005 Nokia Corporation 14 * OMAP2 support by Juha Yrjola 15 * API improvements and OMAP2 clock framework support by Timo Teras 16 * 17 * Copyright (C) 2009 Texas Instruments 18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/cpu_pm.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/device.h> 27 #include <linux/err.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/of.h> 30 #include <linux/platform_device.h> 31 #include <linux/platform_data/dmtimer-omap.h> 32 33 #include <clocksource/timer-ti-dm.h> 34 35 /* 36 * timer errata flags 37 * 38 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This 39 * errata prevents us from using posted mode on these devices, unless the 40 * timer counter register is never read. For more details please refer to 41 * the OMAP3/4/5 errata documents. 42 */ 43 #define OMAP_TIMER_ERRATA_I103_I767 0x80000000 44 45 /* posted mode types */ 46 #define OMAP_TIMER_NONPOSTED 0x00 47 #define OMAP_TIMER_POSTED 0x01 48 49 /* register offsets with the write pending bit encoded */ 50 #define WPSHIFT 16 51 52 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ 53 | (WP_NONE << WPSHIFT)) 54 55 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ 56 | (WP_TCLR << WPSHIFT)) 57 58 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ 59 | (WP_TCRR << WPSHIFT)) 60 61 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ 62 | (WP_TLDR << WPSHIFT)) 63 64 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ 65 | (WP_TTGR << WPSHIFT)) 66 67 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ 68 | (WP_NONE << WPSHIFT)) 69 70 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ 71 | (WP_TMAR << WPSHIFT)) 72 73 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ 74 | (WP_NONE << WPSHIFT)) 75 76 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ 77 | (WP_NONE << WPSHIFT)) 78 79 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ 80 | (WP_NONE << WPSHIFT)) 81 82 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ 83 | (WP_TPIR << WPSHIFT)) 84 85 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ 86 | (WP_TNIR << WPSHIFT)) 87 88 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ 89 | (WP_TCVR << WPSHIFT)) 90 91 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \ 92 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) 93 94 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ 95 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) 96 97 struct timer_regs { 98 u32 ocp_cfg; 99 u32 tidr; 100 u32 tier; 101 u32 twer; 102 u32 tclr; 103 u32 tcrr; 104 u32 tldr; 105 u32 ttrg; 106 u32 twps; 107 u32 tmar; 108 u32 tcar1; 109 u32 tsicr; 110 u32 tcar2; 111 u32 tpir; 112 u32 tnir; 113 u32 tcvr; 114 u32 tocr; 115 u32 towr; 116 }; 117 118 struct dmtimer { 119 struct omap_dm_timer cookie; 120 int id; 121 int irq; 122 struct clk *fclk; 123 124 void __iomem *io_base; 125 int irq_stat; /* TISR/IRQSTATUS interrupt status */ 126 int irq_ena; /* irq enable */ 127 int irq_dis; /* irq disable, only on v2 ip */ 128 void __iomem *pend; /* write pending */ 129 void __iomem *func_base; /* function register base */ 130 131 atomic_t enabled; 132 unsigned long rate; 133 unsigned reserved:1; 134 unsigned posted:1; 135 unsigned omap1:1; 136 struct timer_regs context; 137 int revision; 138 u32 capability; 139 u32 errata; 140 struct platform_device *pdev; 141 struct list_head node; 142 struct notifier_block nb; 143 }; 144 145 static u32 omap_reserved_systimers; 146 static LIST_HEAD(omap_timer_list); 147 static DEFINE_SPINLOCK(dm_timer_lock); 148 149 enum { 150 REQUEST_ANY = 0, 151 REQUEST_BY_ID, 152 REQUEST_BY_CAP, 153 REQUEST_BY_NODE, 154 }; 155 156 /** 157 * dmtimer_read - read timer registers in posted and non-posted mode 158 * @timer: timer pointer over which read operation to perform 159 * @reg: lowest byte holds the register offset 160 * 161 * The posted mode bit is encoded in reg. Note that in posted mode, write 162 * pending bit must be checked. Otherwise a read of a non completed write 163 * will produce an error. 164 */ 165 static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg) 166 { 167 u16 wp, offset; 168 169 wp = reg >> WPSHIFT; 170 offset = reg & 0xff; 171 172 /* Wait for a possible write pending bit in posted mode */ 173 if (wp && timer->posted) 174 while (readl_relaxed(timer->pend) & wp) 175 cpu_relax(); 176 177 return readl_relaxed(timer->func_base + offset); 178 } 179 180 /** 181 * dmtimer_write - write timer registers in posted and non-posted mode 182 * @timer: timer pointer over which write operation is to perform 183 * @reg: lowest byte holds the register offset 184 * @value: data to write into the register 185 * 186 * The posted mode bit is encoded in reg. Note that in posted mode, the write 187 * pending bit must be checked. Otherwise a write on a register which has a 188 * pending write will be lost. 189 */ 190 static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val) 191 { 192 u16 wp, offset; 193 194 wp = reg >> WPSHIFT; 195 offset = reg & 0xff; 196 197 /* Wait for a possible write pending bit in posted mode */ 198 if (wp && timer->posted) 199 while (readl_relaxed(timer->pend) & wp) 200 cpu_relax(); 201 202 writel_relaxed(val, timer->func_base + offset); 203 } 204 205 static inline void __omap_dm_timer_init_regs(struct dmtimer *timer) 206 { 207 u32 tidr; 208 209 /* Assume v1 ip if bits [31:16] are zero */ 210 tidr = readl_relaxed(timer->io_base); 211 if (!(tidr >> 16)) { 212 timer->revision = 1; 213 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET; 214 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; 215 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET; 216 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; 217 timer->func_base = timer->io_base; 218 } else { 219 timer->revision = 2; 220 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET; 221 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET; 222 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET; 223 timer->pend = timer->io_base + 224 _OMAP_TIMER_WRITE_PEND_OFFSET + 225 OMAP_TIMER_V2_FUNC_OFFSET; 226 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; 227 } 228 } 229 230 /* 231 * __omap_dm_timer_enable_posted - enables write posted mode 232 * @timer: pointer to timer instance handle 233 * 234 * Enables the write posted mode for the timer. When posted mode is enabled 235 * writes to certain timer registers are immediately acknowledged by the 236 * internal bus and hence prevents stalling the CPU waiting for the write to 237 * complete. Enabling this feature can improve performance for writing to the 238 * timer registers. 239 */ 240 static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer) 241 { 242 if (timer->posted) 243 return; 244 245 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { 246 timer->posted = OMAP_TIMER_NONPOSTED; 247 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0); 248 return; 249 } 250 251 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED); 252 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; 253 timer->posted = OMAP_TIMER_POSTED; 254 } 255 256 static inline void __omap_dm_timer_stop(struct dmtimer *timer, 257 unsigned long rate) 258 { 259 u32 l; 260 261 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 262 if (l & OMAP_TIMER_CTRL_ST) { 263 l &= ~0x1; 264 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 265 #ifdef CONFIG_ARCH_OMAP2PLUS 266 /* Readback to make sure write has completed */ 267 dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 268 /* 269 * Wait for functional clock period x 3.5 to make sure that 270 * timer is stopped 271 */ 272 udelay(3500000 / rate + 1); 273 #endif 274 } 275 276 /* Ack possibly pending interrupt */ 277 dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW); 278 } 279 280 static inline void __omap_dm_timer_int_enable(struct dmtimer *timer, 281 unsigned int value) 282 { 283 dmtimer_write(timer, timer->irq_ena, value); 284 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value); 285 } 286 287 static inline unsigned int 288 __omap_dm_timer_read_counter(struct dmtimer *timer) 289 { 290 return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG); 291 } 292 293 static inline void __omap_dm_timer_write_status(struct dmtimer *timer, 294 unsigned int value) 295 { 296 dmtimer_write(timer, timer->irq_stat, value); 297 } 298 299 static void omap_timer_restore_context(struct dmtimer *timer) 300 { 301 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg); 302 303 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); 304 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr); 305 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr); 306 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar); 307 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); 308 dmtimer_write(timer, timer->irq_ena, timer->context.tier); 309 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); 310 } 311 312 static void omap_timer_save_context(struct dmtimer *timer) 313 { 314 timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); 315 316 timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 317 timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG); 318 timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG); 319 timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG); 320 timer->context.tier = dmtimer_read(timer, timer->irq_ena); 321 timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG); 322 } 323 324 static int omap_timer_context_notifier(struct notifier_block *nb, 325 unsigned long cmd, void *v) 326 { 327 struct dmtimer *timer; 328 329 timer = container_of(nb, struct dmtimer, nb); 330 331 switch (cmd) { 332 case CPU_CLUSTER_PM_ENTER: 333 if ((timer->capability & OMAP_TIMER_ALWON) || 334 !atomic_read(&timer->enabled)) 335 break; 336 omap_timer_save_context(timer); 337 break; 338 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 339 break; 340 case CPU_CLUSTER_PM_EXIT: 341 if ((timer->capability & OMAP_TIMER_ALWON) || 342 !atomic_read(&timer->enabled)) 343 break; 344 omap_timer_restore_context(timer); 345 break; 346 } 347 348 return NOTIFY_OK; 349 } 350 351 static int omap_dm_timer_reset(struct dmtimer *timer) 352 { 353 u32 l, timeout = 100000; 354 355 if (timer->revision != 1) 356 return -EINVAL; 357 358 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 359 360 do { 361 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET); 362 } while (!l && timeout--); 363 364 if (!timeout) { 365 dev_err(&timer->pdev->dev, "Timer failed to reset\n"); 366 return -ETIMEDOUT; 367 } 368 369 /* Configure timer for smart-idle mode */ 370 l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); 371 l |= 0x2 << 0x3; 372 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l); 373 374 timer->posted = 0; 375 376 return 0; 377 } 378 379 /* 380 * Functions exposed to PWM and remoteproc drivers via platform_data. 381 * Do not use these in the driver, these will get deprecated and will 382 * will be replaced by Linux generic framework functions such as 383 * chained interrupts and clock framework. 384 */ 385 static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie) 386 { 387 if (!cookie) 388 return NULL; 389 390 return container_of(cookie, struct dmtimer, cookie); 391 } 392 393 static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source) 394 { 395 int ret; 396 const char *parent_name; 397 struct clk *parent; 398 struct dmtimer_platform_data *pdata; 399 struct dmtimer *timer; 400 401 timer = to_dmtimer(cookie); 402 if (unlikely(!timer) || IS_ERR(timer->fclk)) 403 return -EINVAL; 404 405 switch (source) { 406 case OMAP_TIMER_SRC_SYS_CLK: 407 parent_name = "timer_sys_ck"; 408 break; 409 case OMAP_TIMER_SRC_32_KHZ: 410 parent_name = "timer_32k_ck"; 411 break; 412 case OMAP_TIMER_SRC_EXT_CLK: 413 parent_name = "timer_ext_ck"; 414 break; 415 default: 416 return -EINVAL; 417 } 418 419 pdata = timer->pdev->dev.platform_data; 420 421 /* 422 * FIXME: Used for OMAP1 devices only because they do not currently 423 * use the clock framework to set the parent clock. To be removed 424 * once OMAP1 migrated to using clock framework for dmtimers 425 */ 426 if (timer->omap1 && pdata && pdata->set_timer_src) 427 return pdata->set_timer_src(timer->pdev, source); 428 429 #if defined(CONFIG_COMMON_CLK) 430 /* Check if the clock has configurable parents */ 431 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) 432 return 0; 433 #endif 434 435 parent = clk_get(&timer->pdev->dev, parent_name); 436 if (IS_ERR(parent)) { 437 pr_err("%s: %s not found\n", __func__, parent_name); 438 return -EINVAL; 439 } 440 441 ret = clk_set_parent(timer->fclk, parent); 442 if (ret < 0) 443 pr_err("%s: failed to set %s as parent\n", __func__, 444 parent_name); 445 446 clk_put(parent); 447 448 return ret; 449 } 450 451 static void omap_dm_timer_enable(struct omap_dm_timer *cookie) 452 { 453 struct dmtimer *timer = to_dmtimer(cookie); 454 struct device *dev = &timer->pdev->dev; 455 int rc; 456 457 rc = pm_runtime_resume_and_get(dev); 458 if (rc) 459 dev_err(dev, "could not enable timer\n"); 460 } 461 462 static void omap_dm_timer_disable(struct omap_dm_timer *cookie) 463 { 464 struct dmtimer *timer = to_dmtimer(cookie); 465 struct device *dev = &timer->pdev->dev; 466 467 pm_runtime_put_sync(dev); 468 } 469 470 static int omap_dm_timer_prepare(struct dmtimer *timer) 471 { 472 struct device *dev = &timer->pdev->dev; 473 int rc; 474 475 rc = pm_runtime_resume_and_get(dev); 476 if (rc) 477 return rc; 478 479 if (timer->capability & OMAP_TIMER_NEEDS_RESET) { 480 rc = omap_dm_timer_reset(timer); 481 if (rc) { 482 pm_runtime_put_sync(dev); 483 return rc; 484 } 485 } 486 487 __omap_dm_timer_enable_posted(timer); 488 pm_runtime_put_sync(dev); 489 490 return 0; 491 } 492 493 static inline u32 omap_dm_timer_reserved_systimer(int id) 494 { 495 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; 496 } 497 498 static struct dmtimer *_omap_dm_timer_request(int req_type, void *data) 499 { 500 struct dmtimer *timer = NULL, *t; 501 struct device_node *np = NULL; 502 unsigned long flags; 503 u32 cap = 0; 504 int id = 0; 505 506 switch (req_type) { 507 case REQUEST_BY_ID: 508 id = *(int *)data; 509 break; 510 case REQUEST_BY_CAP: 511 cap = *(u32 *)data; 512 break; 513 case REQUEST_BY_NODE: 514 np = (struct device_node *)data; 515 break; 516 default: 517 /* REQUEST_ANY */ 518 break; 519 } 520 521 spin_lock_irqsave(&dm_timer_lock, flags); 522 list_for_each_entry(t, &omap_timer_list, node) { 523 if (t->reserved) 524 continue; 525 526 switch (req_type) { 527 case REQUEST_BY_ID: 528 if (id == t->pdev->id) { 529 timer = t; 530 timer->reserved = 1; 531 goto found; 532 } 533 break; 534 case REQUEST_BY_CAP: 535 if (cap == (t->capability & cap)) { 536 /* 537 * If timer is not NULL, we have already found 538 * one timer. But it was not an exact match 539 * because it had more capabilities than what 540 * was required. Therefore, unreserve the last 541 * timer found and see if this one is a better 542 * match. 543 */ 544 if (timer) 545 timer->reserved = 0; 546 timer = t; 547 timer->reserved = 1; 548 549 /* Exit loop early if we find an exact match */ 550 if (t->capability == cap) 551 goto found; 552 } 553 break; 554 case REQUEST_BY_NODE: 555 if (np == t->pdev->dev.of_node) { 556 timer = t; 557 timer->reserved = 1; 558 goto found; 559 } 560 break; 561 default: 562 /* REQUEST_ANY */ 563 timer = t; 564 timer->reserved = 1; 565 goto found; 566 } 567 } 568 found: 569 spin_unlock_irqrestore(&dm_timer_lock, flags); 570 571 if (timer && omap_dm_timer_prepare(timer)) { 572 timer->reserved = 0; 573 timer = NULL; 574 } 575 576 if (!timer) 577 pr_debug("%s: timer request failed!\n", __func__); 578 579 return timer; 580 } 581 582 static struct omap_dm_timer *omap_dm_timer_request(void) 583 { 584 struct dmtimer *timer; 585 586 timer = _omap_dm_timer_request(REQUEST_ANY, NULL); 587 if (!timer) 588 return NULL; 589 590 return &timer->cookie; 591 } 592 593 static struct omap_dm_timer *omap_dm_timer_request_specific(int id) 594 { 595 struct dmtimer *timer; 596 597 /* Requesting timer by ID is not supported when device tree is used */ 598 if (of_have_populated_dt()) { 599 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", 600 __func__); 601 return NULL; 602 } 603 604 timer = _omap_dm_timer_request(REQUEST_BY_ID, &id); 605 if (!timer) 606 return NULL; 607 608 return &timer->cookie; 609 } 610 611 /** 612 * omap_dm_timer_request_by_node - Request a timer by device-tree node 613 * @np: Pointer to device-tree timer node 614 * 615 * Request a timer based upon a device node pointer. Returns pointer to 616 * timer handle on success and a NULL pointer on failure. 617 */ 618 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) 619 { 620 struct dmtimer *timer; 621 622 if (!np) 623 return NULL; 624 625 timer = _omap_dm_timer_request(REQUEST_BY_NODE, np); 626 if (!timer) 627 return NULL; 628 629 return &timer->cookie; 630 } 631 632 static int omap_dm_timer_free(struct omap_dm_timer *cookie) 633 { 634 struct dmtimer *timer; 635 struct device *dev; 636 int rc; 637 638 timer = to_dmtimer(cookie); 639 if (unlikely(!timer)) 640 return -EINVAL; 641 642 WARN_ON(!timer->reserved); 643 timer->reserved = 0; 644 645 dev = &timer->pdev->dev; 646 rc = pm_runtime_resume_and_get(dev); 647 if (rc) 648 return rc; 649 650 /* Clear timer configuration */ 651 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0); 652 653 pm_runtime_put_sync(dev); 654 655 return 0; 656 } 657 658 static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie) 659 { 660 struct dmtimer *timer = to_dmtimer(cookie); 661 if (timer) 662 return timer->irq; 663 return -EINVAL; 664 } 665 666 #if defined(CONFIG_ARCH_OMAP1) 667 #include <linux/soc/ti/omap1-io.h> 668 669 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie) 670 { 671 return NULL; 672 } 673 674 /** 675 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 676 * @inputmask: current value of idlect mask 677 */ 678 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 679 { 680 int i = 0; 681 struct dmtimer *timer = NULL; 682 unsigned long flags; 683 684 /* If ARMXOR cannot be idled this function call is unnecessary */ 685 if (!(inputmask & (1 << 1))) 686 return inputmask; 687 688 /* If any active timer is using ARMXOR return modified mask */ 689 spin_lock_irqsave(&dm_timer_lock, flags); 690 list_for_each_entry(timer, &omap_timer_list, node) { 691 u32 l; 692 693 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 694 if (l & OMAP_TIMER_CTRL_ST) { 695 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) 696 inputmask &= ~(1 << 1); 697 else 698 inputmask &= ~(1 << 2); 699 } 700 i++; 701 } 702 spin_unlock_irqrestore(&dm_timer_lock, flags); 703 704 return inputmask; 705 } 706 707 #else 708 709 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie) 710 { 711 struct dmtimer *timer = to_dmtimer(cookie); 712 713 if (timer && !IS_ERR(timer->fclk)) 714 return timer->fclk; 715 return NULL; 716 } 717 718 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 719 { 720 BUG(); 721 722 return 0; 723 } 724 725 #endif 726 727 static int omap_dm_timer_start(struct omap_dm_timer *cookie) 728 { 729 struct dmtimer *timer; 730 struct device *dev; 731 int rc; 732 u32 l; 733 734 timer = to_dmtimer(cookie); 735 if (unlikely(!timer)) 736 return -EINVAL; 737 738 dev = &timer->pdev->dev; 739 740 rc = pm_runtime_resume_and_get(dev); 741 if (rc) 742 return rc; 743 744 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 745 if (!(l & OMAP_TIMER_CTRL_ST)) { 746 l |= OMAP_TIMER_CTRL_ST; 747 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 748 } 749 750 return 0; 751 } 752 753 static int omap_dm_timer_stop(struct omap_dm_timer *cookie) 754 { 755 struct dmtimer *timer; 756 struct device *dev; 757 unsigned long rate = 0; 758 759 timer = to_dmtimer(cookie); 760 if (unlikely(!timer)) 761 return -EINVAL; 762 763 dev = &timer->pdev->dev; 764 765 if (!timer->omap1) 766 rate = clk_get_rate(timer->fclk); 767 768 __omap_dm_timer_stop(timer, rate); 769 770 pm_runtime_put_sync(dev); 771 772 return 0; 773 } 774 775 static int omap_dm_timer_set_load(struct omap_dm_timer *cookie, 776 unsigned int load) 777 { 778 struct dmtimer *timer; 779 struct device *dev; 780 int rc; 781 782 timer = to_dmtimer(cookie); 783 if (unlikely(!timer)) 784 return -EINVAL; 785 786 dev = &timer->pdev->dev; 787 rc = pm_runtime_resume_and_get(dev); 788 if (rc) 789 return rc; 790 791 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load); 792 793 pm_runtime_put_sync(dev); 794 795 return 0; 796 } 797 798 static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable, 799 unsigned int match) 800 { 801 struct dmtimer *timer; 802 struct device *dev; 803 int rc; 804 u32 l; 805 806 timer = to_dmtimer(cookie); 807 if (unlikely(!timer)) 808 return -EINVAL; 809 810 dev = &timer->pdev->dev; 811 rc = pm_runtime_resume_and_get(dev); 812 if (rc) 813 return rc; 814 815 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 816 if (enable) 817 l |= OMAP_TIMER_CTRL_CE; 818 else 819 l &= ~OMAP_TIMER_CTRL_CE; 820 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match); 821 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 822 823 pm_runtime_put_sync(dev); 824 825 return 0; 826 } 827 828 static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, 829 int toggle, int trigger, int autoreload) 830 { 831 struct dmtimer *timer; 832 struct device *dev; 833 int rc; 834 u32 l; 835 836 timer = to_dmtimer(cookie); 837 if (unlikely(!timer)) 838 return -EINVAL; 839 840 dev = &timer->pdev->dev; 841 rc = pm_runtime_resume_and_get(dev); 842 if (rc) 843 return rc; 844 845 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 846 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | 847 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); 848 if (def_on) 849 l |= OMAP_TIMER_CTRL_SCPWM; 850 if (toggle) 851 l |= OMAP_TIMER_CTRL_PT; 852 l |= trigger << 10; 853 if (autoreload) 854 l |= OMAP_TIMER_CTRL_AR; 855 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 856 857 pm_runtime_put_sync(dev); 858 859 return 0; 860 } 861 862 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie) 863 { 864 struct dmtimer *timer; 865 struct device *dev; 866 int rc; 867 u32 l; 868 869 timer = to_dmtimer(cookie); 870 if (unlikely(!timer)) 871 return -EINVAL; 872 873 dev = &timer->pdev->dev; 874 rc = pm_runtime_resume_and_get(dev); 875 if (rc) 876 return rc; 877 878 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 879 880 pm_runtime_put_sync(dev); 881 882 return l; 883 } 884 885 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie, 886 int prescaler) 887 { 888 struct dmtimer *timer; 889 struct device *dev; 890 int rc; 891 u32 l; 892 893 timer = to_dmtimer(cookie); 894 if (unlikely(!timer) || prescaler < -1 || prescaler > 7) 895 return -EINVAL; 896 897 dev = &timer->pdev->dev; 898 rc = pm_runtime_resume_and_get(dev); 899 if (rc) 900 return rc; 901 902 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 903 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); 904 if (prescaler >= 0) { 905 l |= OMAP_TIMER_CTRL_PRE; 906 l |= prescaler << 2; 907 } 908 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 909 910 pm_runtime_put_sync(dev); 911 912 return 0; 913 } 914 915 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie, 916 unsigned int value) 917 { 918 struct dmtimer *timer; 919 struct device *dev; 920 int rc; 921 922 timer = to_dmtimer(cookie); 923 if (unlikely(!timer)) 924 return -EINVAL; 925 926 dev = &timer->pdev->dev; 927 rc = pm_runtime_resume_and_get(dev); 928 if (rc) 929 return rc; 930 931 __omap_dm_timer_int_enable(timer, value); 932 933 pm_runtime_put_sync(dev); 934 935 return 0; 936 } 937 938 /** 939 * omap_dm_timer_set_int_disable - disable timer interrupts 940 * @timer: pointer to timer handle 941 * @mask: bit mask of interrupts to be disabled 942 * 943 * Disables the specified timer interrupts for a timer. 944 */ 945 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask) 946 { 947 struct dmtimer *timer; 948 struct device *dev; 949 u32 l = mask; 950 int rc; 951 952 timer = to_dmtimer(cookie); 953 if (unlikely(!timer)) 954 return -EINVAL; 955 956 dev = &timer->pdev->dev; 957 rc = pm_runtime_resume_and_get(dev); 958 if (rc) 959 return rc; 960 961 if (timer->revision == 1) 962 l = dmtimer_read(timer, timer->irq_ena) & ~mask; 963 964 dmtimer_write(timer, timer->irq_dis, l); 965 l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; 966 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l); 967 968 pm_runtime_put_sync(dev); 969 970 return 0; 971 } 972 973 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie) 974 { 975 struct dmtimer *timer; 976 unsigned int l; 977 978 timer = to_dmtimer(cookie); 979 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 980 pr_err("%s: timer not available or enabled.\n", __func__); 981 return 0; 982 } 983 984 l = dmtimer_read(timer, timer->irq_stat); 985 986 return l; 987 } 988 989 static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value) 990 { 991 struct dmtimer *timer; 992 993 timer = to_dmtimer(cookie); 994 if (unlikely(!timer || !atomic_read(&timer->enabled))) 995 return -EINVAL; 996 997 __omap_dm_timer_write_status(timer, value); 998 999 return 0; 1000 } 1001 1002 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie) 1003 { 1004 struct dmtimer *timer; 1005 1006 timer = to_dmtimer(cookie); 1007 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1008 pr_err("%s: timer not iavailable or enabled.\n", __func__); 1009 return 0; 1010 } 1011 1012 return __omap_dm_timer_read_counter(timer); 1013 } 1014 1015 static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value) 1016 { 1017 struct dmtimer *timer; 1018 1019 timer = to_dmtimer(cookie); 1020 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1021 pr_err("%s: timer not available or enabled.\n", __func__); 1022 return -EINVAL; 1023 } 1024 1025 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value); 1026 1027 /* Save the context */ 1028 timer->context.tcrr = value; 1029 return 0; 1030 } 1031 1032 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) 1033 { 1034 struct dmtimer *timer = dev_get_drvdata(dev); 1035 1036 atomic_set(&timer->enabled, 0); 1037 1038 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) 1039 return 0; 1040 1041 omap_timer_save_context(timer); 1042 1043 return 0; 1044 } 1045 1046 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) 1047 { 1048 struct dmtimer *timer = dev_get_drvdata(dev); 1049 1050 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) 1051 omap_timer_restore_context(timer); 1052 1053 atomic_set(&timer->enabled, 1); 1054 1055 return 0; 1056 } 1057 1058 static const struct dev_pm_ops omap_dm_timer_pm_ops = { 1059 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, 1060 omap_dm_timer_runtime_resume, NULL) 1061 }; 1062 1063 static const struct of_device_id omap_timer_match[]; 1064 1065 /** 1066 * omap_dm_timer_probe - probe function called for every registered device 1067 * @pdev: pointer to current timer platform device 1068 * 1069 * Called by driver framework at the end of device registration for all 1070 * timer devices. 1071 */ 1072 static int omap_dm_timer_probe(struct platform_device *pdev) 1073 { 1074 unsigned long flags; 1075 struct dmtimer *timer; 1076 struct device *dev = &pdev->dev; 1077 const struct dmtimer_platform_data *pdata; 1078 int ret; 1079 1080 pdata = of_device_get_match_data(dev); 1081 if (!pdata) 1082 pdata = dev_get_platdata(dev); 1083 else 1084 dev->platform_data = (void *)pdata; 1085 1086 if (!pdata) { 1087 dev_err(dev, "%s: no platform data.\n", __func__); 1088 return -ENODEV; 1089 } 1090 1091 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); 1092 if (!timer) 1093 return -ENOMEM; 1094 1095 timer->irq = platform_get_irq(pdev, 0); 1096 if (timer->irq < 0) 1097 return timer->irq; 1098 1099 timer->io_base = devm_platform_ioremap_resource(pdev, 0); 1100 if (IS_ERR(timer->io_base)) 1101 return PTR_ERR(timer->io_base); 1102 1103 platform_set_drvdata(pdev, timer); 1104 1105 if (dev->of_node) { 1106 if (of_property_read_bool(dev->of_node, "ti,timer-alwon")) 1107 timer->capability |= OMAP_TIMER_ALWON; 1108 if (of_property_read_bool(dev->of_node, "ti,timer-dsp")) 1109 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; 1110 if (of_property_read_bool(dev->of_node, "ti,timer-pwm")) 1111 timer->capability |= OMAP_TIMER_HAS_PWM; 1112 if (of_property_read_bool(dev->of_node, "ti,timer-secure")) 1113 timer->capability |= OMAP_TIMER_SECURE; 1114 } else { 1115 timer->id = pdev->id; 1116 timer->capability = pdata->timer_capability; 1117 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 1118 } 1119 1120 timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET; 1121 1122 /* OMAP1 devices do not yet use the clock framework for dmtimers */ 1123 if (!timer->omap1) { 1124 timer->fclk = devm_clk_get(dev, "fck"); 1125 if (IS_ERR(timer->fclk)) 1126 return PTR_ERR(timer->fclk); 1127 } else { 1128 timer->fclk = ERR_PTR(-ENODEV); 1129 } 1130 1131 if (!(timer->capability & OMAP_TIMER_ALWON)) { 1132 timer->nb.notifier_call = omap_timer_context_notifier; 1133 cpu_pm_register_notifier(&timer->nb); 1134 } 1135 1136 timer->errata = pdata->timer_errata; 1137 1138 timer->pdev = pdev; 1139 1140 pm_runtime_enable(dev); 1141 1142 if (!timer->reserved) { 1143 ret = pm_runtime_resume_and_get(dev); 1144 if (ret) { 1145 dev_err(dev, "%s: pm_runtime_get_sync failed!\n", 1146 __func__); 1147 goto err_disable; 1148 } 1149 __omap_dm_timer_init_regs(timer); 1150 1151 /* Clear timer configuration */ 1152 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0); 1153 1154 pm_runtime_put(dev); 1155 } 1156 1157 /* add the timer element to the list */ 1158 spin_lock_irqsave(&dm_timer_lock, flags); 1159 list_add_tail(&timer->node, &omap_timer_list); 1160 spin_unlock_irqrestore(&dm_timer_lock, flags); 1161 1162 dev_dbg(dev, "Device Probed.\n"); 1163 1164 return 0; 1165 1166 err_disable: 1167 pm_runtime_disable(dev); 1168 return ret; 1169 } 1170 1171 /** 1172 * omap_dm_timer_remove - cleanup a registered timer device 1173 * @pdev: pointer to current timer platform device 1174 * 1175 * Called by driver framework whenever a timer device is unregistered. 1176 * In addition to freeing platform resources it also deletes the timer 1177 * entry from the local list. 1178 */ 1179 static void omap_dm_timer_remove(struct platform_device *pdev) 1180 { 1181 struct dmtimer *timer; 1182 unsigned long flags; 1183 int ret = -EINVAL; 1184 1185 spin_lock_irqsave(&dm_timer_lock, flags); 1186 list_for_each_entry(timer, &omap_timer_list, node) 1187 if (!strcmp(dev_name(&timer->pdev->dev), 1188 dev_name(&pdev->dev))) { 1189 if (!(timer->capability & OMAP_TIMER_ALWON)) 1190 cpu_pm_unregister_notifier(&timer->nb); 1191 list_del(&timer->node); 1192 ret = 0; 1193 break; 1194 } 1195 spin_unlock_irqrestore(&dm_timer_lock, flags); 1196 1197 pm_runtime_disable(&pdev->dev); 1198 1199 if (ret) 1200 dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n"); 1201 } 1202 1203 static const struct omap_dm_timer_ops dmtimer_ops = { 1204 .request_by_node = omap_dm_timer_request_by_node, 1205 .request_specific = omap_dm_timer_request_specific, 1206 .request = omap_dm_timer_request, 1207 .set_source = omap_dm_timer_set_source, 1208 .get_irq = omap_dm_timer_get_irq, 1209 .set_int_enable = omap_dm_timer_set_int_enable, 1210 .set_int_disable = omap_dm_timer_set_int_disable, 1211 .free = omap_dm_timer_free, 1212 .enable = omap_dm_timer_enable, 1213 .disable = omap_dm_timer_disable, 1214 .get_fclk = omap_dm_timer_get_fclk, 1215 .start = omap_dm_timer_start, 1216 .stop = omap_dm_timer_stop, 1217 .set_load = omap_dm_timer_set_load, 1218 .set_match = omap_dm_timer_set_match, 1219 .set_pwm = omap_dm_timer_set_pwm, 1220 .get_pwm_status = omap_dm_timer_get_pwm_status, 1221 .set_prescaler = omap_dm_timer_set_prescaler, 1222 .read_counter = omap_dm_timer_read_counter, 1223 .write_counter = omap_dm_timer_write_counter, 1224 .read_status = omap_dm_timer_read_status, 1225 .write_status = omap_dm_timer_write_status, 1226 }; 1227 1228 static const struct dmtimer_platform_data omap3plus_pdata = { 1229 .timer_errata = OMAP_TIMER_ERRATA_I103_I767, 1230 .timer_ops = &dmtimer_ops, 1231 }; 1232 1233 static const struct dmtimer_platform_data am6_pdata = { 1234 .timer_ops = &dmtimer_ops, 1235 }; 1236 1237 static const struct of_device_id omap_timer_match[] = { 1238 { 1239 .compatible = "ti,omap2420-timer", 1240 }, 1241 { 1242 .compatible = "ti,omap3430-timer", 1243 .data = &omap3plus_pdata, 1244 }, 1245 { 1246 .compatible = "ti,omap4430-timer", 1247 .data = &omap3plus_pdata, 1248 }, 1249 { 1250 .compatible = "ti,omap5430-timer", 1251 .data = &omap3plus_pdata, 1252 }, 1253 { 1254 .compatible = "ti,am335x-timer", 1255 .data = &omap3plus_pdata, 1256 }, 1257 { 1258 .compatible = "ti,am335x-timer-1ms", 1259 .data = &omap3plus_pdata, 1260 }, 1261 { 1262 .compatible = "ti,dm816-timer", 1263 .data = &omap3plus_pdata, 1264 }, 1265 { 1266 .compatible = "ti,am654-timer", 1267 .data = &am6_pdata, 1268 }, 1269 {}, 1270 }; 1271 MODULE_DEVICE_TABLE(of, omap_timer_match); 1272 1273 static struct platform_driver omap_dm_timer_driver = { 1274 .probe = omap_dm_timer_probe, 1275 .remove_new = omap_dm_timer_remove, 1276 .driver = { 1277 .name = "omap_timer", 1278 .of_match_table = omap_timer_match, 1279 .pm = &omap_dm_timer_pm_ops, 1280 }, 1281 }; 1282 1283 module_platform_driver(omap_dm_timer_driver); 1284 1285 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); 1286 MODULE_AUTHOR("Texas Instruments Inc"); 1287