1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * linux/arch/arm/plat-omap/dmtimer.c 4 * 5 * OMAP Dual-Mode Timers 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ 8 * Tarun Kanti DebBarma <tarun.kanti@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * dmtimer adaptation to platform_driver. 12 * 13 * Copyright (C) 2005 Nokia Corporation 14 * OMAP2 support by Juha Yrjola 15 * API improvements and OMAP2 clock framework support by Timo Teras 16 * 17 * Copyright (C) 2009 Texas Instruments 18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/cpu_pm.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/device.h> 27 #include <linux/err.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/platform_device.h> 32 #include <linux/platform_data/dmtimer-omap.h> 33 34 #include <clocksource/timer-ti-dm.h> 35 36 static u32 omap_reserved_systimers; 37 static LIST_HEAD(omap_timer_list); 38 static DEFINE_SPINLOCK(dm_timer_lock); 39 40 enum { 41 REQUEST_ANY = 0, 42 REQUEST_BY_ID, 43 REQUEST_BY_CAP, 44 REQUEST_BY_NODE, 45 }; 46 47 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, 48 int posted) 49 { 50 if (posted) 51 while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) 52 cpu_relax(); 53 54 return readl_relaxed(timer->func_base + (reg & 0xff)); 55 } 56 57 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, 58 u32 reg, u32 val, int posted) 59 { 60 if (posted) 61 while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) 62 cpu_relax(); 63 64 writel_relaxed(val, timer->func_base + (reg & 0xff)); 65 } 66 67 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) 68 { 69 u32 tidr; 70 71 /* Assume v1 ip if bits [31:16] are zero */ 72 tidr = readl_relaxed(timer->io_base); 73 if (!(tidr >> 16)) { 74 timer->revision = 1; 75 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; 76 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; 77 timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; 78 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; 79 timer->func_base = timer->io_base; 80 } else { 81 timer->revision = 2; 82 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; 83 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; 84 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; 85 timer->pend = timer->io_base + 86 _OMAP_TIMER_WRITE_PEND_OFFSET + 87 OMAP_TIMER_V2_FUNC_OFFSET; 88 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; 89 } 90 } 91 92 /* 93 * __omap_dm_timer_enable_posted - enables write posted mode 94 * @timer: pointer to timer instance handle 95 * 96 * Enables the write posted mode for the timer. When posted mode is enabled 97 * writes to certain timer registers are immediately acknowledged by the 98 * internal bus and hence prevents stalling the CPU waiting for the write to 99 * complete. Enabling this feature can improve performance for writing to the 100 * timer registers. 101 */ 102 static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer) 103 { 104 if (timer->posted) 105 return; 106 107 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { 108 timer->posted = OMAP_TIMER_NONPOSTED; 109 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0); 110 return; 111 } 112 113 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 114 OMAP_TIMER_CTRL_POSTED, 0); 115 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; 116 timer->posted = OMAP_TIMER_POSTED; 117 } 118 119 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, 120 int posted, unsigned long rate) 121 { 122 u32 l; 123 124 l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); 125 if (l & OMAP_TIMER_CTRL_ST) { 126 l &= ~0x1; 127 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted); 128 #ifdef CONFIG_ARCH_OMAP2PLUS 129 /* Readback to make sure write has completed */ 130 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); 131 /* 132 * Wait for functional clock period x 3.5 to make sure that 133 * timer is stopped 134 */ 135 udelay(3500000 / rate + 1); 136 #endif 137 } 138 139 /* Ack possibly pending interrupt */ 140 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); 141 } 142 143 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, 144 unsigned int value) 145 { 146 writel_relaxed(value, timer->irq_ena); 147 __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); 148 } 149 150 static inline unsigned int 151 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) 152 { 153 return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted); 154 } 155 156 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, 157 unsigned int value) 158 { 159 writel_relaxed(value, timer->irq_stat); 160 } 161 162 /** 163 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode 164 * @timer: timer pointer over which read operation to perform 165 * @reg: lowest byte holds the register offset 166 * 167 * The posted mode bit is encoded in reg. Note that in posted mode write 168 * pending bit must be checked. Otherwise a read of a non completed write 169 * will produce an error. 170 */ 171 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) 172 { 173 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); 174 return __omap_dm_timer_read(timer, reg, timer->posted); 175 } 176 177 /** 178 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode 179 * @timer: timer pointer over which write operation is to perform 180 * @reg: lowest byte holds the register offset 181 * @value: data to write into the register 182 * 183 * The posted mode bit is encoded in reg. Note that in posted mode the write 184 * pending bit must be checked. Otherwise a write on a register which has a 185 * pending write will be lost. 186 */ 187 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, 188 u32 value) 189 { 190 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); 191 __omap_dm_timer_write(timer, reg, value, timer->posted); 192 } 193 194 static void omap_timer_restore_context(struct omap_dm_timer *timer) 195 { 196 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, 197 timer->context.ocp_cfg, 0); 198 199 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, 200 timer->context.twer); 201 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 202 timer->context.tcrr); 203 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, 204 timer->context.tldr); 205 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, 206 timer->context.tmar); 207 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 208 timer->context.tsicr); 209 writel_relaxed(timer->context.tier, timer->irq_ena); 210 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, 211 timer->context.tclr); 212 } 213 214 static void omap_timer_save_context(struct omap_dm_timer *timer) 215 { 216 timer->context.ocp_cfg = 217 __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); 218 219 timer->context.tclr = 220 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 221 timer->context.twer = 222 omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); 223 timer->context.tldr = 224 omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); 225 timer->context.tmar = 226 omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); 227 timer->context.tier = readl_relaxed(timer->irq_ena); 228 timer->context.tsicr = 229 omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); 230 } 231 232 static int omap_timer_context_notifier(struct notifier_block *nb, 233 unsigned long cmd, void *v) 234 { 235 struct omap_dm_timer *timer; 236 237 timer = container_of(nb, struct omap_dm_timer, nb); 238 239 switch (cmd) { 240 case CPU_CLUSTER_PM_ENTER: 241 if ((timer->capability & OMAP_TIMER_ALWON) || 242 !atomic_read(&timer->enabled)) 243 break; 244 omap_timer_save_context(timer); 245 break; 246 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 247 break; 248 case CPU_CLUSTER_PM_EXIT: 249 if ((timer->capability & OMAP_TIMER_ALWON) || 250 !atomic_read(&timer->enabled)) 251 break; 252 omap_timer_restore_context(timer); 253 break; 254 } 255 256 return NOTIFY_OK; 257 } 258 259 static int omap_dm_timer_reset(struct omap_dm_timer *timer) 260 { 261 u32 l, timeout = 100000; 262 263 if (timer->revision != 1) 264 return -EINVAL; 265 266 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 267 268 do { 269 l = __omap_dm_timer_read(timer, 270 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); 271 } while (!l && timeout--); 272 273 if (!timeout) { 274 dev_err(&timer->pdev->dev, "Timer failed to reset\n"); 275 return -ETIMEDOUT; 276 } 277 278 /* Configure timer for smart-idle mode */ 279 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); 280 l |= 0x2 << 0x3; 281 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); 282 283 timer->posted = 0; 284 285 return 0; 286 } 287 288 static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 289 { 290 int ret; 291 const char *parent_name; 292 struct clk *parent; 293 struct dmtimer_platform_data *pdata; 294 295 if (unlikely(!timer) || IS_ERR(timer->fclk)) 296 return -EINVAL; 297 298 switch (source) { 299 case OMAP_TIMER_SRC_SYS_CLK: 300 parent_name = "timer_sys_ck"; 301 break; 302 case OMAP_TIMER_SRC_32_KHZ: 303 parent_name = "timer_32k_ck"; 304 break; 305 case OMAP_TIMER_SRC_EXT_CLK: 306 parent_name = "timer_ext_ck"; 307 break; 308 default: 309 return -EINVAL; 310 } 311 312 pdata = timer->pdev->dev.platform_data; 313 314 /* 315 * FIXME: Used for OMAP1 devices only because they do not currently 316 * use the clock framework to set the parent clock. To be removed 317 * once OMAP1 migrated to using clock framework for dmtimers 318 */ 319 if (pdata && pdata->set_timer_src) 320 return pdata->set_timer_src(timer->pdev, source); 321 322 #if defined(CONFIG_COMMON_CLK) 323 /* Check if the clock has configurable parents */ 324 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) 325 return 0; 326 #endif 327 328 parent = clk_get(&timer->pdev->dev, parent_name); 329 if (IS_ERR(parent)) { 330 pr_err("%s: %s not found\n", __func__, parent_name); 331 return -EINVAL; 332 } 333 334 ret = clk_set_parent(timer->fclk, parent); 335 if (ret < 0) 336 pr_err("%s: failed to set %s as parent\n", __func__, 337 parent_name); 338 339 clk_put(parent); 340 341 return ret; 342 } 343 344 static void omap_dm_timer_enable(struct omap_dm_timer *timer) 345 { 346 pm_runtime_get_sync(&timer->pdev->dev); 347 } 348 349 static void omap_dm_timer_disable(struct omap_dm_timer *timer) 350 { 351 pm_runtime_put_sync(&timer->pdev->dev); 352 } 353 354 static int omap_dm_timer_prepare(struct omap_dm_timer *timer) 355 { 356 int rc; 357 358 /* 359 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so 360 * do not call clk_get() for these devices. 361 */ 362 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { 363 timer->fclk = clk_get(&timer->pdev->dev, "fck"); 364 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { 365 dev_err(&timer->pdev->dev, ": No fclk handle.\n"); 366 return -EINVAL; 367 } 368 } 369 370 omap_dm_timer_enable(timer); 371 372 if (timer->capability & OMAP_TIMER_NEEDS_RESET) { 373 rc = omap_dm_timer_reset(timer); 374 if (rc) { 375 omap_dm_timer_disable(timer); 376 return rc; 377 } 378 } 379 380 __omap_dm_timer_enable_posted(timer); 381 omap_dm_timer_disable(timer); 382 383 return 0; 384 } 385 386 static inline u32 omap_dm_timer_reserved_systimer(int id) 387 { 388 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; 389 } 390 391 int omap_dm_timer_reserve_systimer(int id) 392 { 393 if (omap_dm_timer_reserved_systimer(id)) 394 return -ENODEV; 395 396 omap_reserved_systimers |= (1 << (id - 1)); 397 398 return 0; 399 } 400 401 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) 402 { 403 struct omap_dm_timer *timer = NULL, *t; 404 struct device_node *np = NULL; 405 unsigned long flags; 406 u32 cap = 0; 407 int id = 0; 408 409 switch (req_type) { 410 case REQUEST_BY_ID: 411 id = *(int *)data; 412 break; 413 case REQUEST_BY_CAP: 414 cap = *(u32 *)data; 415 break; 416 case REQUEST_BY_NODE: 417 np = (struct device_node *)data; 418 break; 419 default: 420 /* REQUEST_ANY */ 421 break; 422 } 423 424 spin_lock_irqsave(&dm_timer_lock, flags); 425 list_for_each_entry(t, &omap_timer_list, node) { 426 if (t->reserved) 427 continue; 428 429 switch (req_type) { 430 case REQUEST_BY_ID: 431 if (id == t->pdev->id) { 432 timer = t; 433 timer->reserved = 1; 434 goto found; 435 } 436 break; 437 case REQUEST_BY_CAP: 438 if (cap == (t->capability & cap)) { 439 /* 440 * If timer is not NULL, we have already found 441 * one timer. But it was not an exact match 442 * because it had more capabilities than what 443 * was required. Therefore, unreserve the last 444 * timer found and see if this one is a better 445 * match. 446 */ 447 if (timer) 448 timer->reserved = 0; 449 timer = t; 450 timer->reserved = 1; 451 452 /* Exit loop early if we find an exact match */ 453 if (t->capability == cap) 454 goto found; 455 } 456 break; 457 case REQUEST_BY_NODE: 458 if (np == t->pdev->dev.of_node) { 459 timer = t; 460 timer->reserved = 1; 461 goto found; 462 } 463 break; 464 default: 465 /* REQUEST_ANY */ 466 timer = t; 467 timer->reserved = 1; 468 goto found; 469 } 470 } 471 found: 472 spin_unlock_irqrestore(&dm_timer_lock, flags); 473 474 if (timer && omap_dm_timer_prepare(timer)) { 475 timer->reserved = 0; 476 timer = NULL; 477 } 478 479 if (!timer) 480 pr_debug("%s: timer request failed!\n", __func__); 481 482 return timer; 483 } 484 485 static struct omap_dm_timer *omap_dm_timer_request(void) 486 { 487 return _omap_dm_timer_request(REQUEST_ANY, NULL); 488 } 489 490 static struct omap_dm_timer *omap_dm_timer_request_specific(int id) 491 { 492 /* Requesting timer by ID is not supported when device tree is used */ 493 if (of_have_populated_dt()) { 494 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", 495 __func__); 496 return NULL; 497 } 498 499 return _omap_dm_timer_request(REQUEST_BY_ID, &id); 500 } 501 502 /** 503 * omap_dm_timer_request_by_cap - Request a timer by capability 504 * @cap: Bit mask of capabilities to match 505 * 506 * Find a timer based upon capabilities bit mask. Callers of this function 507 * should use the definitions found in the plat/dmtimer.h file under the 508 * comment "timer capabilities used in hwmod database". Returns pointer to 509 * timer handle on success and a NULL pointer on failure. 510 */ 511 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) 512 { 513 return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); 514 } 515 516 /** 517 * omap_dm_timer_request_by_node - Request a timer by device-tree node 518 * @np: Pointer to device-tree timer node 519 * 520 * Request a timer based upon a device node pointer. Returns pointer to 521 * timer handle on success and a NULL pointer on failure. 522 */ 523 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) 524 { 525 if (!np) 526 return NULL; 527 528 return _omap_dm_timer_request(REQUEST_BY_NODE, np); 529 } 530 531 static int omap_dm_timer_free(struct omap_dm_timer *timer) 532 { 533 if (unlikely(!timer)) 534 return -EINVAL; 535 536 clk_put(timer->fclk); 537 538 WARN_ON(!timer->reserved); 539 timer->reserved = 0; 540 return 0; 541 } 542 543 int omap_dm_timer_get_irq(struct omap_dm_timer *timer) 544 { 545 if (timer) 546 return timer->irq; 547 return -EINVAL; 548 } 549 550 #if defined(CONFIG_ARCH_OMAP1) 551 #include <mach/hardware.h> 552 553 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 554 { 555 return NULL; 556 } 557 558 /** 559 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 560 * @inputmask: current value of idlect mask 561 */ 562 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 563 { 564 int i = 0; 565 struct omap_dm_timer *timer = NULL; 566 unsigned long flags; 567 568 /* If ARMXOR cannot be idled this function call is unnecessary */ 569 if (!(inputmask & (1 << 1))) 570 return inputmask; 571 572 /* If any active timer is using ARMXOR return modified mask */ 573 spin_lock_irqsave(&dm_timer_lock, flags); 574 list_for_each_entry(timer, &omap_timer_list, node) { 575 u32 l; 576 577 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 578 if (l & OMAP_TIMER_CTRL_ST) { 579 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) 580 inputmask &= ~(1 << 1); 581 else 582 inputmask &= ~(1 << 2); 583 } 584 i++; 585 } 586 spin_unlock_irqrestore(&dm_timer_lock, flags); 587 588 return inputmask; 589 } 590 591 #else 592 593 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 594 { 595 if (timer && !IS_ERR(timer->fclk)) 596 return timer->fclk; 597 return NULL; 598 } 599 600 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 601 { 602 BUG(); 603 604 return 0; 605 } 606 607 #endif 608 609 int omap_dm_timer_trigger(struct omap_dm_timer *timer) 610 { 611 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 612 pr_err("%s: timer not available or enabled.\n", __func__); 613 return -EINVAL; 614 } 615 616 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 617 return 0; 618 } 619 620 static int omap_dm_timer_start(struct omap_dm_timer *timer) 621 { 622 u32 l; 623 624 if (unlikely(!timer)) 625 return -EINVAL; 626 627 omap_dm_timer_enable(timer); 628 629 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 630 if (!(l & OMAP_TIMER_CTRL_ST)) { 631 l |= OMAP_TIMER_CTRL_ST; 632 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 633 } 634 635 return 0; 636 } 637 638 static int omap_dm_timer_stop(struct omap_dm_timer *timer) 639 { 640 unsigned long rate = 0; 641 642 if (unlikely(!timer)) 643 return -EINVAL; 644 645 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) 646 rate = clk_get_rate(timer->fclk); 647 648 __omap_dm_timer_stop(timer, timer->posted, rate); 649 650 omap_dm_timer_disable(timer); 651 return 0; 652 } 653 654 static int omap_dm_timer_set_load(struct omap_dm_timer *timer, 655 unsigned int load) 656 { 657 if (unlikely(!timer)) 658 return -EINVAL; 659 660 omap_dm_timer_enable(timer); 661 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 662 663 omap_dm_timer_disable(timer); 664 return 0; 665 } 666 667 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, 668 unsigned int match) 669 { 670 u32 l; 671 672 if (unlikely(!timer)) 673 return -EINVAL; 674 675 omap_dm_timer_enable(timer); 676 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 677 if (enable) 678 l |= OMAP_TIMER_CTRL_CE; 679 else 680 l &= ~OMAP_TIMER_CTRL_CE; 681 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 682 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 683 684 omap_dm_timer_disable(timer); 685 return 0; 686 } 687 688 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, 689 int toggle, int trigger, int autoreload) 690 { 691 u32 l; 692 693 if (unlikely(!timer)) 694 return -EINVAL; 695 696 omap_dm_timer_enable(timer); 697 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 698 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | 699 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); 700 if (def_on) 701 l |= OMAP_TIMER_CTRL_SCPWM; 702 if (toggle) 703 l |= OMAP_TIMER_CTRL_PT; 704 l |= trigger << 10; 705 if (autoreload) 706 l |= OMAP_TIMER_CTRL_AR; 707 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 708 709 omap_dm_timer_disable(timer); 710 return 0; 711 } 712 713 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) 714 { 715 u32 l; 716 717 if (unlikely(!timer)) 718 return -EINVAL; 719 720 omap_dm_timer_enable(timer); 721 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 722 omap_dm_timer_disable(timer); 723 724 return l; 725 } 726 727 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, 728 int prescaler) 729 { 730 u32 l; 731 732 if (unlikely(!timer) || prescaler < -1 || prescaler > 7) 733 return -EINVAL; 734 735 omap_dm_timer_enable(timer); 736 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 737 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); 738 if (prescaler >= 0) { 739 l |= OMAP_TIMER_CTRL_PRE; 740 l |= prescaler << 2; 741 } 742 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 743 744 omap_dm_timer_disable(timer); 745 return 0; 746 } 747 748 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 749 unsigned int value) 750 { 751 if (unlikely(!timer)) 752 return -EINVAL; 753 754 omap_dm_timer_enable(timer); 755 __omap_dm_timer_int_enable(timer, value); 756 757 omap_dm_timer_disable(timer); 758 return 0; 759 } 760 761 /** 762 * omap_dm_timer_set_int_disable - disable timer interrupts 763 * @timer: pointer to timer handle 764 * @mask: bit mask of interrupts to be disabled 765 * 766 * Disables the specified timer interrupts for a timer. 767 */ 768 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) 769 { 770 u32 l = mask; 771 772 if (unlikely(!timer)) 773 return -EINVAL; 774 775 omap_dm_timer_enable(timer); 776 777 if (timer->revision == 1) 778 l = readl_relaxed(timer->irq_ena) & ~mask; 779 780 writel_relaxed(l, timer->irq_dis); 781 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; 782 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); 783 784 omap_dm_timer_disable(timer); 785 return 0; 786 } 787 788 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 789 { 790 unsigned int l; 791 792 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 793 pr_err("%s: timer not available or enabled.\n", __func__); 794 return 0; 795 } 796 797 l = readl_relaxed(timer->irq_stat); 798 799 return l; 800 } 801 802 static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 803 { 804 if (unlikely(!timer || !atomic_read(&timer->enabled))) 805 return -EINVAL; 806 807 __omap_dm_timer_write_status(timer, value); 808 809 return 0; 810 } 811 812 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 813 { 814 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 815 pr_err("%s: timer not iavailable or enabled.\n", __func__); 816 return 0; 817 } 818 819 return __omap_dm_timer_read_counter(timer, timer->posted); 820 } 821 822 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) 823 { 824 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 825 pr_err("%s: timer not available or enabled.\n", __func__); 826 return -EINVAL; 827 } 828 829 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); 830 831 /* Save the context */ 832 timer->context.tcrr = value; 833 return 0; 834 } 835 836 int omap_dm_timers_active(void) 837 { 838 struct omap_dm_timer *timer; 839 840 list_for_each_entry(timer, &omap_timer_list, node) { 841 if (!timer->reserved) 842 continue; 843 844 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & 845 OMAP_TIMER_CTRL_ST) { 846 return 1; 847 } 848 } 849 return 0; 850 } 851 852 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) 853 { 854 struct omap_dm_timer *timer = dev_get_drvdata(dev); 855 856 atomic_set(&timer->enabled, 0); 857 858 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) 859 return 0; 860 861 omap_timer_save_context(timer); 862 863 return 0; 864 } 865 866 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) 867 { 868 struct omap_dm_timer *timer = dev_get_drvdata(dev); 869 870 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) 871 omap_timer_restore_context(timer); 872 873 atomic_set(&timer->enabled, 1); 874 875 return 0; 876 } 877 878 static const struct dev_pm_ops omap_dm_timer_pm_ops = { 879 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, 880 omap_dm_timer_runtime_resume, NULL) 881 }; 882 883 static const struct of_device_id omap_timer_match[]; 884 885 /** 886 * omap_dm_timer_probe - probe function called for every registered device 887 * @pdev: pointer to current timer platform device 888 * 889 * Called by driver framework at the end of device registration for all 890 * timer devices. 891 */ 892 static int omap_dm_timer_probe(struct platform_device *pdev) 893 { 894 unsigned long flags; 895 struct omap_dm_timer *timer; 896 struct device *dev = &pdev->dev; 897 const struct dmtimer_platform_data *pdata; 898 int ret; 899 900 pdata = of_device_get_match_data(dev); 901 if (!pdata) 902 pdata = dev_get_platdata(dev); 903 else 904 dev->platform_data = (void *)pdata; 905 906 if (!pdata) { 907 dev_err(dev, "%s: no platform data.\n", __func__); 908 return -ENODEV; 909 } 910 911 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); 912 if (!timer) 913 return -ENOMEM; 914 915 timer->irq = platform_get_irq(pdev, 0); 916 if (timer->irq < 0) 917 return timer->irq; 918 919 timer->fclk = ERR_PTR(-ENODEV); 920 timer->io_base = devm_platform_ioremap_resource(pdev, 0); 921 if (IS_ERR(timer->io_base)) 922 return PTR_ERR(timer->io_base); 923 924 platform_set_drvdata(pdev, timer); 925 926 if (dev->of_node) { 927 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) 928 timer->capability |= OMAP_TIMER_ALWON; 929 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) 930 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; 931 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) 932 timer->capability |= OMAP_TIMER_HAS_PWM; 933 if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) 934 timer->capability |= OMAP_TIMER_SECURE; 935 } else { 936 timer->id = pdev->id; 937 timer->capability = pdata->timer_capability; 938 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 939 } 940 941 if (!(timer->capability & OMAP_TIMER_ALWON)) { 942 timer->nb.notifier_call = omap_timer_context_notifier; 943 cpu_pm_register_notifier(&timer->nb); 944 } 945 946 timer->errata = pdata->timer_errata; 947 948 timer->pdev = pdev; 949 950 pm_runtime_enable(dev); 951 952 if (!timer->reserved) { 953 ret = pm_runtime_get_sync(dev); 954 if (ret < 0) { 955 dev_err(dev, "%s: pm_runtime_get_sync failed!\n", 956 __func__); 957 goto err_get_sync; 958 } 959 __omap_dm_timer_init_regs(timer); 960 pm_runtime_put(dev); 961 } 962 963 /* add the timer element to the list */ 964 spin_lock_irqsave(&dm_timer_lock, flags); 965 list_add_tail(&timer->node, &omap_timer_list); 966 spin_unlock_irqrestore(&dm_timer_lock, flags); 967 968 dev_dbg(dev, "Device Probed.\n"); 969 970 return 0; 971 972 err_get_sync: 973 pm_runtime_put_noidle(dev); 974 pm_runtime_disable(dev); 975 return ret; 976 } 977 978 /** 979 * omap_dm_timer_remove - cleanup a registered timer device 980 * @pdev: pointer to current timer platform device 981 * 982 * Called by driver framework whenever a timer device is unregistered. 983 * In addition to freeing platform resources it also deletes the timer 984 * entry from the local list. 985 */ 986 static int omap_dm_timer_remove(struct platform_device *pdev) 987 { 988 struct omap_dm_timer *timer; 989 unsigned long flags; 990 int ret = -EINVAL; 991 992 spin_lock_irqsave(&dm_timer_lock, flags); 993 list_for_each_entry(timer, &omap_timer_list, node) 994 if (!strcmp(dev_name(&timer->pdev->dev), 995 dev_name(&pdev->dev))) { 996 if (!(timer->capability & OMAP_TIMER_ALWON)) 997 cpu_pm_unregister_notifier(&timer->nb); 998 list_del(&timer->node); 999 ret = 0; 1000 break; 1001 } 1002 spin_unlock_irqrestore(&dm_timer_lock, flags); 1003 1004 pm_runtime_disable(&pdev->dev); 1005 1006 return ret; 1007 } 1008 1009 static const struct omap_dm_timer_ops dmtimer_ops = { 1010 .request_by_node = omap_dm_timer_request_by_node, 1011 .request_specific = omap_dm_timer_request_specific, 1012 .request = omap_dm_timer_request, 1013 .set_source = omap_dm_timer_set_source, 1014 .get_irq = omap_dm_timer_get_irq, 1015 .set_int_enable = omap_dm_timer_set_int_enable, 1016 .set_int_disable = omap_dm_timer_set_int_disable, 1017 .free = omap_dm_timer_free, 1018 .enable = omap_dm_timer_enable, 1019 .disable = omap_dm_timer_disable, 1020 .get_fclk = omap_dm_timer_get_fclk, 1021 .start = omap_dm_timer_start, 1022 .stop = omap_dm_timer_stop, 1023 .set_load = omap_dm_timer_set_load, 1024 .set_match = omap_dm_timer_set_match, 1025 .set_pwm = omap_dm_timer_set_pwm, 1026 .get_pwm_status = omap_dm_timer_get_pwm_status, 1027 .set_prescaler = omap_dm_timer_set_prescaler, 1028 .read_counter = omap_dm_timer_read_counter, 1029 .write_counter = omap_dm_timer_write_counter, 1030 .read_status = omap_dm_timer_read_status, 1031 .write_status = omap_dm_timer_write_status, 1032 }; 1033 1034 static const struct dmtimer_platform_data omap3plus_pdata = { 1035 .timer_errata = OMAP_TIMER_ERRATA_I103_I767, 1036 .timer_ops = &dmtimer_ops, 1037 }; 1038 1039 static const struct dmtimer_platform_data am6_pdata = { 1040 .timer_ops = &dmtimer_ops, 1041 }; 1042 1043 static const struct of_device_id omap_timer_match[] = { 1044 { 1045 .compatible = "ti,omap2420-timer", 1046 }, 1047 { 1048 .compatible = "ti,omap3430-timer", 1049 .data = &omap3plus_pdata, 1050 }, 1051 { 1052 .compatible = "ti,omap4430-timer", 1053 .data = &omap3plus_pdata, 1054 }, 1055 { 1056 .compatible = "ti,omap5430-timer", 1057 .data = &omap3plus_pdata, 1058 }, 1059 { 1060 .compatible = "ti,am335x-timer", 1061 .data = &omap3plus_pdata, 1062 }, 1063 { 1064 .compatible = "ti,am335x-timer-1ms", 1065 .data = &omap3plus_pdata, 1066 }, 1067 { 1068 .compatible = "ti,dm816-timer", 1069 .data = &omap3plus_pdata, 1070 }, 1071 { 1072 .compatible = "ti,am654-timer", 1073 .data = &am6_pdata, 1074 }, 1075 {}, 1076 }; 1077 MODULE_DEVICE_TABLE(of, omap_timer_match); 1078 1079 static struct platform_driver omap_dm_timer_driver = { 1080 .probe = omap_dm_timer_probe, 1081 .remove = omap_dm_timer_remove, 1082 .driver = { 1083 .name = "omap_timer", 1084 .of_match_table = of_match_ptr(omap_timer_match), 1085 .pm = &omap_dm_timer_pm_ops, 1086 }, 1087 }; 1088 1089 module_platform_driver(omap_dm_timer_driver); 1090 1091 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); 1092 MODULE_LICENSE("GPL"); 1093 MODULE_AUTHOR("Texas Instruments Inc"); 1094