1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * linux/arch/arm/plat-omap/dmtimer.c 4 * 5 * OMAP Dual-Mode Timers 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 8 * Tarun Kanti DebBarma <tarun.kanti@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * dmtimer adaptation to platform_driver. 12 * 13 * Copyright (C) 2005 Nokia Corporation 14 * OMAP2 support by Juha Yrjola 15 * API improvements and OMAP2 clock framework support by Timo Teras 16 * 17 * Copyright (C) 2009 Texas Instruments 18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/cpu_pm.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/device.h> 27 #include <linux/err.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/platform_device.h> 32 #include <linux/platform_data/dmtimer-omap.h> 33 34 #include <clocksource/timer-ti-dm.h> 35 36 static u32 omap_reserved_systimers; 37 static LIST_HEAD(omap_timer_list); 38 static DEFINE_SPINLOCK(dm_timer_lock); 39 40 enum { 41 REQUEST_ANY = 0, 42 REQUEST_BY_ID, 43 REQUEST_BY_CAP, 44 REQUEST_BY_NODE, 45 }; 46 47 /** 48 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode 49 * @timer: timer pointer over which read operation to perform 50 * @reg: lowest byte holds the register offset 51 * 52 * The posted mode bit is encoded in reg. Note that in posted mode write 53 * pending bit must be checked. Otherwise a read of a non completed write 54 * will produce an error. 55 */ 56 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) 57 { 58 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); 59 return __omap_dm_timer_read(timer, reg, timer->posted); 60 } 61 62 /** 63 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode 64 * @timer: timer pointer over which write operation is to perform 65 * @reg: lowest byte holds the register offset 66 * @value: data to write into the register 67 * 68 * The posted mode bit is encoded in reg. Note that in posted mode the write 69 * pending bit must be checked. Otherwise a write on a register which has a 70 * pending write will be lost. 71 */ 72 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, 73 u32 value) 74 { 75 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); 76 __omap_dm_timer_write(timer, reg, value, timer->posted); 77 } 78 79 static void omap_timer_restore_context(struct omap_dm_timer *timer) 80 { 81 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, 82 timer->context.twer); 83 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 84 timer->context.tcrr); 85 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, 86 timer->context.tldr); 87 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, 88 timer->context.tmar); 89 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 90 timer->context.tsicr); 91 writel_relaxed(timer->context.tier, timer->irq_ena); 92 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, 93 timer->context.tclr); 94 } 95 96 static void omap_timer_save_context(struct omap_dm_timer *timer) 97 { 98 timer->context.tclr = 99 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 100 timer->context.twer = 101 omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); 102 timer->context.tldr = 103 omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); 104 timer->context.tmar = 105 omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); 106 timer->context.tier = readl_relaxed(timer->irq_ena); 107 timer->context.tsicr = 108 omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); 109 } 110 111 static int omap_timer_context_notifier(struct notifier_block *nb, 112 unsigned long cmd, void *v) 113 { 114 struct omap_dm_timer *timer; 115 116 timer = container_of(nb, struct omap_dm_timer, nb); 117 118 switch (cmd) { 119 case CPU_CLUSTER_PM_ENTER: 120 if ((timer->capability & OMAP_TIMER_ALWON) || 121 !atomic_read(&timer->enabled)) 122 break; 123 omap_timer_save_context(timer); 124 break; 125 case CPU_CLUSTER_PM_ENTER_FAILED: 126 case CPU_CLUSTER_PM_EXIT: 127 if ((timer->capability & OMAP_TIMER_ALWON) || 128 !atomic_read(&timer->enabled)) 129 break; 130 omap_timer_restore_context(timer); 131 break; 132 } 133 134 return NOTIFY_OK; 135 } 136 137 static int omap_dm_timer_reset(struct omap_dm_timer *timer) 138 { 139 u32 l, timeout = 100000; 140 141 if (timer->revision != 1) 142 return -EINVAL; 143 144 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 145 146 do { 147 l = __omap_dm_timer_read(timer, 148 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); 149 } while (!l && timeout--); 150 151 if (!timeout) { 152 dev_err(&timer->pdev->dev, "Timer failed to reset\n"); 153 return -ETIMEDOUT; 154 } 155 156 /* Configure timer for smart-idle mode */ 157 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); 158 l |= 0x2 << 0x3; 159 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); 160 161 timer->posted = 0; 162 163 return 0; 164 } 165 166 static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer) 167 { 168 int ret; 169 struct clk *parent; 170 171 /* 172 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so 173 * do not call clk_get() for these devices. 174 */ 175 if (!timer->fclk) 176 return -ENODEV; 177 178 parent = clk_get(&timer->pdev->dev, NULL); 179 if (IS_ERR(parent)) 180 return -ENODEV; 181 182 /* Bail out if both clocks point to fck */ 183 if (clk_is_match(parent, timer->fclk)) 184 return 0; 185 186 ret = clk_set_parent(timer->fclk, parent); 187 if (ret < 0) 188 pr_err("%s: failed to set parent\n", __func__); 189 190 clk_put(parent); 191 192 return ret; 193 } 194 195 static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 196 { 197 int ret; 198 const char *parent_name; 199 struct clk *parent; 200 struct dmtimer_platform_data *pdata; 201 202 if (unlikely(!timer) || IS_ERR(timer->fclk)) 203 return -EINVAL; 204 205 switch (source) { 206 case OMAP_TIMER_SRC_SYS_CLK: 207 parent_name = "timer_sys_ck"; 208 break; 209 case OMAP_TIMER_SRC_32_KHZ: 210 parent_name = "timer_32k_ck"; 211 break; 212 case OMAP_TIMER_SRC_EXT_CLK: 213 parent_name = "timer_ext_ck"; 214 break; 215 default: 216 return -EINVAL; 217 } 218 219 pdata = timer->pdev->dev.platform_data; 220 221 /* 222 * FIXME: Used for OMAP1 devices only because they do not currently 223 * use the clock framework to set the parent clock. To be removed 224 * once OMAP1 migrated to using clock framework for dmtimers 225 */ 226 if (pdata && pdata->set_timer_src) 227 return pdata->set_timer_src(timer->pdev, source); 228 229 #if defined(CONFIG_COMMON_CLK) 230 /* Check if the clock has configurable parents */ 231 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) 232 return 0; 233 #endif 234 235 parent = clk_get(&timer->pdev->dev, parent_name); 236 if (IS_ERR(parent)) { 237 pr_err("%s: %s not found\n", __func__, parent_name); 238 return -EINVAL; 239 } 240 241 ret = clk_set_parent(timer->fclk, parent); 242 if (ret < 0) 243 pr_err("%s: failed to set %s as parent\n", __func__, 244 parent_name); 245 246 clk_put(parent); 247 248 return ret; 249 } 250 251 static void omap_dm_timer_enable(struct omap_dm_timer *timer) 252 { 253 pm_runtime_get_sync(&timer->pdev->dev); 254 } 255 256 static void omap_dm_timer_disable(struct omap_dm_timer *timer) 257 { 258 pm_runtime_put_sync(&timer->pdev->dev); 259 } 260 261 static int omap_dm_timer_prepare(struct omap_dm_timer *timer) 262 { 263 int rc; 264 265 /* 266 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so 267 * do not call clk_get() for these devices. 268 */ 269 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { 270 timer->fclk = clk_get(&timer->pdev->dev, "fck"); 271 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { 272 dev_err(&timer->pdev->dev, ": No fclk handle.\n"); 273 return -EINVAL; 274 } 275 } 276 277 omap_dm_timer_enable(timer); 278 279 if (timer->capability & OMAP_TIMER_NEEDS_RESET) { 280 rc = omap_dm_timer_reset(timer); 281 if (rc) { 282 omap_dm_timer_disable(timer); 283 return rc; 284 } 285 } 286 287 __omap_dm_timer_enable_posted(timer); 288 omap_dm_timer_disable(timer); 289 290 rc = omap_dm_timer_of_set_source(timer); 291 if (rc == -ENODEV) 292 return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 293 294 return rc; 295 } 296 297 static inline u32 omap_dm_timer_reserved_systimer(int id) 298 { 299 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; 300 } 301 302 int omap_dm_timer_reserve_systimer(int id) 303 { 304 if (omap_dm_timer_reserved_systimer(id)) 305 return -ENODEV; 306 307 omap_reserved_systimers |= (1 << (id - 1)); 308 309 return 0; 310 } 311 312 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) 313 { 314 struct omap_dm_timer *timer = NULL, *t; 315 struct device_node *np = NULL; 316 unsigned long flags; 317 u32 cap = 0; 318 int id = 0; 319 320 switch (req_type) { 321 case REQUEST_BY_ID: 322 id = *(int *)data; 323 break; 324 case REQUEST_BY_CAP: 325 cap = *(u32 *)data; 326 break; 327 case REQUEST_BY_NODE: 328 np = (struct device_node *)data; 329 break; 330 default: 331 /* REQUEST_ANY */ 332 break; 333 } 334 335 spin_lock_irqsave(&dm_timer_lock, flags); 336 list_for_each_entry(t, &omap_timer_list, node) { 337 if (t->reserved) 338 continue; 339 340 switch (req_type) { 341 case REQUEST_BY_ID: 342 if (id == t->pdev->id) { 343 timer = t; 344 timer->reserved = 1; 345 goto found; 346 } 347 break; 348 case REQUEST_BY_CAP: 349 if (cap == (t->capability & cap)) { 350 /* 351 * If timer is not NULL, we have already found 352 * one timer. But it was not an exact match 353 * because it had more capabilities than what 354 * was required. Therefore, unreserve the last 355 * timer found and see if this one is a better 356 * match. 357 */ 358 if (timer) 359 timer->reserved = 0; 360 timer = t; 361 timer->reserved = 1; 362 363 /* Exit loop early if we find an exact match */ 364 if (t->capability == cap) 365 goto found; 366 } 367 break; 368 case REQUEST_BY_NODE: 369 if (np == t->pdev->dev.of_node) { 370 timer = t; 371 timer->reserved = 1; 372 goto found; 373 } 374 break; 375 default: 376 /* REQUEST_ANY */ 377 timer = t; 378 timer->reserved = 1; 379 goto found; 380 } 381 } 382 found: 383 spin_unlock_irqrestore(&dm_timer_lock, flags); 384 385 if (timer && omap_dm_timer_prepare(timer)) { 386 timer->reserved = 0; 387 timer = NULL; 388 } 389 390 if (!timer) 391 pr_debug("%s: timer request failed!\n", __func__); 392 393 return timer; 394 } 395 396 static struct omap_dm_timer *omap_dm_timer_request(void) 397 { 398 return _omap_dm_timer_request(REQUEST_ANY, NULL); 399 } 400 401 static struct omap_dm_timer *omap_dm_timer_request_specific(int id) 402 { 403 /* Requesting timer by ID is not supported when device tree is used */ 404 if (of_have_populated_dt()) { 405 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", 406 __func__); 407 return NULL; 408 } 409 410 return _omap_dm_timer_request(REQUEST_BY_ID, &id); 411 } 412 413 /** 414 * omap_dm_timer_request_by_cap - Request a timer by capability 415 * @cap: Bit mask of capabilities to match 416 * 417 * Find a timer based upon capabilities bit mask. Callers of this function 418 * should use the definitions found in the plat/dmtimer.h file under the 419 * comment "timer capabilities used in hwmod database". Returns pointer to 420 * timer handle on success and a NULL pointer on failure. 421 */ 422 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) 423 { 424 return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); 425 } 426 427 /** 428 * omap_dm_timer_request_by_node - Request a timer by device-tree node 429 * @np: Pointer to device-tree timer node 430 * 431 * Request a timer based upon a device node pointer. Returns pointer to 432 * timer handle on success and a NULL pointer on failure. 433 */ 434 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) 435 { 436 if (!np) 437 return NULL; 438 439 return _omap_dm_timer_request(REQUEST_BY_NODE, np); 440 } 441 442 static int omap_dm_timer_free(struct omap_dm_timer *timer) 443 { 444 if (unlikely(!timer)) 445 return -EINVAL; 446 447 clk_put(timer->fclk); 448 449 WARN_ON(!timer->reserved); 450 timer->reserved = 0; 451 return 0; 452 } 453 454 int omap_dm_timer_get_irq(struct omap_dm_timer *timer) 455 { 456 if (timer) 457 return timer->irq; 458 return -EINVAL; 459 } 460 461 #if defined(CONFIG_ARCH_OMAP1) 462 #include <mach/hardware.h> 463 464 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 465 { 466 return NULL; 467 } 468 469 /** 470 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 471 * @inputmask: current value of idlect mask 472 */ 473 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 474 { 475 int i = 0; 476 struct omap_dm_timer *timer = NULL; 477 unsigned long flags; 478 479 /* If ARMXOR cannot be idled this function call is unnecessary */ 480 if (!(inputmask & (1 << 1))) 481 return inputmask; 482 483 /* If any active timer is using ARMXOR return modified mask */ 484 spin_lock_irqsave(&dm_timer_lock, flags); 485 list_for_each_entry(timer, &omap_timer_list, node) { 486 u32 l; 487 488 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 489 if (l & OMAP_TIMER_CTRL_ST) { 490 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) 491 inputmask &= ~(1 << 1); 492 else 493 inputmask &= ~(1 << 2); 494 } 495 i++; 496 } 497 spin_unlock_irqrestore(&dm_timer_lock, flags); 498 499 return inputmask; 500 } 501 502 #else 503 504 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 505 { 506 if (timer && !IS_ERR(timer->fclk)) 507 return timer->fclk; 508 return NULL; 509 } 510 511 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 512 { 513 BUG(); 514 515 return 0; 516 } 517 518 #endif 519 520 int omap_dm_timer_trigger(struct omap_dm_timer *timer) 521 { 522 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 523 pr_err("%s: timer not available or enabled.\n", __func__); 524 return -EINVAL; 525 } 526 527 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 528 return 0; 529 } 530 531 static int omap_dm_timer_start(struct omap_dm_timer *timer) 532 { 533 u32 l; 534 535 if (unlikely(!timer)) 536 return -EINVAL; 537 538 omap_dm_timer_enable(timer); 539 540 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 541 if (!(l & OMAP_TIMER_CTRL_ST)) { 542 l |= OMAP_TIMER_CTRL_ST; 543 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 544 } 545 546 return 0; 547 } 548 549 static int omap_dm_timer_stop(struct omap_dm_timer *timer) 550 { 551 unsigned long rate = 0; 552 553 if (unlikely(!timer)) 554 return -EINVAL; 555 556 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) 557 rate = clk_get_rate(timer->fclk); 558 559 __omap_dm_timer_stop(timer, timer->posted, rate); 560 561 omap_dm_timer_disable(timer); 562 return 0; 563 } 564 565 static int omap_dm_timer_set_load(struct omap_dm_timer *timer, 566 unsigned int load) 567 { 568 if (unlikely(!timer)) 569 return -EINVAL; 570 571 omap_dm_timer_enable(timer); 572 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 573 574 omap_dm_timer_disable(timer); 575 return 0; 576 } 577 578 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, 579 unsigned int match) 580 { 581 u32 l; 582 583 if (unlikely(!timer)) 584 return -EINVAL; 585 586 omap_dm_timer_enable(timer); 587 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 588 if (enable) 589 l |= OMAP_TIMER_CTRL_CE; 590 else 591 l &= ~OMAP_TIMER_CTRL_CE; 592 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 593 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 594 595 omap_dm_timer_disable(timer); 596 return 0; 597 } 598 599 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, 600 int toggle, int trigger, int autoreload) 601 { 602 u32 l; 603 604 if (unlikely(!timer)) 605 return -EINVAL; 606 607 omap_dm_timer_enable(timer); 608 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 609 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | 610 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); 611 if (def_on) 612 l |= OMAP_TIMER_CTRL_SCPWM; 613 if (toggle) 614 l |= OMAP_TIMER_CTRL_PT; 615 l |= trigger << 10; 616 if (autoreload) 617 l |= OMAP_TIMER_CTRL_AR; 618 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 619 620 omap_dm_timer_disable(timer); 621 return 0; 622 } 623 624 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) 625 { 626 u32 l; 627 628 if (unlikely(!timer)) 629 return -EINVAL; 630 631 omap_dm_timer_enable(timer); 632 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 633 omap_dm_timer_disable(timer); 634 635 return l; 636 } 637 638 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, 639 int prescaler) 640 { 641 u32 l; 642 643 if (unlikely(!timer) || prescaler < -1 || prescaler > 7) 644 return -EINVAL; 645 646 omap_dm_timer_enable(timer); 647 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 648 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); 649 if (prescaler >= 0) { 650 l |= OMAP_TIMER_CTRL_PRE; 651 l |= prescaler << 2; 652 } 653 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 654 655 omap_dm_timer_disable(timer); 656 return 0; 657 } 658 659 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 660 unsigned int value) 661 { 662 if (unlikely(!timer)) 663 return -EINVAL; 664 665 omap_dm_timer_enable(timer); 666 __omap_dm_timer_int_enable(timer, value); 667 668 omap_dm_timer_disable(timer); 669 return 0; 670 } 671 672 /** 673 * omap_dm_timer_set_int_disable - disable timer interrupts 674 * @timer: pointer to timer handle 675 * @mask: bit mask of interrupts to be disabled 676 * 677 * Disables the specified timer interrupts for a timer. 678 */ 679 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) 680 { 681 u32 l = mask; 682 683 if (unlikely(!timer)) 684 return -EINVAL; 685 686 omap_dm_timer_enable(timer); 687 688 if (timer->revision == 1) 689 l = readl_relaxed(timer->irq_ena) & ~mask; 690 691 writel_relaxed(l, timer->irq_dis); 692 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; 693 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); 694 695 omap_dm_timer_disable(timer); 696 return 0; 697 } 698 699 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 700 { 701 unsigned int l; 702 703 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 704 pr_err("%s: timer not available or enabled.\n", __func__); 705 return 0; 706 } 707 708 l = readl_relaxed(timer->irq_stat); 709 710 return l; 711 } 712 713 static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 714 { 715 if (unlikely(!timer || !atomic_read(&timer->enabled))) 716 return -EINVAL; 717 718 __omap_dm_timer_write_status(timer, value); 719 720 return 0; 721 } 722 723 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 724 { 725 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 726 pr_err("%s: timer not iavailable or enabled.\n", __func__); 727 return 0; 728 } 729 730 return __omap_dm_timer_read_counter(timer, timer->posted); 731 } 732 733 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) 734 { 735 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 736 pr_err("%s: timer not available or enabled.\n", __func__); 737 return -EINVAL; 738 } 739 740 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); 741 742 /* Save the context */ 743 timer->context.tcrr = value; 744 return 0; 745 } 746 747 int omap_dm_timers_active(void) 748 { 749 struct omap_dm_timer *timer; 750 751 list_for_each_entry(timer, &omap_timer_list, node) { 752 if (!timer->reserved) 753 continue; 754 755 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & 756 OMAP_TIMER_CTRL_ST) { 757 return 1; 758 } 759 } 760 return 0; 761 } 762 763 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) 764 { 765 struct omap_dm_timer *timer = dev_get_drvdata(dev); 766 767 atomic_set(&timer->enabled, 0); 768 769 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) 770 return 0; 771 772 omap_timer_save_context(timer); 773 774 return 0; 775 } 776 777 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) 778 { 779 struct omap_dm_timer *timer = dev_get_drvdata(dev); 780 781 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) 782 omap_timer_restore_context(timer); 783 784 atomic_set(&timer->enabled, 1); 785 786 return 0; 787 } 788 789 static const struct dev_pm_ops omap_dm_timer_pm_ops = { 790 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, 791 omap_dm_timer_runtime_resume, NULL) 792 }; 793 794 static const struct of_device_id omap_timer_match[]; 795 796 /** 797 * omap_dm_timer_probe - probe function called for every registered device 798 * @pdev: pointer to current timer platform device 799 * 800 * Called by driver framework at the end of device registration for all 801 * timer devices. 802 */ 803 static int omap_dm_timer_probe(struct platform_device *pdev) 804 { 805 unsigned long flags; 806 struct omap_dm_timer *timer; 807 struct device *dev = &pdev->dev; 808 const struct dmtimer_platform_data *pdata; 809 int ret; 810 811 pdata = of_device_get_match_data(dev); 812 if (!pdata) 813 pdata = dev_get_platdata(dev); 814 else 815 dev->platform_data = (void *)pdata; 816 817 if (!pdata) { 818 dev_err(dev, "%s: no platform data.\n", __func__); 819 return -ENODEV; 820 } 821 822 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); 823 if (!timer) 824 return -ENOMEM; 825 826 timer->irq = platform_get_irq(pdev, 0); 827 if (timer->irq < 0) 828 return timer->irq; 829 830 timer->fclk = ERR_PTR(-ENODEV); 831 timer->io_base = devm_platform_ioremap_resource(pdev, 0); 832 if (IS_ERR(timer->io_base)) 833 return PTR_ERR(timer->io_base); 834 835 platform_set_drvdata(pdev, timer); 836 837 if (dev->of_node) { 838 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) 839 timer->capability |= OMAP_TIMER_ALWON; 840 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) 841 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; 842 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) 843 timer->capability |= OMAP_TIMER_HAS_PWM; 844 if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) 845 timer->capability |= OMAP_TIMER_SECURE; 846 } else { 847 timer->id = pdev->id; 848 timer->capability = pdata->timer_capability; 849 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 850 } 851 852 if (!(timer->capability & OMAP_TIMER_ALWON)) { 853 timer->nb.notifier_call = omap_timer_context_notifier; 854 cpu_pm_register_notifier(&timer->nb); 855 } 856 857 if (pdata) 858 timer->errata = pdata->timer_errata; 859 860 timer->pdev = pdev; 861 862 pm_runtime_enable(dev); 863 864 if (!timer->reserved) { 865 ret = pm_runtime_get_sync(dev); 866 if (ret < 0) { 867 dev_err(dev, "%s: pm_runtime_get_sync failed!\n", 868 __func__); 869 goto err_get_sync; 870 } 871 __omap_dm_timer_init_regs(timer); 872 pm_runtime_put(dev); 873 } 874 875 /* add the timer element to the list */ 876 spin_lock_irqsave(&dm_timer_lock, flags); 877 list_add_tail(&timer->node, &omap_timer_list); 878 spin_unlock_irqrestore(&dm_timer_lock, flags); 879 880 dev_dbg(dev, "Device Probed.\n"); 881 882 return 0; 883 884 err_get_sync: 885 pm_runtime_put_noidle(dev); 886 pm_runtime_disable(dev); 887 return ret; 888 } 889 890 /** 891 * omap_dm_timer_remove - cleanup a registered timer device 892 * @pdev: pointer to current timer platform device 893 * 894 * Called by driver framework whenever a timer device is unregistered. 895 * In addition to freeing platform resources it also deletes the timer 896 * entry from the local list. 897 */ 898 static int omap_dm_timer_remove(struct platform_device *pdev) 899 { 900 struct omap_dm_timer *timer; 901 unsigned long flags; 902 int ret = -EINVAL; 903 904 spin_lock_irqsave(&dm_timer_lock, flags); 905 list_for_each_entry(timer, &omap_timer_list, node) 906 if (!strcmp(dev_name(&timer->pdev->dev), 907 dev_name(&pdev->dev))) { 908 if (!(timer->capability & OMAP_TIMER_ALWON)) 909 cpu_pm_unregister_notifier(&timer->nb); 910 list_del(&timer->node); 911 ret = 0; 912 break; 913 } 914 spin_unlock_irqrestore(&dm_timer_lock, flags); 915 916 pm_runtime_disable(&pdev->dev); 917 918 return ret; 919 } 920 921 static const struct omap_dm_timer_ops dmtimer_ops = { 922 .request_by_node = omap_dm_timer_request_by_node, 923 .request_specific = omap_dm_timer_request_specific, 924 .request = omap_dm_timer_request, 925 .set_source = omap_dm_timer_set_source, 926 .get_irq = omap_dm_timer_get_irq, 927 .set_int_enable = omap_dm_timer_set_int_enable, 928 .set_int_disable = omap_dm_timer_set_int_disable, 929 .free = omap_dm_timer_free, 930 .enable = omap_dm_timer_enable, 931 .disable = omap_dm_timer_disable, 932 .get_fclk = omap_dm_timer_get_fclk, 933 .start = omap_dm_timer_start, 934 .stop = omap_dm_timer_stop, 935 .set_load = omap_dm_timer_set_load, 936 .set_match = omap_dm_timer_set_match, 937 .set_pwm = omap_dm_timer_set_pwm, 938 .get_pwm_status = omap_dm_timer_get_pwm_status, 939 .set_prescaler = omap_dm_timer_set_prescaler, 940 .read_counter = omap_dm_timer_read_counter, 941 .write_counter = omap_dm_timer_write_counter, 942 .read_status = omap_dm_timer_read_status, 943 .write_status = omap_dm_timer_write_status, 944 }; 945 946 static const struct dmtimer_platform_data omap3plus_pdata = { 947 .timer_errata = OMAP_TIMER_ERRATA_I103_I767, 948 .timer_ops = &dmtimer_ops, 949 }; 950 951 static const struct of_device_id omap_timer_match[] = { 952 { 953 .compatible = "ti,omap2420-timer", 954 }, 955 { 956 .compatible = "ti,omap3430-timer", 957 .data = &omap3plus_pdata, 958 }, 959 { 960 .compatible = "ti,omap4430-timer", 961 .data = &omap3plus_pdata, 962 }, 963 { 964 .compatible = "ti,omap5430-timer", 965 .data = &omap3plus_pdata, 966 }, 967 { 968 .compatible = "ti,am335x-timer", 969 .data = &omap3plus_pdata, 970 }, 971 { 972 .compatible = "ti,am335x-timer-1ms", 973 .data = &omap3plus_pdata, 974 }, 975 { 976 .compatible = "ti,dm816-timer", 977 .data = &omap3plus_pdata, 978 }, 979 {}, 980 }; 981 MODULE_DEVICE_TABLE(of, omap_timer_match); 982 983 static struct platform_driver omap_dm_timer_driver = { 984 .probe = omap_dm_timer_probe, 985 .remove = omap_dm_timer_remove, 986 .driver = { 987 .name = "omap_timer", 988 .of_match_table = of_match_ptr(omap_timer_match), 989 .pm = &omap_dm_timer_pm_ops, 990 }, 991 }; 992 993 module_platform_driver(omap_dm_timer_driver); 994 995 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); 996 MODULE_LICENSE("GPL"); 997 MODULE_AUTHOR("Texas Instruments Inc"); 998