1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/clk.h> 3 #include <linux/clocksource.h> 4 #include <linux/clockchips.h> 5 #include <linux/interrupt.h> 6 #include <linux/io.h> 7 #include <linux/iopoll.h> 8 #include <linux/err.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_irq.h> 12 #include <linux/sched_clock.h> 13 14 #include <linux/clk/clk-conf.h> 15 16 #include <clocksource/timer-ti-dm.h> 17 #include <dt-bindings/bus/ti-sysc.h> 18 19 /* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */ 20 #define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \ 21 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE) 22 #define DMTIMER_TYPE1_DISABLE (SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE) 23 #define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2) 24 #define DMTIMER_RESET_WAIT 100000 25 26 #define DMTIMER_INST_DONT_CARE ~0U 27 28 static int counter_32k; 29 static u32 clocksource; 30 static u32 clockevent; 31 32 /* 33 * Subset of the timer registers we use. Note that the register offsets 34 * depend on the timer revision detected. 35 */ 36 struct dmtimer_systimer { 37 void __iomem *base; 38 u8 sysc; 39 u8 irq_stat; 40 u8 irq_ena; 41 u8 pend; 42 u8 load; 43 u8 counter; 44 u8 ctrl; 45 u8 wakeup; 46 u8 ifctrl; 47 struct clk *fck; 48 struct clk *ick; 49 unsigned long rate; 50 }; 51 52 struct dmtimer_clockevent { 53 struct clock_event_device dev; 54 struct dmtimer_systimer t; 55 u32 period; 56 }; 57 58 struct dmtimer_clocksource { 59 struct clocksource dev; 60 struct dmtimer_systimer t; 61 unsigned int loadval; 62 }; 63 64 /* Assumes v1 ip if bits [31:16] are zero */ 65 static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t) 66 { 67 u32 tidr = readl_relaxed(t->base); 68 69 return !(tidr >> 16); 70 } 71 72 static void dmtimer_systimer_enable(struct dmtimer_systimer *t) 73 { 74 u32 val; 75 76 if (dmtimer_systimer_revision1(t)) 77 val = DMTIMER_TYPE1_ENABLE; 78 else 79 val = DMTIMER_TYPE2_ENABLE; 80 81 writel_relaxed(val, t->base + t->sysc); 82 } 83 84 static void dmtimer_systimer_disable(struct dmtimer_systimer *t) 85 { 86 if (!dmtimer_systimer_revision1(t)) 87 return; 88 89 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc); 90 } 91 92 static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t) 93 { 94 void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET; 95 int ret; 96 u32 l; 97 98 dmtimer_systimer_enable(t); 99 writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl); 100 ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100, 101 DMTIMER_RESET_WAIT); 102 103 return ret; 104 } 105 106 /* Note we must use io_base instead of func_base for type2 OCP regs */ 107 static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t) 108 { 109 void __iomem *sysc = t->base + t->sysc; 110 u32 l; 111 112 dmtimer_systimer_enable(t); 113 l = readl_relaxed(sysc); 114 l |= BIT(0); 115 writel_relaxed(l, sysc); 116 117 return readl_poll_timeout_atomic(sysc, l, !(l & BIT(0)), 100, 118 DMTIMER_RESET_WAIT); 119 } 120 121 static int __init dmtimer_systimer_reset(struct dmtimer_systimer *t) 122 { 123 int ret; 124 125 if (dmtimer_systimer_revision1(t)) 126 ret = dmtimer_systimer_type1_reset(t); 127 else 128 ret = dmtimer_systimer_type2_reset(t); 129 if (ret < 0) { 130 pr_err("%s failed with %i\n", __func__, ret); 131 132 return ret; 133 } 134 135 return 0; 136 } 137 138 static const struct of_device_id counter_match_table[] = { 139 { .compatible = "ti,omap-counter32k" }, 140 { /* Sentinel */ }, 141 }; 142 143 /* 144 * Check if the SoC als has a usable working 32 KiHz counter. The 32 KiHz 145 * counter is handled by timer-ti-32k, but we need to detect it as it 146 * affects the preferred dmtimer system timer configuration. There is 147 * typically no use for a dmtimer clocksource if the 32 KiHz counter is 148 * present, except on am437x as described below. 149 */ 150 static void __init dmtimer_systimer_check_counter32k(void) 151 { 152 struct device_node *np; 153 154 if (counter_32k) 155 return; 156 157 np = of_find_matching_node(NULL, counter_match_table); 158 if (!np) { 159 counter_32k = -ENODEV; 160 161 return; 162 } 163 164 if (of_device_is_available(np)) 165 counter_32k = 1; 166 else 167 counter_32k = -ENODEV; 168 169 of_node_put(np); 170 } 171 172 static const struct of_device_id dmtimer_match_table[] = { 173 { .compatible = "ti,omap2420-timer", }, 174 { .compatible = "ti,omap3430-timer", }, 175 { .compatible = "ti,omap4430-timer", }, 176 { .compatible = "ti,omap5430-timer", }, 177 { .compatible = "ti,am335x-timer", }, 178 { .compatible = "ti,am335x-timer-1ms", }, 179 { .compatible = "ti,dm814-timer", }, 180 { .compatible = "ti,dm816-timer", }, 181 { /* Sentinel */ }, 182 }; 183 184 /* 185 * Checks that system timers are configured to not reset and idle during 186 * the generic timer-ti-dm device driver probe. And that the system timer 187 * source clocks are properly configured. Also, let's not hog any DSP and 188 * PWM capable timers unnecessarily as system timers. 189 */ 190 static bool __init dmtimer_is_preferred(struct device_node *np) 191 { 192 if (!of_device_is_available(np)) 193 return false; 194 195 if (!of_property_read_bool(np->parent, 196 "ti,no-reset-on-init")) 197 return false; 198 199 if (!of_property_read_bool(np->parent, "ti,no-idle")) 200 return false; 201 202 /* Secure gptimer12 is always clocked with a fixed source */ 203 if (!of_property_read_bool(np, "ti,timer-secure")) { 204 if (!of_property_read_bool(np, "assigned-clocks")) 205 return false; 206 207 if (!of_property_read_bool(np, "assigned-clock-parents")) 208 return false; 209 } 210 211 if (of_property_read_bool(np, "ti,timer-dsp")) 212 return false; 213 214 if (of_property_read_bool(np, "ti,timer-pwm")) 215 return false; 216 217 return true; 218 } 219 220 /* 221 * Finds the first available usable always-on timer, and assigns it to either 222 * clockevent or clocksource depending if the counter_32k is available on the 223 * SoC or not. 224 * 225 * Some omap3 boards with unreliable oscillator must not use the counter_32k 226 * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable 227 * oscillator should really set counter_32k as disabled, and delete dmtimer1 228 * ti,always-on property, but let's not count on it. For these quirky cases, 229 * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz 230 * clock as the clocksource, and any available dmtimer as clockevent. 231 * 232 * For am437x, we are using am335x style dmtimer clocksource. It is unclear 233 * if this quirk handling is really needed, but let's change it separately 234 * based on testing as it might cause side effects. 235 */ 236 static void __init dmtimer_systimer_assign_alwon(void) 237 { 238 struct device_node *np; 239 u32 pa = 0; 240 bool quirk_unreliable_oscillator = false; 241 242 /* Quirk unreliable 32 KiHz oscillator with incomplete dts */ 243 if (of_machine_is_compatible("ti,omap3-beagle") || 244 of_machine_is_compatible("timll,omap3-devkit8000")) { 245 quirk_unreliable_oscillator = true; 246 counter_32k = -ENODEV; 247 } 248 249 /* Quirk am437x using am335x style dmtimer clocksource */ 250 if (of_machine_is_compatible("ti,am43")) 251 counter_32k = -ENODEV; 252 253 for_each_matching_node(np, dmtimer_match_table) { 254 if (!dmtimer_is_preferred(np)) 255 continue; 256 257 if (of_property_read_bool(np, "ti,timer-alwon")) { 258 const __be32 *addr; 259 260 addr = of_get_address(np, 0, NULL, NULL); 261 pa = of_translate_address(np, addr); 262 if (pa) { 263 /* Quirky omap3 boards must use dmtimer12 */ 264 if (quirk_unreliable_oscillator && 265 pa == 0x48318000) 266 continue; 267 268 of_node_put(np); 269 break; 270 } 271 } 272 } 273 274 /* Usually no need for dmtimer clocksource if we have counter32 */ 275 if (counter_32k >= 0) { 276 clockevent = pa; 277 clocksource = 0; 278 } else { 279 clocksource = pa; 280 clockevent = DMTIMER_INST_DONT_CARE; 281 } 282 } 283 284 /* Finds the first usable dmtimer, used for the don't care case */ 285 static u32 __init dmtimer_systimer_find_first_available(void) 286 { 287 struct device_node *np; 288 const __be32 *addr; 289 u32 pa = 0; 290 291 for_each_matching_node(np, dmtimer_match_table) { 292 if (!dmtimer_is_preferred(np)) 293 continue; 294 295 addr = of_get_address(np, 0, NULL, NULL); 296 pa = of_translate_address(np, addr); 297 if (pa) { 298 if (pa == clocksource || pa == clockevent) { 299 pa = 0; 300 continue; 301 } 302 303 of_node_put(np); 304 break; 305 } 306 } 307 308 return pa; 309 } 310 311 /* Selects the best clocksource and clockevent to use */ 312 static void __init dmtimer_systimer_select_best(void) 313 { 314 dmtimer_systimer_check_counter32k(); 315 dmtimer_systimer_assign_alwon(); 316 317 if (clockevent == DMTIMER_INST_DONT_CARE) 318 clockevent = dmtimer_systimer_find_first_available(); 319 320 pr_debug("%s: counter_32k: %i clocksource: %08x clockevent: %08x\n", 321 __func__, counter_32k, clocksource, clockevent); 322 } 323 324 /* Interface clocks are only available on some SoCs variants */ 325 static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t, 326 struct device_node *np, 327 const char *name, 328 unsigned long *rate) 329 { 330 struct clk *clock; 331 unsigned long r; 332 bool is_ick = false; 333 int error; 334 335 is_ick = !strncmp(name, "ick", 3); 336 337 clock = of_clk_get_by_name(np, name); 338 if ((PTR_ERR(clock) == -EINVAL) && is_ick) 339 return 0; 340 else if (IS_ERR(clock)) 341 return PTR_ERR(clock); 342 343 error = clk_prepare_enable(clock); 344 if (error) 345 return error; 346 347 r = clk_get_rate(clock); 348 if (!r) 349 return -ENODEV; 350 351 if (is_ick) 352 t->ick = clock; 353 else 354 t->fck = clock; 355 356 *rate = r; 357 358 return 0; 359 } 360 361 static int __init dmtimer_systimer_setup(struct device_node *np, 362 struct dmtimer_systimer *t) 363 { 364 unsigned long rate; 365 u8 regbase; 366 int error; 367 368 if (!of_device_is_compatible(np->parent, "ti,sysc")) 369 return -EINVAL; 370 371 t->base = of_iomap(np, 0); 372 if (!t->base) 373 return -ENXIO; 374 375 /* 376 * Enable optional assigned-clock-parents configured at the timer 377 * node level. For regular device drivers, this is done automatically 378 * by bus related code such as platform_drv_probe(). 379 */ 380 error = of_clk_set_defaults(np, false); 381 if (error < 0) 382 pr_err("%s: clock source init failed: %i\n", __func__, error); 383 384 /* For ti-sysc, we have timer clocks at the parent module level */ 385 error = dmtimer_systimer_init_clock(t, np->parent, "fck", &rate); 386 if (error) 387 goto err_unmap; 388 389 t->rate = rate; 390 391 error = dmtimer_systimer_init_clock(t, np->parent, "ick", &rate); 392 if (error) 393 goto err_unmap; 394 395 if (dmtimer_systimer_revision1(t)) { 396 t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET; 397 t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; 398 t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET; 399 regbase = 0; 400 } else { 401 t->irq_stat = OMAP_TIMER_V2_IRQSTATUS; 402 t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET; 403 regbase = OMAP_TIMER_V2_FUNC_OFFSET; 404 t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET; 405 } 406 407 t->sysc = OMAP_TIMER_OCP_CFG_OFFSET; 408 t->load = regbase + _OMAP_TIMER_LOAD_OFFSET; 409 t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET; 410 t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET; 411 t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET; 412 t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET; 413 414 dmtimer_systimer_reset(t); 415 dmtimer_systimer_enable(t); 416 pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base), 417 readl_relaxed(t->base + t->sysc)); 418 419 return 0; 420 421 err_unmap: 422 iounmap(t->base); 423 424 return error; 425 } 426 427 /* Clockevent */ 428 static struct dmtimer_clockevent * 429 to_dmtimer_clockevent(struct clock_event_device *clockevent) 430 { 431 return container_of(clockevent, struct dmtimer_clockevent, dev); 432 } 433 434 static irqreturn_t dmtimer_clockevent_interrupt(int irq, void *data) 435 { 436 struct dmtimer_clockevent *clkevt = data; 437 struct dmtimer_systimer *t = &clkevt->t; 438 439 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat); 440 clkevt->dev.event_handler(&clkevt->dev); 441 442 return IRQ_HANDLED; 443 } 444 445 static int dmtimer_set_next_event(unsigned long cycles, 446 struct clock_event_device *evt) 447 { 448 struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); 449 struct dmtimer_systimer *t = &clkevt->t; 450 void __iomem *pend = t->base + t->pend; 451 452 writel_relaxed(0xffffffff - cycles, t->base + t->counter); 453 while (readl_relaxed(pend) & WP_TCRR) 454 cpu_relax(); 455 456 writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); 457 while (readl_relaxed(pend) & WP_TCLR) 458 cpu_relax(); 459 460 return 0; 461 } 462 463 static int dmtimer_clockevent_shutdown(struct clock_event_device *evt) 464 { 465 struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); 466 struct dmtimer_systimer *t = &clkevt->t; 467 void __iomem *ctrl = t->base + t->ctrl; 468 u32 l; 469 470 l = readl_relaxed(ctrl); 471 if (l & OMAP_TIMER_CTRL_ST) { 472 l &= ~BIT(0); 473 writel_relaxed(l, ctrl); 474 /* Flush posted write */ 475 l = readl_relaxed(ctrl); 476 /* Wait for functional clock period x 3.5 */ 477 udelay(3500000 / t->rate + 1); 478 } 479 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat); 480 481 return 0; 482 } 483 484 static int dmtimer_set_periodic(struct clock_event_device *evt) 485 { 486 struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); 487 struct dmtimer_systimer *t = &clkevt->t; 488 void __iomem *pend = t->base + t->pend; 489 490 dmtimer_clockevent_shutdown(evt); 491 492 /* Looks like we need to first set the load value separately */ 493 writel_relaxed(clkevt->period, t->base + t->load); 494 while (readl_relaxed(pend) & WP_TLDR) 495 cpu_relax(); 496 497 writel_relaxed(clkevt->period, t->base + t->counter); 498 while (readl_relaxed(pend) & WP_TCRR) 499 cpu_relax(); 500 501 writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 502 t->base + t->ctrl); 503 while (readl_relaxed(pend) & WP_TCLR) 504 cpu_relax(); 505 506 return 0; 507 } 508 509 static void omap_clockevent_idle(struct clock_event_device *evt) 510 { 511 struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); 512 struct dmtimer_systimer *t = &clkevt->t; 513 514 dmtimer_systimer_disable(t); 515 clk_disable(t->fck); 516 } 517 518 static void omap_clockevent_unidle(struct clock_event_device *evt) 519 { 520 struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt); 521 struct dmtimer_systimer *t = &clkevt->t; 522 int error; 523 524 error = clk_enable(t->fck); 525 if (error) 526 pr_err("could not enable timer fck on resume: %i\n", error); 527 528 dmtimer_systimer_enable(t); 529 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); 530 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup); 531 } 532 533 static int __init dmtimer_clockevent_init(struct device_node *np) 534 { 535 struct dmtimer_clockevent *clkevt; 536 struct clock_event_device *dev; 537 struct dmtimer_systimer *t; 538 int error; 539 540 clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL); 541 if (!clkevt) 542 return -ENOMEM; 543 544 t = &clkevt->t; 545 dev = &clkevt->dev; 546 547 /* 548 * We mostly use cpuidle_coupled with ARM local timers for runtime, 549 * so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here. 550 */ 551 dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 552 dev->rating = 300; 553 dev->set_next_event = dmtimer_set_next_event; 554 dev->set_state_shutdown = dmtimer_clockevent_shutdown; 555 dev->set_state_periodic = dmtimer_set_periodic; 556 dev->set_state_oneshot = dmtimer_clockevent_shutdown; 557 dev->tick_resume = dmtimer_clockevent_shutdown; 558 dev->cpumask = cpu_possible_mask; 559 560 dev->irq = irq_of_parse_and_map(np, 0); 561 if (!dev->irq) { 562 error = -ENXIO; 563 goto err_out_free; 564 } 565 566 error = dmtimer_systimer_setup(np, &clkevt->t); 567 if (error) 568 goto err_out_free; 569 570 clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ); 571 572 /* 573 * For clock-event timers we never read the timer counter and 574 * so we are not impacted by errata i103 and i767. Therefore, 575 * we can safely ignore this errata for clock-event timers. 576 */ 577 writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl); 578 579 error = request_irq(dev->irq, dmtimer_clockevent_interrupt, 580 IRQF_TIMER, "clockevent", clkevt); 581 if (error) 582 goto err_out_unmap; 583 584 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); 585 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup); 586 587 pr_info("TI gptimer clockevent: %s%lu Hz at %pOF\n", 588 of_find_property(np, "ti,timer-alwon", NULL) ? 589 "always-on " : "", t->rate, np->parent); 590 591 clockevents_config_and_register(dev, t->rate, 592 3, /* Timer internal resynch latency */ 593 0xffffffff); 594 595 if (of_machine_is_compatible("ti,am33xx") || 596 of_machine_is_compatible("ti,am43")) { 597 dev->suspend = omap_clockevent_idle; 598 dev->resume = omap_clockevent_unidle; 599 } 600 601 return 0; 602 603 err_out_unmap: 604 iounmap(t->base); 605 606 err_out_free: 607 kfree(clkevt); 608 609 return error; 610 } 611 612 /* Clocksource */ 613 static struct dmtimer_clocksource * 614 to_dmtimer_clocksource(struct clocksource *cs) 615 { 616 return container_of(cs, struct dmtimer_clocksource, dev); 617 } 618 619 static u64 dmtimer_clocksource_read_cycles(struct clocksource *cs) 620 { 621 struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); 622 struct dmtimer_systimer *t = &clksrc->t; 623 624 return (u64)readl_relaxed(t->base + t->counter); 625 } 626 627 static void __iomem *dmtimer_sched_clock_counter; 628 629 static u64 notrace dmtimer_read_sched_clock(void) 630 { 631 return readl_relaxed(dmtimer_sched_clock_counter); 632 } 633 634 static void dmtimer_clocksource_suspend(struct clocksource *cs) 635 { 636 struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); 637 struct dmtimer_systimer *t = &clksrc->t; 638 639 clksrc->loadval = readl_relaxed(t->base + t->counter); 640 dmtimer_systimer_disable(t); 641 clk_disable(t->fck); 642 } 643 644 static void dmtimer_clocksource_resume(struct clocksource *cs) 645 { 646 struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); 647 struct dmtimer_systimer *t = &clksrc->t; 648 int error; 649 650 error = clk_enable(t->fck); 651 if (error) 652 pr_err("could not enable timer fck on resume: %i\n", error); 653 654 dmtimer_systimer_enable(t); 655 writel_relaxed(clksrc->loadval, t->base + t->counter); 656 writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 657 t->base + t->ctrl); 658 } 659 660 static int __init dmtimer_clocksource_init(struct device_node *np) 661 { 662 struct dmtimer_clocksource *clksrc; 663 struct dmtimer_systimer *t; 664 struct clocksource *dev; 665 int error; 666 667 clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL); 668 if (!clksrc) 669 return -ENOMEM; 670 671 dev = &clksrc->dev; 672 t = &clksrc->t; 673 674 error = dmtimer_systimer_setup(np, t); 675 if (error) 676 goto err_out_free; 677 678 dev->name = "dmtimer"; 679 dev->rating = 300; 680 dev->read = dmtimer_clocksource_read_cycles; 681 dev->mask = CLOCKSOURCE_MASK(32); 682 dev->flags = CLOCK_SOURCE_IS_CONTINUOUS; 683 684 /* Unlike for clockevent, legacy code sets suspend only for am4 */ 685 if (of_machine_is_compatible("ti,am43")) { 686 dev->suspend = dmtimer_clocksource_suspend; 687 dev->resume = dmtimer_clocksource_resume; 688 } 689 690 writel_relaxed(0, t->base + t->counter); 691 writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 692 t->base + t->ctrl); 693 694 pr_info("TI gptimer clocksource: %s%pOF\n", 695 of_find_property(np, "ti,timer-alwon", NULL) ? 696 "always-on " : "", np->parent); 697 698 if (!dmtimer_sched_clock_counter) { 699 dmtimer_sched_clock_counter = t->base + t->counter; 700 sched_clock_register(dmtimer_read_sched_clock, 32, t->rate); 701 } 702 703 if (clocksource_register_hz(dev, t->rate)) 704 pr_err("Could not register clocksource %pOF\n", np); 705 706 return 0; 707 708 err_out_free: 709 kfree(clksrc); 710 711 return -ENODEV; 712 } 713 714 /* 715 * To detect between a clocksource and clockevent, we assume the device tree 716 * has no interrupts configured for a clocksource timer. 717 */ 718 static int __init dmtimer_systimer_init(struct device_node *np) 719 { 720 const __be32 *addr; 721 u32 pa; 722 723 /* One time init for the preferred timer configuration */ 724 if (!clocksource && !clockevent) 725 dmtimer_systimer_select_best(); 726 727 if (!clocksource && !clockevent) { 728 pr_err("%s: unable to detect system timers, update dtb?\n", 729 __func__); 730 731 return -EINVAL; 732 } 733 734 addr = of_get_address(np, 0, NULL, NULL); 735 pa = of_translate_address(np, addr); 736 if (!pa) 737 return -EINVAL; 738 739 if (counter_32k <= 0 && clocksource == pa) 740 return dmtimer_clocksource_init(np); 741 742 if (clockevent == pa) 743 return dmtimer_clockevent_init(np); 744 745 return 0; 746 } 747 748 TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init); 749 TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init); 750 TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init); 751 TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init); 752 TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init); 753 TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init); 754 TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init); 755 TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init); 756