1fe851f56SFelipe Balbi /** 2fe851f56SFelipe Balbi * timer-ti-32k.c - OMAP2 32k Timer Support 3fe851f56SFelipe Balbi * 4fe851f56SFelipe Balbi * Copyright (C) 2009 Nokia Corporation 5fe851f56SFelipe Balbi * 6fe851f56SFelipe Balbi * Update to use new clocksource/clockevent layers 7fe851f56SFelipe Balbi * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 8fe851f56SFelipe Balbi * Copyright (C) 2007 MontaVista Software, Inc. 9fe851f56SFelipe Balbi * 10fe851f56SFelipe Balbi * Original driver: 11fe851f56SFelipe Balbi * Copyright (C) 2005 Nokia Corporation 12fe851f56SFelipe Balbi * Author: Paul Mundt <paul.mundt@nokia.com> 13fe851f56SFelipe Balbi * Juha Yrjölä <juha.yrjola@nokia.com> 14fe851f56SFelipe Balbi * OMAP Dual-mode timer framework support by Timo Teras 15fe851f56SFelipe Balbi * 16fe851f56SFelipe Balbi * Some parts based off of TI's 24xx code: 17fe851f56SFelipe Balbi * 18fe851f56SFelipe Balbi * Copyright (C) 2004-2009 Texas Instruments, Inc. 19fe851f56SFelipe Balbi * 20fe851f56SFelipe Balbi * Roughly modelled after the OMAP1 MPU timer code. 21fe851f56SFelipe Balbi * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 22fe851f56SFelipe Balbi * 23fe851f56SFelipe Balbi * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 24fe851f56SFelipe Balbi * 25fe851f56SFelipe Balbi * This program is free software: you can redistribute it and/or modify 26fe851f56SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 27fe851f56SFelipe Balbi * the License as published by the Free Software Foundation. 28fe851f56SFelipe Balbi * 29fe851f56SFelipe Balbi * This program is distributed in the hope that it will be useful, 30fe851f56SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 31fe851f56SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32fe851f56SFelipe Balbi * GNU General Public License for more details. 33fe851f56SFelipe Balbi * 34fe851f56SFelipe Balbi * You should have received a copy of the GNU General Public License 35fe851f56SFelipe Balbi * along with this program. If not, see <http://www.gnu.org/licenses/>. 36fe851f56SFelipe Balbi */ 37fe851f56SFelipe Balbi 38fe851f56SFelipe Balbi #include <linux/init.h> 39fe851f56SFelipe Balbi #include <linux/time.h> 40fe851f56SFelipe Balbi #include <linux/sched_clock.h> 41fe851f56SFelipe Balbi #include <linux/clocksource.h> 42fe851f56SFelipe Balbi #include <linux/of.h> 43fe851f56SFelipe Balbi #include <linux/of_address.h> 44fe851f56SFelipe Balbi 45fe851f56SFelipe Balbi /* 46fe851f56SFelipe Balbi * 32KHz clocksource ... always available, on pretty most chips except 47fe851f56SFelipe Balbi * OMAP 730 and 1510. Other timers could be used as clocksources, with 48fe851f56SFelipe Balbi * higher resolution in free-running counter modes (e.g. 12 MHz xtal), 49fe851f56SFelipe Balbi * but systems won't necessarily want to spend resources that way. 50fe851f56SFelipe Balbi */ 51fe851f56SFelipe Balbi 52fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_REV_OFF 0x0 53fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) 54fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 55fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 56fe851f56SFelipe Balbi 57fe851f56SFelipe Balbi struct ti_32k { 58fe851f56SFelipe Balbi void __iomem *base; 59fe851f56SFelipe Balbi void __iomem *counter; 60fe851f56SFelipe Balbi struct clocksource cs; 61fe851f56SFelipe Balbi }; 62fe851f56SFelipe Balbi 63fe851f56SFelipe Balbi static inline struct ti_32k *to_ti_32k(struct clocksource *cs) 64fe851f56SFelipe Balbi { 65fe851f56SFelipe Balbi return container_of(cs, struct ti_32k, cs); 66fe851f56SFelipe Balbi } 67fe851f56SFelipe Balbi 68a5a1d1c2SThomas Gleixner static u64 notrace ti_32k_read_cycles(struct clocksource *cs) 69fe851f56SFelipe Balbi { 70fe851f56SFelipe Balbi struct ti_32k *ti = to_ti_32k(cs); 71fe851f56SFelipe Balbi 72a5a1d1c2SThomas Gleixner return (u64)readl_relaxed(ti->counter); 73fe851f56SFelipe Balbi } 74fe851f56SFelipe Balbi 75fe851f56SFelipe Balbi static struct ti_32k ti_32k_timer = { 76fe851f56SFelipe Balbi .cs = { 77fe851f56SFelipe Balbi .name = "32k_counter", 78fe851f56SFelipe Balbi .rating = 250, 79fe851f56SFelipe Balbi .read = ti_32k_read_cycles, 80fe851f56SFelipe Balbi .mask = CLOCKSOURCE_MASK(32), 81fe851f56SFelipe Balbi .flags = CLOCK_SOURCE_IS_CONTINUOUS | 82fe851f56SFelipe Balbi CLOCK_SOURCE_SUSPEND_NONSTOP, 83fe851f56SFelipe Balbi }, 84fe851f56SFelipe Balbi }; 85fe851f56SFelipe Balbi 86fe851f56SFelipe Balbi static u64 notrace omap_32k_read_sched_clock(void) 87fe851f56SFelipe Balbi { 88fe851f56SFelipe Balbi return ti_32k_read_cycles(&ti_32k_timer.cs); 89fe851f56SFelipe Balbi } 90fe851f56SFelipe Balbi 910a8e7d49SDaniel Lezcano static int __init ti_32k_timer_init(struct device_node *np) 92fe851f56SFelipe Balbi { 93fe851f56SFelipe Balbi int ret; 94fe851f56SFelipe Balbi 95fe851f56SFelipe Balbi ti_32k_timer.base = of_iomap(np, 0); 96fe851f56SFelipe Balbi if (!ti_32k_timer.base) { 97fe851f56SFelipe Balbi pr_err("Can't ioremap 32k timer base\n"); 980a8e7d49SDaniel Lezcano return -ENXIO; 99fe851f56SFelipe Balbi } 100fe851f56SFelipe Balbi 101fe851f56SFelipe Balbi ti_32k_timer.counter = ti_32k_timer.base; 102fe851f56SFelipe Balbi 103fe851f56SFelipe Balbi /* 104fe851f56SFelipe Balbi * 32k sync Counter IP register offsets vary between the highlander 105fe851f56SFelipe Balbi * version and the legacy ones. 106fe851f56SFelipe Balbi * 107fe851f56SFelipe Balbi * The 'SCHEME' bits(30-31) of the revision register is used to identify 108fe851f56SFelipe Balbi * the version. 109fe851f56SFelipe Balbi */ 110fe851f56SFelipe Balbi if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) & 111fe851f56SFelipe Balbi OMAP2_32KSYNCNT_REV_SCHEME) 112fe851f56SFelipe Balbi ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH; 113fe851f56SFelipe Balbi else 114fe851f56SFelipe Balbi ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW; 115fe851f56SFelipe Balbi 116fe851f56SFelipe Balbi ret = clocksource_register_hz(&ti_32k_timer.cs, 32768); 117fe851f56SFelipe Balbi if (ret) { 118fe851f56SFelipe Balbi pr_err("32k_counter: can't register clocksource\n"); 1190a8e7d49SDaniel Lezcano return ret; 120fe851f56SFelipe Balbi } 121fe851f56SFelipe Balbi 122fe851f56SFelipe Balbi sched_clock_register(omap_32k_read_sched_clock, 32, 32768); 123fe851f56SFelipe Balbi pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); 1240a8e7d49SDaniel Lezcano 1250a8e7d49SDaniel Lezcano return 0; 126fe851f56SFelipe Balbi } 127177cf6e5SDaniel Lezcano CLOCKSOURCE_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k", 128fe851f56SFelipe Balbi ti_32k_timer_init); 129