16b1baefeSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2fe851f56SFelipe Balbi /** 3fe851f56SFelipe Balbi * timer-ti-32k.c - OMAP2 32k Timer Support 4fe851f56SFelipe Balbi * 5fe851f56SFelipe Balbi * Copyright (C) 2009 Nokia Corporation 6fe851f56SFelipe Balbi * 7fe851f56SFelipe Balbi * Update to use new clocksource/clockevent layers 8fe851f56SFelipe Balbi * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 9fe851f56SFelipe Balbi * Copyright (C) 2007 MontaVista Software, Inc. 10fe851f56SFelipe Balbi * 11fe851f56SFelipe Balbi * Original driver: 12fe851f56SFelipe Balbi * Copyright (C) 2005 Nokia Corporation 13fe851f56SFelipe Balbi * Author: Paul Mundt <paul.mundt@nokia.com> 14fe851f56SFelipe Balbi * Juha Yrjölä <juha.yrjola@nokia.com> 15fe851f56SFelipe Balbi * OMAP Dual-mode timer framework support by Timo Teras 16fe851f56SFelipe Balbi * 17fe851f56SFelipe Balbi * Some parts based off of TI's 24xx code: 18fe851f56SFelipe Balbi * 19fe851f56SFelipe Balbi * Copyright (C) 2004-2009 Texas Instruments, Inc. 20fe851f56SFelipe Balbi * 21fe851f56SFelipe Balbi * Roughly modelled after the OMAP1 MPU timer code. 22fe851f56SFelipe Balbi * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 23fe851f56SFelipe Balbi * 24fe851f56SFelipe Balbi * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 25fe851f56SFelipe Balbi */ 26fe851f56SFelipe Balbi 2746b30515STony Lindgren #include <linux/clk.h> 28fe851f56SFelipe Balbi #include <linux/init.h> 29fe851f56SFelipe Balbi #include <linux/time.h> 30fe851f56SFelipe Balbi #include <linux/sched_clock.h> 31fe851f56SFelipe Balbi #include <linux/clocksource.h> 32fe851f56SFelipe Balbi #include <linux/of.h> 33fe851f56SFelipe Balbi #include <linux/of_address.h> 34fe851f56SFelipe Balbi 35fe851f56SFelipe Balbi /* 36fe851f56SFelipe Balbi * 32KHz clocksource ... always available, on pretty most chips except 37fe851f56SFelipe Balbi * OMAP 730 and 1510. Other timers could be used as clocksources, with 38fe851f56SFelipe Balbi * higher resolution in free-running counter modes (e.g. 12 MHz xtal), 39fe851f56SFelipe Balbi * but systems won't necessarily want to spend resources that way. 40fe851f56SFelipe Balbi */ 41fe851f56SFelipe Balbi 42fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_REV_OFF 0x0 43fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) 44fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 45fe851f56SFelipe Balbi #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 46fe851f56SFelipe Balbi 47fe851f56SFelipe Balbi struct ti_32k { 48fe851f56SFelipe Balbi void __iomem *base; 49fe851f56SFelipe Balbi void __iomem *counter; 50fe851f56SFelipe Balbi struct clocksource cs; 51fe851f56SFelipe Balbi }; 52fe851f56SFelipe Balbi 53fe851f56SFelipe Balbi static inline struct ti_32k *to_ti_32k(struct clocksource *cs) 54fe851f56SFelipe Balbi { 55fe851f56SFelipe Balbi return container_of(cs, struct ti_32k, cs); 56fe851f56SFelipe Balbi } 57fe851f56SFelipe Balbi 58a5a1d1c2SThomas Gleixner static u64 notrace ti_32k_read_cycles(struct clocksource *cs) 59fe851f56SFelipe Balbi { 60fe851f56SFelipe Balbi struct ti_32k *ti = to_ti_32k(cs); 61fe851f56SFelipe Balbi 62a5a1d1c2SThomas Gleixner return (u64)readl_relaxed(ti->counter); 63fe851f56SFelipe Balbi } 64fe851f56SFelipe Balbi 65fe851f56SFelipe Balbi static struct ti_32k ti_32k_timer = { 66fe851f56SFelipe Balbi .cs = { 67fe851f56SFelipe Balbi .name = "32k_counter", 68fe851f56SFelipe Balbi .rating = 250, 69fe851f56SFelipe Balbi .read = ti_32k_read_cycles, 70fe851f56SFelipe Balbi .mask = CLOCKSOURCE_MASK(32), 71c77aee71SKeerthy .flags = CLOCK_SOURCE_IS_CONTINUOUS, 72fe851f56SFelipe Balbi }, 73fe851f56SFelipe Balbi }; 74fe851f56SFelipe Balbi 75fe851f56SFelipe Balbi static u64 notrace omap_32k_read_sched_clock(void) 76fe851f56SFelipe Balbi { 77fe851f56SFelipe Balbi return ti_32k_read_cycles(&ti_32k_timer.cs); 78fe851f56SFelipe Balbi } 79fe851f56SFelipe Balbi 8046b30515STony Lindgren static void __init ti_32k_timer_enable_clock(struct device_node *np, 8146b30515STony Lindgren const char *name) 8246b30515STony Lindgren { 8346b30515STony Lindgren struct clk *clock; 8446b30515STony Lindgren int error; 8546b30515STony Lindgren 8646b30515STony Lindgren clock = of_clk_get_by_name(np->parent, name); 8746b30515STony Lindgren if (IS_ERR(clock)) { 8846b30515STony Lindgren /* Only some SoCs have a separate interface clock */ 8946b30515STony Lindgren if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3)) 9046b30515STony Lindgren return; 9146b30515STony Lindgren 9246b30515STony Lindgren pr_warn("%s: could not get clock %s %li\n", 9346b30515STony Lindgren __func__, name, PTR_ERR(clock)); 9446b30515STony Lindgren return; 9546b30515STony Lindgren } 9646b30515STony Lindgren 9746b30515STony Lindgren error = clk_prepare_enable(clock); 9846b30515STony Lindgren if (error) { 9946b30515STony Lindgren pr_warn("%s: could not enable %s: %i\n", 10046b30515STony Lindgren __func__, name, error); 10146b30515STony Lindgren return; 10246b30515STony Lindgren } 10346b30515STony Lindgren } 10446b30515STony Lindgren 10546b30515STony Lindgren static void __init ti_32k_timer_module_init(struct device_node *np, 10646b30515STony Lindgren void __iomem *base) 10746b30515STony Lindgren { 10846b30515STony Lindgren void __iomem *sysc = base + 4; 10946b30515STony Lindgren 11046b30515STony Lindgren if (!of_device_is_compatible(np->parent, "ti,sysc")) 11146b30515STony Lindgren return; 11246b30515STony Lindgren 11346b30515STony Lindgren ti_32k_timer_enable_clock(np, "fck"); 11446b30515STony Lindgren ti_32k_timer_enable_clock(np, "ick"); 11546b30515STony Lindgren 11646b30515STony Lindgren /* 11746b30515STony Lindgren * Force idle module as wkup domain is active with MPU. 11846b30515STony Lindgren * No need to tag the module disabled for ti-sysc probe. 11946b30515STony Lindgren */ 12046b30515STony Lindgren writel_relaxed(0, sysc); 12146b30515STony Lindgren } 12246b30515STony Lindgren 1230a8e7d49SDaniel Lezcano static int __init ti_32k_timer_init(struct device_node *np) 124fe851f56SFelipe Balbi { 125fe851f56SFelipe Balbi int ret; 126fe851f56SFelipe Balbi 127fe851f56SFelipe Balbi ti_32k_timer.base = of_iomap(np, 0); 128fe851f56SFelipe Balbi if (!ti_32k_timer.base) { 129fe851f56SFelipe Balbi pr_err("Can't ioremap 32k timer base\n"); 1300a8e7d49SDaniel Lezcano return -ENXIO; 131fe851f56SFelipe Balbi } 132fe851f56SFelipe Balbi 1333b7d96a0SKeerthy if (!of_machine_is_compatible("ti,am43")) 1343b7d96a0SKeerthy ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; 1353b7d96a0SKeerthy 136fe851f56SFelipe Balbi ti_32k_timer.counter = ti_32k_timer.base; 13746b30515STony Lindgren ti_32k_timer_module_init(np, ti_32k_timer.base); 138fe851f56SFelipe Balbi 139fe851f56SFelipe Balbi /* 140fe851f56SFelipe Balbi * 32k sync Counter IP register offsets vary between the highlander 141fe851f56SFelipe Balbi * version and the legacy ones. 142fe851f56SFelipe Balbi * 143fe851f56SFelipe Balbi * The 'SCHEME' bits(30-31) of the revision register is used to identify 144fe851f56SFelipe Balbi * the version. 145fe851f56SFelipe Balbi */ 146fe851f56SFelipe Balbi if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) & 147fe851f56SFelipe Balbi OMAP2_32KSYNCNT_REV_SCHEME) 148fe851f56SFelipe Balbi ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH; 149fe851f56SFelipe Balbi else 150fe851f56SFelipe Balbi ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW; 151fe851f56SFelipe Balbi 15246b30515STony Lindgren pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); 15346b30515STony Lindgren 154fe851f56SFelipe Balbi ret = clocksource_register_hz(&ti_32k_timer.cs, 32768); 155fe851f56SFelipe Balbi if (ret) { 156fe851f56SFelipe Balbi pr_err("32k_counter: can't register clocksource\n"); 1570a8e7d49SDaniel Lezcano return ret; 158fe851f56SFelipe Balbi } 159fe851f56SFelipe Balbi 160fe851f56SFelipe Balbi sched_clock_register(omap_32k_read_sched_clock, 32, 32768); 1610a8e7d49SDaniel Lezcano 1620a8e7d49SDaniel Lezcano return 0; 163fe851f56SFelipe Balbi } 16417273395SDaniel Lezcano TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k", 165fe851f56SFelipe Balbi ti_32k_timer_init); 166