1 /* 2 * linux/drivers/clocksource/timer-sp.c 3 * 4 * Copyright (C) 1999 - 2003 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #include <linux/clk.h> 22 #include <linux/clocksource.h> 23 #include <linux/clockchips.h> 24 #include <linux/err.h> 25 #include <linux/interrupt.h> 26 #include <linux/irq.h> 27 #include <linux/io.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/sched_clock.h> 32 33 #include <clocksource/timer-sp804.h> 34 35 #include "timer-sp.h" 36 37 static long __init sp804_get_clock_rate(struct clk *clk) 38 { 39 long rate; 40 int err; 41 42 err = clk_prepare(clk); 43 if (err) { 44 pr_err("sp804: clock failed to prepare: %d\n", err); 45 clk_put(clk); 46 return err; 47 } 48 49 err = clk_enable(clk); 50 if (err) { 51 pr_err("sp804: clock failed to enable: %d\n", err); 52 clk_unprepare(clk); 53 clk_put(clk); 54 return err; 55 } 56 57 rate = clk_get_rate(clk); 58 if (rate < 0) { 59 pr_err("sp804: clock failed to get rate: %ld\n", rate); 60 clk_disable(clk); 61 clk_unprepare(clk); 62 clk_put(clk); 63 } 64 65 return rate; 66 } 67 68 static void __iomem *sched_clock_base; 69 70 static u64 notrace sp804_read(void) 71 { 72 return ~readl_relaxed(sched_clock_base + TIMER_VALUE); 73 } 74 75 void __init sp804_timer_disable(void __iomem *base) 76 { 77 writel(0, base + TIMER_CTRL); 78 } 79 80 void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, 81 const char *name, 82 struct clk *clk, 83 int use_sched_clock) 84 { 85 long rate; 86 87 if (!clk) { 88 clk = clk_get_sys("sp804", name); 89 if (IS_ERR(clk)) { 90 pr_err("sp804: clock not found: %d\n", 91 (int)PTR_ERR(clk)); 92 return; 93 } 94 } 95 96 rate = sp804_get_clock_rate(clk); 97 98 if (rate < 0) 99 return; 100 101 /* setup timer 0 as free-running clocksource */ 102 writel(0, base + TIMER_CTRL); 103 writel(0xffffffff, base + TIMER_LOAD); 104 writel(0xffffffff, base + TIMER_VALUE); 105 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, 106 base + TIMER_CTRL); 107 108 clocksource_mmio_init(base + TIMER_VALUE, name, 109 rate, 200, 32, clocksource_mmio_readl_down); 110 111 if (use_sched_clock) { 112 sched_clock_base = base; 113 sched_clock_register(sp804_read, 32, rate); 114 } 115 } 116 117 118 static void __iomem *clkevt_base; 119 static unsigned long clkevt_reload; 120 121 /* 122 * IRQ handler for the timer 123 */ 124 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) 125 { 126 struct clock_event_device *evt = dev_id; 127 128 /* clear the interrupt */ 129 writel(1, clkevt_base + TIMER_INTCLR); 130 131 evt->event_handler(evt); 132 133 return IRQ_HANDLED; 134 } 135 136 static inline void timer_shutdown(struct clock_event_device *evt) 137 { 138 writel(0, clkevt_base + TIMER_CTRL); 139 } 140 141 static int sp804_shutdown(struct clock_event_device *evt) 142 { 143 timer_shutdown(evt); 144 return 0; 145 } 146 147 static int sp804_set_periodic(struct clock_event_device *evt) 148 { 149 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | 150 TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; 151 152 timer_shutdown(evt); 153 writel(clkevt_reload, clkevt_base + TIMER_LOAD); 154 writel(ctrl, clkevt_base + TIMER_CTRL); 155 return 0; 156 } 157 158 static int sp804_set_next_event(unsigned long next, 159 struct clock_event_device *evt) 160 { 161 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | 162 TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE; 163 164 writel(next, clkevt_base + TIMER_LOAD); 165 writel(ctrl, clkevt_base + TIMER_CTRL); 166 167 return 0; 168 } 169 170 static struct clock_event_device sp804_clockevent = { 171 .features = CLOCK_EVT_FEAT_PERIODIC | 172 CLOCK_EVT_FEAT_ONESHOT | 173 CLOCK_EVT_FEAT_DYNIRQ, 174 .set_state_shutdown = sp804_shutdown, 175 .set_state_periodic = sp804_set_periodic, 176 .set_state_oneshot = sp804_shutdown, 177 .tick_resume = sp804_shutdown, 178 .set_next_event = sp804_set_next_event, 179 .rating = 300, 180 }; 181 182 static struct irqaction sp804_timer_irq = { 183 .name = "timer", 184 .flags = IRQF_TIMER | IRQF_IRQPOLL, 185 .handler = sp804_timer_interrupt, 186 .dev_id = &sp804_clockevent, 187 }; 188 189 void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) 190 { 191 struct clock_event_device *evt = &sp804_clockevent; 192 long rate; 193 194 if (!clk) 195 clk = clk_get_sys("sp804", name); 196 if (IS_ERR(clk)) { 197 pr_err("sp804: %s clock not found: %d\n", name, 198 (int)PTR_ERR(clk)); 199 return; 200 } 201 202 rate = sp804_get_clock_rate(clk); 203 if (rate < 0) 204 return; 205 206 clkevt_base = base; 207 clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); 208 evt->name = name; 209 evt->irq = irq; 210 evt->cpumask = cpu_possible_mask; 211 212 writel(0, base + TIMER_CTRL); 213 214 setup_irq(irq, &sp804_timer_irq); 215 clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); 216 } 217 218 static void __init sp804_of_init(struct device_node *np) 219 { 220 static bool initialized = false; 221 void __iomem *base; 222 int irq; 223 u32 irq_num = 0; 224 struct clk *clk1, *clk2; 225 const char *name = of_get_property(np, "compatible", NULL); 226 227 base = of_iomap(np, 0); 228 if (WARN_ON(!base)) 229 return; 230 231 /* Ensure timers are disabled */ 232 writel(0, base + TIMER_CTRL); 233 writel(0, base + TIMER_2_BASE + TIMER_CTRL); 234 235 if (initialized || !of_device_is_available(np)) 236 goto err; 237 238 clk1 = of_clk_get(np, 0); 239 if (IS_ERR(clk1)) 240 clk1 = NULL; 241 242 /* Get the 2nd clock if the timer has 3 timer clocks */ 243 if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) { 244 clk2 = of_clk_get(np, 1); 245 if (IS_ERR(clk2)) { 246 pr_err("sp804: %s clock not found: %d\n", np->name, 247 (int)PTR_ERR(clk2)); 248 clk2 = NULL; 249 } 250 } else 251 clk2 = clk1; 252 253 irq = irq_of_parse_and_map(np, 0); 254 if (irq <= 0) 255 goto err; 256 257 of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); 258 if (irq_num == 2) { 259 __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); 260 __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); 261 } else { 262 __sp804_clockevents_init(base, irq, clk1 , name); 263 __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, 264 name, clk2, 1); 265 } 266 initialized = true; 267 268 return; 269 err: 270 iounmap(base); 271 } 272 CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); 273 274 static void __init integrator_cp_of_init(struct device_node *np) 275 { 276 static int init_count = 0; 277 void __iomem *base; 278 int irq; 279 const char *name = of_get_property(np, "compatible", NULL); 280 struct clk *clk; 281 282 base = of_iomap(np, 0); 283 if (WARN_ON(!base)) 284 return; 285 clk = of_clk_get(np, 0); 286 if (WARN_ON(IS_ERR(clk))) 287 return; 288 289 /* Ensure timer is disabled */ 290 writel(0, base + TIMER_CTRL); 291 292 if (init_count == 2 || !of_device_is_available(np)) 293 goto err; 294 295 if (!init_count) 296 __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); 297 else { 298 irq = irq_of_parse_and_map(np, 0); 299 if (irq <= 0) 300 goto err; 301 302 __sp804_clockevents_init(base, irq, clk, name); 303 } 304 305 init_count++; 306 return; 307 err: 308 iounmap(base); 309 } 310 CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init); 311