1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012 Regents of the University of California
4  * Copyright (C) 2017 SiFive
5  *
6  * All RISC-V systems have a timer attached to every hart.  These timers can
7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
8  * setup events, or directly accessed using MMIO registers.
9  */
10 #include <linux/clocksource.h>
11 #include <linux/clockchips.h>
12 #include <linux/cpu.h>
13 #include <linux/delay.h>
14 #include <linux/irq.h>
15 #include <linux/sched_clock.h>
16 #include <linux/io-64-nonatomic-lo-hi.h>
17 #include <asm/smp.h>
18 #include <asm/sbi.h>
19 
20 u64 __iomem *riscv_time_cmp;
21 u64 __iomem *riscv_time_val;
22 
23 static inline void mmio_set_timer(u64 val)
24 {
25 	void __iomem *r;
26 
27 	r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
28 	writeq_relaxed(val, r);
29 }
30 
31 static int riscv_clock_next_event(unsigned long delta,
32 		struct clock_event_device *ce)
33 {
34 	csr_set(CSR_IE, IE_TIE);
35 	if (IS_ENABLED(CONFIG_RISCV_SBI))
36 		sbi_set_timer(get_cycles64() + delta);
37 	else
38 		mmio_set_timer(get_cycles64() + delta);
39 	return 0;
40 }
41 
42 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
43 	.name			= "riscv_timer_clockevent",
44 	.features		= CLOCK_EVT_FEAT_ONESHOT,
45 	.rating			= 100,
46 	.set_next_event		= riscv_clock_next_event,
47 };
48 
49 /*
50  * It is guaranteed that all the timers across all the harts are synchronized
51  * within one tick of each other, so while this could technically go
52  * backwards when hopping between CPUs, practically it won't happen.
53  */
54 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
55 {
56 	return get_cycles64();
57 }
58 
59 static u64 riscv_sched_clock(void)
60 {
61 	return get_cycles64();
62 }
63 
64 static struct clocksource riscv_clocksource = {
65 	.name		= "riscv_clocksource",
66 	.rating		= 300,
67 	.mask		= CLOCKSOURCE_MASK(64),
68 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
69 	.read		= riscv_clocksource_rdtime,
70 };
71 
72 static int riscv_timer_starting_cpu(unsigned int cpu)
73 {
74 	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
75 
76 	ce->cpumask = cpumask_of(cpu);
77 	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
78 
79 	csr_set(CSR_IE, IE_TIE);
80 	return 0;
81 }
82 
83 static int riscv_timer_dying_cpu(unsigned int cpu)
84 {
85 	csr_clear(CSR_IE, IE_TIE);
86 	return 0;
87 }
88 
89 /* called directly from the low-level interrupt handler */
90 void riscv_timer_interrupt(void)
91 {
92 	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
93 
94 	csr_clear(CSR_IE, IE_TIE);
95 	evdev->event_handler(evdev);
96 }
97 
98 static int __init riscv_timer_init_dt(struct device_node *n)
99 {
100 	int cpuid, hartid, error;
101 
102 	hartid = riscv_of_processor_hartid(n);
103 	if (hartid < 0) {
104 		pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
105 			n, hartid);
106 		return hartid;
107 	}
108 
109 	cpuid = riscv_hartid_to_cpuid(hartid);
110 	if (cpuid < 0) {
111 		pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
112 		return cpuid;
113 	}
114 
115 	if (cpuid != smp_processor_id())
116 		return 0;
117 
118 	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
119 	       __func__, cpuid, hartid);
120 	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
121 	if (error) {
122 		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
123 		       error, cpuid);
124 		return error;
125 	}
126 
127 	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
128 
129 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
130 			 "clockevents/riscv/timer:starting",
131 			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
132 	if (error)
133 		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
134 		       error);
135 	return error;
136 }
137 
138 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
139