1 /* 2 * Integrator/AP timer driver 3 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd 4 * Copyright (c) 2014, Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clocksource.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_address.h> 25 #include <linux/of_platform.h> 26 #include <linux/clockchips.h> 27 #include <linux/interrupt.h> 28 #include <linux/sched_clock.h> 29 30 #include "timer-sp.h" 31 32 static void __iomem * sched_clk_base; 33 34 static u64 notrace integrator_read_sched_clock(void) 35 { 36 return -readl(sched_clk_base + TIMER_VALUE); 37 } 38 39 static void integrator_clocksource_init(unsigned long inrate, 40 void __iomem *base) 41 { 42 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; 43 unsigned long rate = inrate; 44 45 if (rate >= 1500000) { 46 rate /= 16; 47 ctrl |= TIMER_CTRL_DIV16; 48 } 49 50 writel(0xffff, base + TIMER_LOAD); 51 writel(ctrl, base + TIMER_CTRL); 52 53 clocksource_mmio_init(base + TIMER_VALUE, "timer2", 54 rate, 200, 16, clocksource_mmio_readl_down); 55 56 sched_clk_base = base; 57 sched_clock_register(integrator_read_sched_clock, 16, rate); 58 } 59 60 static unsigned long timer_reload; 61 static void __iomem * clkevt_base; 62 63 /* 64 * IRQ handler for the timer 65 */ 66 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) 67 { 68 struct clock_event_device *evt = dev_id; 69 70 /* clear the interrupt */ 71 writel(1, clkevt_base + TIMER_INTCLR); 72 73 evt->event_handler(evt); 74 75 return IRQ_HANDLED; 76 } 77 78 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) 79 { 80 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; 81 82 /* Disable timer */ 83 writel(ctrl, clkevt_base + TIMER_CTRL); 84 85 switch (mode) { 86 case CLOCK_EVT_MODE_PERIODIC: 87 /* Enable the timer and start the periodic tick */ 88 writel(timer_reload, clkevt_base + TIMER_LOAD); 89 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; 90 writel(ctrl, clkevt_base + TIMER_CTRL); 91 break; 92 case CLOCK_EVT_MODE_ONESHOT: 93 /* Leave the timer disabled, .set_next_event will enable it */ 94 ctrl &= ~TIMER_CTRL_PERIODIC; 95 writel(ctrl, clkevt_base + TIMER_CTRL); 96 break; 97 case CLOCK_EVT_MODE_UNUSED: 98 case CLOCK_EVT_MODE_SHUTDOWN: 99 case CLOCK_EVT_MODE_RESUME: 100 default: 101 /* Just leave in disabled state */ 102 break; 103 } 104 105 } 106 107 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) 108 { 109 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); 110 111 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); 112 writel(next, clkevt_base + TIMER_LOAD); 113 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); 114 115 return 0; 116 } 117 118 static struct clock_event_device integrator_clockevent = { 119 .name = "timer1", 120 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 121 .set_mode = clkevt_set_mode, 122 .set_next_event = clkevt_set_next_event, 123 .rating = 300, 124 }; 125 126 static struct irqaction integrator_timer_irq = { 127 .name = "timer", 128 .flags = IRQF_TIMER | IRQF_IRQPOLL, 129 .handler = integrator_timer_interrupt, 130 .dev_id = &integrator_clockevent, 131 }; 132 133 static void integrator_clockevent_init(unsigned long inrate, 134 void __iomem *base, int irq) 135 { 136 unsigned long rate = inrate; 137 unsigned int ctrl = 0; 138 139 clkevt_base = base; 140 /* Calculate and program a divisor */ 141 if (rate > 0x100000 * HZ) { 142 rate /= 256; 143 ctrl |= TIMER_CTRL_DIV256; 144 } else if (rate > 0x10000 * HZ) { 145 rate /= 16; 146 ctrl |= TIMER_CTRL_DIV16; 147 } 148 timer_reload = rate / HZ; 149 writel(ctrl, clkevt_base + TIMER_CTRL); 150 151 setup_irq(irq, &integrator_timer_irq); 152 clockevents_config_and_register(&integrator_clockevent, 153 rate, 154 1, 155 0xffffU); 156 } 157 158 static void __init integrator_ap_timer_init_of(struct device_node *node) 159 { 160 const char *path; 161 void __iomem *base; 162 int err; 163 int irq; 164 struct clk *clk; 165 unsigned long rate; 166 struct device_node *pri_node; 167 struct device_node *sec_node; 168 169 base = of_io_request_and_map(node, 0, "integrator-timer"); 170 if (IS_ERR(base)) 171 return; 172 173 clk = of_clk_get(node, 0); 174 if (IS_ERR(clk)) { 175 pr_err("No clock for %s\n", node->name); 176 return; 177 } 178 clk_prepare_enable(clk); 179 rate = clk_get_rate(clk); 180 writel(0, base + TIMER_CTRL); 181 182 err = of_property_read_string(of_aliases, 183 "arm,timer-primary", &path); 184 if (WARN_ON(err)) 185 return; 186 pri_node = of_find_node_by_path(path); 187 err = of_property_read_string(of_aliases, 188 "arm,timer-secondary", &path); 189 if (WARN_ON(err)) 190 return; 191 sec_node = of_find_node_by_path(path); 192 193 if (node == pri_node) { 194 /* The primary timer lacks IRQ, use as clocksource */ 195 integrator_clocksource_init(rate, base); 196 return; 197 } 198 199 if (node == sec_node) { 200 /* The secondary timer will drive the clock event */ 201 irq = irq_of_parse_and_map(node, 0); 202 integrator_clockevent_init(rate, base, irq); 203 return; 204 } 205 206 pr_info("Timer @%p unused\n", base); 207 clk_disable_unprepare(clk); 208 } 209 210 CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer", 211 integrator_ap_timer_init_of); 212