1 /* 2 * Integrator/AP timer driver 3 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd 4 * Copyright (c) 2014, Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clocksource.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_address.h> 25 #include <linux/of_platform.h> 26 #include <linux/clockchips.h> 27 #include <linux/interrupt.h> 28 #include <linux/sched_clock.h> 29 30 #include "timer-sp.h" 31 32 static void __iomem * sched_clk_base; 33 34 static u64 notrace integrator_read_sched_clock(void) 35 { 36 return -readl(sched_clk_base + TIMER_VALUE); 37 } 38 39 static void integrator_clocksource_init(unsigned long inrate, 40 void __iomem *base) 41 { 42 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; 43 unsigned long rate = inrate; 44 45 if (rate >= 1500000) { 46 rate /= 16; 47 ctrl |= TIMER_CTRL_DIV16; 48 } 49 50 writel(0xffff, base + TIMER_LOAD); 51 writel(ctrl, base + TIMER_CTRL); 52 53 clocksource_mmio_init(base + TIMER_VALUE, "timer2", 54 rate, 200, 16, clocksource_mmio_readl_down); 55 56 sched_clk_base = base; 57 sched_clock_register(integrator_read_sched_clock, 16, rate); 58 } 59 60 static unsigned long timer_reload; 61 static void __iomem * clkevt_base; 62 63 /* 64 * IRQ handler for the timer 65 */ 66 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) 67 { 68 struct clock_event_device *evt = dev_id; 69 70 /* clear the interrupt */ 71 writel(1, clkevt_base + TIMER_INTCLR); 72 73 evt->event_handler(evt); 74 75 return IRQ_HANDLED; 76 } 77 78 static int clkevt_shutdown(struct clock_event_device *evt) 79 { 80 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; 81 82 /* Disable timer */ 83 writel(ctrl, clkevt_base + TIMER_CTRL); 84 return 0; 85 } 86 87 static int clkevt_set_oneshot(struct clock_event_device *evt) 88 { 89 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & 90 ~(TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC); 91 92 /* Leave the timer disabled, .set_next_event will enable it */ 93 writel(ctrl, clkevt_base + TIMER_CTRL); 94 return 0; 95 } 96 97 static int clkevt_set_periodic(struct clock_event_device *evt) 98 { 99 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; 100 101 /* Disable timer */ 102 writel(ctrl, clkevt_base + TIMER_CTRL); 103 104 /* Enable the timer and start the periodic tick */ 105 writel(timer_reload, clkevt_base + TIMER_LOAD); 106 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; 107 writel(ctrl, clkevt_base + TIMER_CTRL); 108 return 0; 109 } 110 111 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) 112 { 113 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); 114 115 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); 116 writel(next, clkevt_base + TIMER_LOAD); 117 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); 118 119 return 0; 120 } 121 122 static struct clock_event_device integrator_clockevent = { 123 .name = "timer1", 124 .features = CLOCK_EVT_FEAT_PERIODIC | 125 CLOCK_EVT_FEAT_ONESHOT, 126 .set_state_shutdown = clkevt_shutdown, 127 .set_state_periodic = clkevt_set_periodic, 128 .set_state_oneshot = clkevt_set_oneshot, 129 .tick_resume = clkevt_shutdown, 130 .set_next_event = clkevt_set_next_event, 131 .rating = 300, 132 }; 133 134 static struct irqaction integrator_timer_irq = { 135 .name = "timer", 136 .flags = IRQF_TIMER | IRQF_IRQPOLL, 137 .handler = integrator_timer_interrupt, 138 .dev_id = &integrator_clockevent, 139 }; 140 141 static void integrator_clockevent_init(unsigned long inrate, 142 void __iomem *base, int irq) 143 { 144 unsigned long rate = inrate; 145 unsigned int ctrl = 0; 146 147 clkevt_base = base; 148 /* Calculate and program a divisor */ 149 if (rate > 0x100000 * HZ) { 150 rate /= 256; 151 ctrl |= TIMER_CTRL_DIV256; 152 } else if (rate > 0x10000 * HZ) { 153 rate /= 16; 154 ctrl |= TIMER_CTRL_DIV16; 155 } 156 timer_reload = rate / HZ; 157 writel(ctrl, clkevt_base + TIMER_CTRL); 158 159 setup_irq(irq, &integrator_timer_irq); 160 clockevents_config_and_register(&integrator_clockevent, 161 rate, 162 1, 163 0xffffU); 164 } 165 166 static void __init integrator_ap_timer_init_of(struct device_node *node) 167 { 168 const char *path; 169 void __iomem *base; 170 int err; 171 int irq; 172 struct clk *clk; 173 unsigned long rate; 174 struct device_node *pri_node; 175 struct device_node *sec_node; 176 177 base = of_io_request_and_map(node, 0, "integrator-timer"); 178 if (IS_ERR(base)) 179 return; 180 181 clk = of_clk_get(node, 0); 182 if (IS_ERR(clk)) { 183 pr_err("No clock for %s\n", node->name); 184 return; 185 } 186 clk_prepare_enable(clk); 187 rate = clk_get_rate(clk); 188 writel(0, base + TIMER_CTRL); 189 190 err = of_property_read_string(of_aliases, 191 "arm,timer-primary", &path); 192 if (WARN_ON(err)) 193 return; 194 pri_node = of_find_node_by_path(path); 195 err = of_property_read_string(of_aliases, 196 "arm,timer-secondary", &path); 197 if (WARN_ON(err)) 198 return; 199 sec_node = of_find_node_by_path(path); 200 201 if (node == pri_node) { 202 /* The primary timer lacks IRQ, use as clocksource */ 203 integrator_clocksource_init(rate, base); 204 return; 205 } 206 207 if (node == sec_node) { 208 /* The secondary timer will drive the clock event */ 209 irq = irq_of_parse_and_map(node, 0); 210 integrator_clockevent_init(rate, base, irq); 211 return; 212 } 213 214 pr_info("Timer @%p unused\n", base); 215 clk_disable_unprepare(clk); 216 } 217 218 CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer", 219 integrator_ap_timer_init_of); 220