1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2017-2019 NXP
4 
5 #include <linux/interrupt.h>
6 #include <linux/clockchips.h>
7 #include <linux/of_address.h>
8 #include <linux/of_irq.h>
9 
10 #include "timer-of.h"
11 
12 #define CMP_OFFSET	0x10000
13 
14 #define CNTCV_LO	0x8
15 #define CNTCV_HI	0xc
16 #define CMPCV_LO	(CMP_OFFSET + 0x20)
17 #define CMPCV_HI	(CMP_OFFSET + 0x24)
18 #define CMPCR		(CMP_OFFSET + 0x2c)
19 
20 #define SYS_CTR_EN		0x1
21 #define SYS_CTR_IRQ_MASK	0x2
22 
23 #define SYS_CTR_CLK_DIV		0x3
24 
25 static void __iomem *sys_ctr_base;
26 static u32 cmpcr;
27 
28 static void sysctr_timer_enable(bool enable)
29 {
30 	writel(enable ? cmpcr | SYS_CTR_EN : cmpcr, sys_ctr_base + CMPCR);
31 }
32 
33 static void sysctr_irq_acknowledge(void)
34 {
35 	/*
36 	 * clear the enable bit(EN =0) will clear
37 	 * the status bit(ISTAT = 0), then the interrupt
38 	 * signal will be negated(acknowledged).
39 	 */
40 	sysctr_timer_enable(false);
41 }
42 
43 static inline u64 sysctr_read_counter(void)
44 {
45 	u32 cnt_hi, tmp_hi, cnt_lo;
46 
47 	do {
48 		cnt_hi = readl_relaxed(sys_ctr_base + CNTCV_HI);
49 		cnt_lo = readl_relaxed(sys_ctr_base + CNTCV_LO);
50 		tmp_hi = readl_relaxed(sys_ctr_base + CNTCV_HI);
51 	} while (tmp_hi != cnt_hi);
52 
53 	return  ((u64) cnt_hi << 32) | cnt_lo;
54 }
55 
56 static int sysctr_set_next_event(unsigned long delta,
57 				 struct clock_event_device *evt)
58 {
59 	u32 cmp_hi, cmp_lo;
60 	u64 next;
61 
62 	sysctr_timer_enable(false);
63 
64 	next = sysctr_read_counter();
65 
66 	next += delta;
67 
68 	cmp_hi = (next >> 32) & 0x00fffff;
69 	cmp_lo = next & 0xffffffff;
70 
71 	writel_relaxed(cmp_hi, sys_ctr_base + CMPCV_HI);
72 	writel_relaxed(cmp_lo, sys_ctr_base + CMPCV_LO);
73 
74 	sysctr_timer_enable(true);
75 
76 	return 0;
77 }
78 
79 static int sysctr_set_state_oneshot(struct clock_event_device *evt)
80 {
81 	return 0;
82 }
83 
84 static int sysctr_set_state_shutdown(struct clock_event_device *evt)
85 {
86 	sysctr_timer_enable(false);
87 
88 	return 0;
89 }
90 
91 static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
92 {
93 	struct clock_event_device *evt = dev_id;
94 
95 	sysctr_irq_acknowledge();
96 
97 	evt->event_handler(evt);
98 
99 	return IRQ_HANDLED;
100 }
101 
102 static struct timer_of to_sysctr = {
103 	.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
104 	.clkevt = {
105 		.name			= "i.MX system counter timer",
106 		.features		= CLOCK_EVT_FEAT_ONESHOT |
107 						CLOCK_EVT_FEAT_DYNIRQ,
108 		.set_state_oneshot	= sysctr_set_state_oneshot,
109 		.set_next_event		= sysctr_set_next_event,
110 		.set_state_shutdown	= sysctr_set_state_shutdown,
111 		.rating			= 200,
112 	},
113 	.of_irq = {
114 		.handler		= sysctr_timer_interrupt,
115 		.flags			= IRQF_TIMER | IRQF_IRQPOLL,
116 	},
117 	.of_clk = {
118 		.name = "per",
119 	},
120 };
121 
122 static void __init sysctr_clockevent_init(void)
123 {
124 	to_sysctr.clkevt.cpumask = cpumask_of(0);
125 
126 	clockevents_config_and_register(&to_sysctr.clkevt,
127 					timer_of_rate(&to_sysctr),
128 					0xff, 0x7fffffff);
129 }
130 
131 static int __init sysctr_timer_init(struct device_node *np)
132 {
133 	int ret = 0;
134 
135 	ret = timer_of_init(np, &to_sysctr);
136 	if (ret)
137 		return ret;
138 
139 	/* system counter clock is divided by 3 internally */
140 	to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
141 
142 	sys_ctr_base = timer_of_base(&to_sysctr);
143 	cmpcr = readl(sys_ctr_base + CMPCR);
144 	cmpcr &= ~SYS_CTR_EN;
145 
146 	sysctr_clockevent_init();
147 
148 	return 0;
149 }
150 TIMER_OF_DECLARE(sysctr_timer, "nxp,sysctr-timer", sysctr_timer_init);
151