1 /* 2 * linux/arch/arm/plat-mxc/time.c 3 * 4 * Copyright (C) 2000-2001 Deep Blue Solutions 5 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) 7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 21 * MA 02110-1301, USA. 22 */ 23 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/clockchips.h> 27 #include <linux/clk.h> 28 #include <linux/delay.h> 29 #include <linux/err.h> 30 #include <linux/sched_clock.h> 31 #include <linux/slab.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <soc/imx/timer.h> 36 37 #include <asm/mach/time.h> 38 39 /* 40 * There are 4 versions of the timer hardware on Freescale MXC hardware. 41 * - MX1/MXL 42 * - MX21, MX27. 43 * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) 44 * - MX6DL, MX6SX, MX6Q(rev1.1+) 45 */ 46 47 /* defines common for all i.MX */ 48 #define MXC_TCTL 0x00 49 #define MXC_TCTL_TEN (1 << 0) /* Enable module */ 50 #define MXC_TPRER 0x04 51 52 /* MX1, MX21, MX27 */ 53 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1) 54 #define MX1_2_TCTL_IRQEN (1 << 4) 55 #define MX1_2_TCTL_FRR (1 << 8) 56 #define MX1_2_TCMP 0x08 57 #define MX1_2_TCN 0x10 58 #define MX1_2_TSTAT 0x14 59 60 /* MX21, MX27 */ 61 #define MX2_TSTAT_CAPT (1 << 1) 62 #define MX2_TSTAT_COMP (1 << 0) 63 64 /* MX31, MX35, MX25, MX5, MX6 */ 65 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 66 #define V2_TCTL_CLK_IPG (1 << 6) 67 #define V2_TCTL_CLK_PER (2 << 6) 68 #define V2_TCTL_CLK_OSC_DIV8 (5 << 6) 69 #define V2_TCTL_FRR (1 << 9) 70 #define V2_TCTL_24MEN (1 << 10) 71 #define V2_TPRER_PRE24M 12 72 #define V2_IR 0x0c 73 #define V2_TSTAT 0x08 74 #define V2_TSTAT_OF1 (1 << 0) 75 #define V2_TCN 0x24 76 #define V2_TCMP 0x10 77 78 #define V2_TIMER_RATE_OSC_DIV8 3000000 79 80 struct imx_timer { 81 enum imx_gpt_type type; 82 void __iomem *base; 83 int irq; 84 struct clk *clk_per; 85 struct clk *clk_ipg; 86 const struct imx_gpt_data *gpt; 87 struct clock_event_device ced; 88 enum clock_event_mode cem; 89 struct irqaction act; 90 }; 91 92 struct imx_gpt_data { 93 int reg_tstat; 94 int reg_tcn; 95 int reg_tcmp; 96 void (*gpt_setup_tctl)(struct imx_timer *imxtm); 97 void (*gpt_irq_enable)(struct imx_timer *imxtm); 98 void (*gpt_irq_disable)(struct imx_timer *imxtm); 99 void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); 100 int (*set_next_event)(unsigned long evt, 101 struct clock_event_device *ced); 102 }; 103 104 static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) 105 { 106 return container_of(ced, struct imx_timer, ced); 107 } 108 109 static void imx1_gpt_irq_disable(struct imx_timer *imxtm) 110 { 111 unsigned int tmp; 112 113 tmp = readl_relaxed(imxtm->base + MXC_TCTL); 114 writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); 115 } 116 #define imx21_gpt_irq_disable imx1_gpt_irq_disable 117 118 static void imx31_gpt_irq_disable(struct imx_timer *imxtm) 119 { 120 writel_relaxed(0, imxtm->base + V2_IR); 121 } 122 #define imx6dl_gpt_irq_disable imx31_gpt_irq_disable 123 124 static void imx1_gpt_irq_enable(struct imx_timer *imxtm) 125 { 126 unsigned int tmp; 127 128 tmp = readl_relaxed(imxtm->base + MXC_TCTL); 129 writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); 130 } 131 #define imx21_gpt_irq_enable imx1_gpt_irq_enable 132 133 static void imx31_gpt_irq_enable(struct imx_timer *imxtm) 134 { 135 writel_relaxed(1<<0, imxtm->base + V2_IR); 136 } 137 #define imx6dl_gpt_irq_enable imx31_gpt_irq_enable 138 139 static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) 140 { 141 writel_relaxed(0, imxtm->base + MX1_2_TSTAT); 142 } 143 144 static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) 145 { 146 writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, 147 imxtm->base + MX1_2_TSTAT); 148 } 149 150 static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) 151 { 152 writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); 153 } 154 #define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge 155 156 static void __iomem *sched_clock_reg; 157 158 static u64 notrace mxc_read_sched_clock(void) 159 { 160 return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; 161 } 162 163 static struct delay_timer imx_delay_timer; 164 165 static unsigned long imx_read_current_timer(void) 166 { 167 return readl_relaxed(sched_clock_reg); 168 } 169 170 static int __init mxc_clocksource_init(struct imx_timer *imxtm) 171 { 172 unsigned int c = clk_get_rate(imxtm->clk_per); 173 void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; 174 175 imx_delay_timer.read_current_timer = &imx_read_current_timer; 176 imx_delay_timer.freq = c; 177 register_current_timer_delay(&imx_delay_timer); 178 179 sched_clock_reg = reg; 180 181 sched_clock_register(mxc_read_sched_clock, 32, c); 182 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, 183 clocksource_mmio_readl_up); 184 } 185 186 /* clock event */ 187 188 static int mx1_2_set_next_event(unsigned long evt, 189 struct clock_event_device *ced) 190 { 191 struct imx_timer *imxtm = to_imx_timer(ced); 192 unsigned long tcmp; 193 194 tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; 195 196 writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); 197 198 return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? 199 -ETIME : 0; 200 } 201 202 static int v2_set_next_event(unsigned long evt, 203 struct clock_event_device *ced) 204 { 205 struct imx_timer *imxtm = to_imx_timer(ced); 206 unsigned long tcmp; 207 208 tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; 209 210 writel_relaxed(tcmp, imxtm->base + V2_TCMP); 211 212 return evt < 0x7fffffff && 213 (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? 214 -ETIME : 0; 215 } 216 217 #ifdef DEBUG 218 static const char *clock_event_mode_label[] = { 219 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", 220 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", 221 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", 222 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED", 223 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME", 224 }; 225 #endif /* DEBUG */ 226 227 static void mxc_set_mode(enum clock_event_mode mode, 228 struct clock_event_device *ced) 229 { 230 struct imx_timer *imxtm = to_imx_timer(ced); 231 unsigned long flags; 232 233 /* 234 * The timer interrupt generation is disabled at least 235 * for enough time to call mxc_set_next_event() 236 */ 237 local_irq_save(flags); 238 239 /* Disable interrupt in GPT module */ 240 imxtm->gpt->gpt_irq_disable(imxtm); 241 242 if (mode != imxtm->cem) { 243 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); 244 /* Set event time into far-far future */ 245 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); 246 247 /* Clear pending interrupt */ 248 imxtm->gpt->gpt_irq_acknowledge(imxtm); 249 } 250 251 #ifdef DEBUG 252 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", 253 clock_event_mode_label[imxtm->cem], 254 clock_event_mode_label[mode]); 255 #endif /* DEBUG */ 256 257 /* Remember timer mode */ 258 imxtm->cem = mode; 259 local_irq_restore(flags); 260 261 switch (mode) { 262 case CLOCK_EVT_MODE_PERIODIC: 263 printk(KERN_ERR"mxc_set_mode: Periodic mode is not " 264 "supported for i.MX\n"); 265 break; 266 case CLOCK_EVT_MODE_ONESHOT: 267 /* 268 * Do not put overhead of interrupt enable/disable into 269 * mxc_set_next_event(), the core has about 4 minutes 270 * to call mxc_set_next_event() or shutdown clock after 271 * mode switching 272 */ 273 local_irq_save(flags); 274 imxtm->gpt->gpt_irq_enable(imxtm); 275 local_irq_restore(flags); 276 break; 277 case CLOCK_EVT_MODE_SHUTDOWN: 278 case CLOCK_EVT_MODE_UNUSED: 279 case CLOCK_EVT_MODE_RESUME: 280 /* Left event sources disabled, no more interrupts appear */ 281 break; 282 } 283 } 284 285 /* 286 * IRQ handler for the timer 287 */ 288 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) 289 { 290 struct clock_event_device *ced = dev_id; 291 struct imx_timer *imxtm = to_imx_timer(ced); 292 uint32_t tstat; 293 294 tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); 295 296 imxtm->gpt->gpt_irq_acknowledge(imxtm); 297 298 ced->event_handler(ced); 299 300 return IRQ_HANDLED; 301 } 302 303 static int __init mxc_clockevent_init(struct imx_timer *imxtm) 304 { 305 struct clock_event_device *ced = &imxtm->ced; 306 struct irqaction *act = &imxtm->act; 307 308 imxtm->cem = CLOCK_EVT_MODE_UNUSED; 309 310 ced->name = "mxc_timer1"; 311 ced->features = CLOCK_EVT_FEAT_ONESHOT; 312 ced->set_mode = mxc_set_mode; 313 ced->set_next_event = imxtm->gpt->set_next_event; 314 ced->rating = 200; 315 ced->cpumask = cpumask_of(0); 316 clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per), 317 0xff, 0xfffffffe); 318 319 act->name = "i.MX Timer Tick"; 320 act->flags = IRQF_TIMER | IRQF_IRQPOLL; 321 act->handler = mxc_timer_interrupt; 322 act->dev_id = ced; 323 324 return setup_irq(imxtm->irq, act); 325 } 326 327 static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) 328 { 329 u32 tctl_val; 330 331 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 332 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); 333 } 334 #define imx21_gpt_setup_tctl imx1_gpt_setup_tctl 335 336 static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) 337 { 338 u32 tctl_val; 339 340 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 341 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) 342 tctl_val |= V2_TCTL_CLK_OSC_DIV8; 343 else 344 tctl_val |= V2_TCTL_CLK_PER; 345 346 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); 347 } 348 349 static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) 350 { 351 u32 tctl_val; 352 353 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 354 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { 355 tctl_val |= V2_TCTL_CLK_OSC_DIV8; 356 /* 24 / 8 = 3 MHz */ 357 writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); 358 tctl_val |= V2_TCTL_24MEN; 359 } else { 360 tctl_val |= V2_TCTL_CLK_PER; 361 } 362 363 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); 364 } 365 366 static const struct imx_gpt_data imx1_gpt_data = { 367 .reg_tstat = MX1_2_TSTAT, 368 .reg_tcn = MX1_2_TCN, 369 .reg_tcmp = MX1_2_TCMP, 370 .gpt_irq_enable = imx1_gpt_irq_enable, 371 .gpt_irq_disable = imx1_gpt_irq_disable, 372 .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, 373 .gpt_setup_tctl = imx1_gpt_setup_tctl, 374 .set_next_event = mx1_2_set_next_event, 375 }; 376 377 static const struct imx_gpt_data imx21_gpt_data = { 378 .reg_tstat = MX1_2_TSTAT, 379 .reg_tcn = MX1_2_TCN, 380 .reg_tcmp = MX1_2_TCMP, 381 .gpt_irq_enable = imx21_gpt_irq_enable, 382 .gpt_irq_disable = imx21_gpt_irq_disable, 383 .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, 384 .gpt_setup_tctl = imx21_gpt_setup_tctl, 385 .set_next_event = mx1_2_set_next_event, 386 }; 387 388 static const struct imx_gpt_data imx31_gpt_data = { 389 .reg_tstat = V2_TSTAT, 390 .reg_tcn = V2_TCN, 391 .reg_tcmp = V2_TCMP, 392 .gpt_irq_enable = imx31_gpt_irq_enable, 393 .gpt_irq_disable = imx31_gpt_irq_disable, 394 .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, 395 .gpt_setup_tctl = imx31_gpt_setup_tctl, 396 .set_next_event = v2_set_next_event, 397 }; 398 399 static const struct imx_gpt_data imx6dl_gpt_data = { 400 .reg_tstat = V2_TSTAT, 401 .reg_tcn = V2_TCN, 402 .reg_tcmp = V2_TCMP, 403 .gpt_irq_enable = imx6dl_gpt_irq_enable, 404 .gpt_irq_disable = imx6dl_gpt_irq_disable, 405 .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, 406 .gpt_setup_tctl = imx6dl_gpt_setup_tctl, 407 .set_next_event = v2_set_next_event, 408 }; 409 410 static void __init _mxc_timer_init(struct imx_timer *imxtm) 411 { 412 switch (imxtm->type) { 413 case GPT_TYPE_IMX1: 414 imxtm->gpt = &imx1_gpt_data; 415 break; 416 case GPT_TYPE_IMX21: 417 imxtm->gpt = &imx21_gpt_data; 418 break; 419 case GPT_TYPE_IMX31: 420 imxtm->gpt = &imx31_gpt_data; 421 break; 422 case GPT_TYPE_IMX6DL: 423 imxtm->gpt = &imx6dl_gpt_data; 424 break; 425 default: 426 BUG(); 427 } 428 429 if (IS_ERR(imxtm->clk_per)) { 430 pr_err("i.MX timer: unable to get clk\n"); 431 return; 432 } 433 434 if (!IS_ERR(imxtm->clk_ipg)) 435 clk_prepare_enable(imxtm->clk_ipg); 436 437 clk_prepare_enable(imxtm->clk_per); 438 439 /* 440 * Initialise to a known state (all timers off, and timing reset) 441 */ 442 443 writel_relaxed(0, imxtm->base + MXC_TCTL); 444 writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ 445 446 imxtm->gpt->gpt_setup_tctl(imxtm); 447 448 /* init and register the timer to the framework */ 449 mxc_clocksource_init(imxtm); 450 mxc_clockevent_init(imxtm); 451 } 452 453 void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) 454 { 455 struct imx_timer *imxtm; 456 457 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); 458 BUG_ON(!imxtm); 459 460 imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); 461 imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); 462 463 imxtm->base = ioremap(pbase, SZ_4K); 464 BUG_ON(!imxtm->base); 465 466 imxtm->type = type; 467 468 _mxc_timer_init(imxtm); 469 } 470 471 static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) 472 { 473 struct imx_timer *imxtm; 474 static int initialized; 475 476 /* Support one instance only */ 477 if (initialized) 478 return; 479 480 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); 481 BUG_ON(!imxtm); 482 483 imxtm->base = of_iomap(np, 0); 484 WARN_ON(!imxtm->base); 485 imxtm->irq = irq_of_parse_and_map(np, 0); 486 487 imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); 488 489 /* Try osc_per first, and fall back to per otherwise */ 490 imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); 491 if (IS_ERR(imxtm->clk_per)) 492 imxtm->clk_per = of_clk_get_by_name(np, "per"); 493 494 imxtm->type = type; 495 496 _mxc_timer_init(imxtm); 497 498 initialized = 1; 499 } 500 501 static void __init imx1_timer_init_dt(struct device_node *np) 502 { 503 mxc_timer_init_dt(np, GPT_TYPE_IMX1); 504 } 505 506 static void __init imx21_timer_init_dt(struct device_node *np) 507 { 508 mxc_timer_init_dt(np, GPT_TYPE_IMX21); 509 } 510 511 static void __init imx31_timer_init_dt(struct device_node *np) 512 { 513 enum imx_gpt_type type = GPT_TYPE_IMX31; 514 515 /* 516 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S 517 * GPT device, while they actually have different programming model. 518 * This is a workaround to keep the existing i.MX6DL/S DTBs continue 519 * working with the new kernel. 520 */ 521 if (of_machine_is_compatible("fsl,imx6dl")) 522 type = GPT_TYPE_IMX6DL; 523 524 mxc_timer_init_dt(np, type); 525 } 526 527 static void __init imx6dl_timer_init_dt(struct device_node *np) 528 { 529 mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); 530 } 531 532 CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); 533 CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); 534 CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); 535 CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); 536 CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); 537 CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); 538 CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); 539 CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); 540 CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); 541 CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); 542 CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); 543