1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Faraday Technology FTTMR010 timer driver 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * Based on a rewrite of arch/arm/mach-gemini/timer.c: 7 * Copyright (C) 2001-2006 Storlink, Corp. 8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/clockchips.h> 16 #include <linux/clocksource.h> 17 #include <linux/sched_clock.h> 18 #include <linux/clk.h> 19 #include <linux/slab.h> 20 #include <linux/bitops.h> 21 #include <linux/delay.h> 22 23 /* 24 * Register definitions for the timers 25 */ 26 #define TIMER1_COUNT (0x00) 27 #define TIMER1_LOAD (0x04) 28 #define TIMER1_MATCH1 (0x08) 29 #define TIMER1_MATCH2 (0x0c) 30 #define TIMER2_COUNT (0x10) 31 #define TIMER2_LOAD (0x14) 32 #define TIMER2_MATCH1 (0x18) 33 #define TIMER2_MATCH2 (0x1c) 34 #define TIMER3_COUNT (0x20) 35 #define TIMER3_LOAD (0x24) 36 #define TIMER3_MATCH1 (0x28) 37 #define TIMER3_MATCH2 (0x2c) 38 #define TIMER_CR (0x30) 39 #define TIMER_INTR_STATE (0x34) 40 #define TIMER_INTR_MASK (0x38) 41 42 #define TIMER_1_CR_ENABLE BIT(0) 43 #define TIMER_1_CR_CLOCK BIT(1) 44 #define TIMER_1_CR_INT BIT(2) 45 #define TIMER_2_CR_ENABLE BIT(3) 46 #define TIMER_2_CR_CLOCK BIT(4) 47 #define TIMER_2_CR_INT BIT(5) 48 #define TIMER_3_CR_ENABLE BIT(6) 49 #define TIMER_3_CR_CLOCK BIT(7) 50 #define TIMER_3_CR_INT BIT(8) 51 #define TIMER_1_CR_UPDOWN BIT(9) 52 #define TIMER_2_CR_UPDOWN BIT(10) 53 #define TIMER_3_CR_UPDOWN BIT(11) 54 55 /* 56 * The Aspeed AST2400 moves bits around in the control register 57 * and lacks bits for setting the timer to count upwards. 58 */ 59 #define TIMER_1_CR_ASPEED_ENABLE BIT(0) 60 #define TIMER_1_CR_ASPEED_CLOCK BIT(1) 61 #define TIMER_1_CR_ASPEED_INT BIT(2) 62 #define TIMER_2_CR_ASPEED_ENABLE BIT(4) 63 #define TIMER_2_CR_ASPEED_CLOCK BIT(5) 64 #define TIMER_2_CR_ASPEED_INT BIT(6) 65 #define TIMER_3_CR_ASPEED_ENABLE BIT(8) 66 #define TIMER_3_CR_ASPEED_CLOCK BIT(9) 67 #define TIMER_3_CR_ASPEED_INT BIT(10) 68 69 #define TIMER_1_INT_MATCH1 BIT(0) 70 #define TIMER_1_INT_MATCH2 BIT(1) 71 #define TIMER_1_INT_OVERFLOW BIT(2) 72 #define TIMER_2_INT_MATCH1 BIT(3) 73 #define TIMER_2_INT_MATCH2 BIT(4) 74 #define TIMER_2_INT_OVERFLOW BIT(5) 75 #define TIMER_3_INT_MATCH1 BIT(6) 76 #define TIMER_3_INT_MATCH2 BIT(7) 77 #define TIMER_3_INT_OVERFLOW BIT(8) 78 #define TIMER_INT_ALL_MASK 0x1ff 79 80 struct fttmr010 { 81 void __iomem *base; 82 unsigned int tick_rate; 83 bool count_down; 84 u32 t1_enable_val; 85 struct clock_event_device clkevt; 86 #ifdef CONFIG_ARM 87 struct delay_timer delay_timer; 88 #endif 89 }; 90 91 /* 92 * A local singleton used by sched_clock and delay timer reads, which are 93 * fast and stateless 94 */ 95 static struct fttmr010 *local_fttmr; 96 97 static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) 98 { 99 return container_of(evt, struct fttmr010, clkevt); 100 } 101 102 static unsigned long fttmr010_read_current_timer_up(void) 103 { 104 return readl(local_fttmr->base + TIMER2_COUNT); 105 } 106 107 static unsigned long fttmr010_read_current_timer_down(void) 108 { 109 return ~readl(local_fttmr->base + TIMER2_COUNT); 110 } 111 112 static u64 notrace fttmr010_read_sched_clock_up(void) 113 { 114 return fttmr010_read_current_timer_up(); 115 } 116 117 static u64 notrace fttmr010_read_sched_clock_down(void) 118 { 119 return fttmr010_read_current_timer_down(); 120 } 121 122 static int fttmr010_timer_set_next_event(unsigned long cycles, 123 struct clock_event_device *evt) 124 { 125 struct fttmr010 *fttmr010 = to_fttmr010(evt); 126 u32 cr; 127 128 /* Stop */ 129 cr = readl(fttmr010->base + TIMER_CR); 130 cr &= ~fttmr010->t1_enable_val; 131 writel(cr, fttmr010->base + TIMER_CR); 132 133 /* Setup the match register forward/backward in time */ 134 cr = readl(fttmr010->base + TIMER1_COUNT); 135 if (fttmr010->count_down) 136 cr -= cycles; 137 else 138 cr += cycles; 139 writel(cr, fttmr010->base + TIMER1_MATCH1); 140 141 /* Start */ 142 cr = readl(fttmr010->base + TIMER_CR); 143 cr |= fttmr010->t1_enable_val; 144 writel(cr, fttmr010->base + TIMER_CR); 145 146 return 0; 147 } 148 149 static int fttmr010_timer_shutdown(struct clock_event_device *evt) 150 { 151 struct fttmr010 *fttmr010 = to_fttmr010(evt); 152 u32 cr; 153 154 /* Stop */ 155 cr = readl(fttmr010->base + TIMER_CR); 156 cr &= ~fttmr010->t1_enable_val; 157 writel(cr, fttmr010->base + TIMER_CR); 158 159 return 0; 160 } 161 162 static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) 163 { 164 struct fttmr010 *fttmr010 = to_fttmr010(evt); 165 u32 cr; 166 167 /* Stop */ 168 cr = readl(fttmr010->base + TIMER_CR); 169 cr &= ~fttmr010->t1_enable_val; 170 writel(cr, fttmr010->base + TIMER_CR); 171 172 /* Setup counter start from 0 or ~0 */ 173 writel(0, fttmr010->base + TIMER1_COUNT); 174 if (fttmr010->count_down) 175 writel(~0, fttmr010->base + TIMER1_LOAD); 176 else 177 writel(0, fttmr010->base + TIMER1_LOAD); 178 179 /* Enable interrupt */ 180 cr = readl(fttmr010->base + TIMER_INTR_MASK); 181 cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); 182 cr |= TIMER_1_INT_MATCH1; 183 writel(cr, fttmr010->base + TIMER_INTR_MASK); 184 185 return 0; 186 } 187 188 static int fttmr010_timer_set_periodic(struct clock_event_device *evt) 189 { 190 struct fttmr010 *fttmr010 = to_fttmr010(evt); 191 u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); 192 u32 cr; 193 194 /* Stop */ 195 cr = readl(fttmr010->base + TIMER_CR); 196 cr &= ~fttmr010->t1_enable_val; 197 writel(cr, fttmr010->base + TIMER_CR); 198 199 /* Setup timer to fire at 1/HZ intervals. */ 200 if (fttmr010->count_down) { 201 writel(period, fttmr010->base + TIMER1_LOAD); 202 writel(0, fttmr010->base + TIMER1_MATCH1); 203 } else { 204 cr = 0xffffffff - (period - 1); 205 writel(cr, fttmr010->base + TIMER1_COUNT); 206 writel(cr, fttmr010->base + TIMER1_LOAD); 207 208 /* Enable interrupt on overflow */ 209 cr = readl(fttmr010->base + TIMER_INTR_MASK); 210 cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); 211 cr |= TIMER_1_INT_OVERFLOW; 212 writel(cr, fttmr010->base + TIMER_INTR_MASK); 213 } 214 215 /* Start the timer */ 216 cr = readl(fttmr010->base + TIMER_CR); 217 cr |= fttmr010->t1_enable_val; 218 writel(cr, fttmr010->base + TIMER_CR); 219 220 return 0; 221 } 222 223 /* 224 * IRQ handler for the timer 225 */ 226 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) 227 { 228 struct clock_event_device *evt = dev_id; 229 230 evt->event_handler(evt); 231 return IRQ_HANDLED; 232 } 233 234 static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) 235 { 236 struct fttmr010 *fttmr010; 237 int irq; 238 struct clk *clk; 239 int ret; 240 u32 val; 241 242 /* 243 * These implementations require a clock reference. 244 * FIXME: we currently only support clocking using PCLK 245 * and using EXTCLK is not supported in the driver. 246 */ 247 clk = of_clk_get_by_name(np, "PCLK"); 248 if (IS_ERR(clk)) { 249 pr_err("could not get PCLK\n"); 250 return PTR_ERR(clk); 251 } 252 ret = clk_prepare_enable(clk); 253 if (ret) { 254 pr_err("failed to enable PCLK\n"); 255 return ret; 256 } 257 258 fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL); 259 if (!fttmr010) { 260 ret = -ENOMEM; 261 goto out_disable_clock; 262 } 263 fttmr010->tick_rate = clk_get_rate(clk); 264 265 fttmr010->base = of_iomap(np, 0); 266 if (!fttmr010->base) { 267 pr_err("Can't remap registers\n"); 268 ret = -ENXIO; 269 goto out_free; 270 } 271 /* IRQ for timer 1 */ 272 irq = irq_of_parse_and_map(np, 0); 273 if (irq <= 0) { 274 pr_err("Can't parse IRQ\n"); 275 ret = -EINVAL; 276 goto out_unmap; 277 } 278 279 /* 280 * The Aspeed AST2400 moves bits around in the control register, 281 * otherwise it works the same. 282 */ 283 if (is_aspeed) { 284 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | 285 TIMER_1_CR_ASPEED_INT; 286 /* Downward not available */ 287 fttmr010->count_down = true; 288 } else { 289 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; 290 } 291 292 /* 293 * Reset the interrupt mask and status 294 */ 295 writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); 296 writel(0, fttmr010->base + TIMER_INTR_STATE); 297 298 /* 299 * Enable timer 1 count up, timer 2 count up, except on Aspeed, 300 * where everything just counts down. 301 */ 302 if (is_aspeed) 303 val = TIMER_2_CR_ASPEED_ENABLE; 304 else { 305 val = TIMER_2_CR_ENABLE; 306 if (!fttmr010->count_down) 307 val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN; 308 } 309 writel(val, fttmr010->base + TIMER_CR); 310 311 /* 312 * Setup free-running clocksource timer (interrupts 313 * disabled.) 314 */ 315 local_fttmr = fttmr010; 316 writel(0, fttmr010->base + TIMER2_COUNT); 317 writel(0, fttmr010->base + TIMER2_MATCH1); 318 writel(0, fttmr010->base + TIMER2_MATCH2); 319 320 if (fttmr010->count_down) { 321 writel(~0, fttmr010->base + TIMER2_LOAD); 322 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, 323 "FTTMR010-TIMER2", 324 fttmr010->tick_rate, 325 300, 32, clocksource_mmio_readl_down); 326 sched_clock_register(fttmr010_read_sched_clock_down, 32, 327 fttmr010->tick_rate); 328 } else { 329 writel(0, fttmr010->base + TIMER2_LOAD); 330 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, 331 "FTTMR010-TIMER2", 332 fttmr010->tick_rate, 333 300, 32, clocksource_mmio_readl_up); 334 sched_clock_register(fttmr010_read_sched_clock_up, 32, 335 fttmr010->tick_rate); 336 } 337 338 /* 339 * Setup clockevent timer (interrupt-driven) on timer 1. 340 */ 341 writel(0, fttmr010->base + TIMER1_COUNT); 342 writel(0, fttmr010->base + TIMER1_LOAD); 343 writel(0, fttmr010->base + TIMER1_MATCH1); 344 writel(0, fttmr010->base + TIMER1_MATCH2); 345 ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER, 346 "FTTMR010-TIMER1", &fttmr010->clkevt); 347 if (ret) { 348 pr_err("FTTMR010-TIMER1 no IRQ\n"); 349 goto out_unmap; 350 } 351 352 fttmr010->clkevt.name = "FTTMR010-TIMER1"; 353 /* Reasonably fast and accurate clock event */ 354 fttmr010->clkevt.rating = 300; 355 fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | 356 CLOCK_EVT_FEAT_ONESHOT; 357 fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; 358 fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown; 359 fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; 360 fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; 361 fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown; 362 fttmr010->clkevt.cpumask = cpumask_of(0); 363 fttmr010->clkevt.irq = irq; 364 clockevents_config_and_register(&fttmr010->clkevt, 365 fttmr010->tick_rate, 366 1, 0xffffffff); 367 368 #ifdef CONFIG_ARM 369 /* Also use this timer for delays */ 370 if (fttmr010->count_down) 371 fttmr010->delay_timer.read_current_timer = 372 fttmr010_read_current_timer_down; 373 else 374 fttmr010->delay_timer.read_current_timer = 375 fttmr010_read_current_timer_up; 376 fttmr010->delay_timer.freq = fttmr010->tick_rate; 377 register_current_timer_delay(&fttmr010->delay_timer); 378 #endif 379 380 return 0; 381 382 out_unmap: 383 iounmap(fttmr010->base); 384 out_free: 385 kfree(fttmr010); 386 out_disable_clock: 387 clk_disable_unprepare(clk); 388 389 return ret; 390 } 391 392 static __init int aspeed_timer_init(struct device_node *np) 393 { 394 return fttmr010_common_init(np, true); 395 } 396 397 static __init int fttmr010_timer_init(struct device_node *np) 398 { 399 return fttmr010_common_init(np, false); 400 } 401 402 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); 403 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); 404 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init); 405 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init); 406 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init); 407