1 /*
2  * linux/arch/arm/mach-at91/at91rm9200_time.c
3  *
4  *  Copyright (C) 2003 SAN People
5  *  Copyright (C) 2003 ATMEL
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 
22 #include <linux/kernel.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/clockchips.h>
26 #include <linux/export.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/mfd/syscon/atmel-st.h>
29 #include <linux/of_irq.h>
30 #include <linux/regmap.h>
31 
32 static unsigned long last_crtr;
33 static u32 irqmask;
34 static struct clock_event_device clkevt;
35 static struct regmap *regmap_st;
36 
37 #define AT91_SLOW_CLOCK		32768
38 #define RM9200_TIMER_LATCH	((AT91_SLOW_CLOCK + HZ/2) / HZ)
39 
40 /*
41  * The ST_CRTR is updated asynchronously to the master clock ... but
42  * the updates as seen by the CPU don't seem to be strictly monotonic.
43  * Waiting until we read the same value twice avoids glitching.
44  */
45 static inline unsigned long read_CRTR(void)
46 {
47 	unsigned int x1, x2;
48 
49 	regmap_read(regmap_st, AT91_ST_CRTR, &x1);
50 	do {
51 		regmap_read(regmap_st, AT91_ST_CRTR, &x2);
52 		if (x1 == x2)
53 			break;
54 		x1 = x2;
55 	} while (1);
56 	return x1;
57 }
58 
59 /*
60  * IRQ handler for the timer.
61  */
62 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
63 {
64 	u32 sr;
65 
66 	regmap_read(regmap_st, AT91_ST_SR, &sr);
67 	sr &= irqmask;
68 
69 	/*
70 	 * irqs should be disabled here, but as the irq is shared they are only
71 	 * guaranteed to be off if the timer irq is registered first.
72 	 */
73 	WARN_ON_ONCE(!irqs_disabled());
74 
75 	/* simulate "oneshot" timer with alarm */
76 	if (sr & AT91_ST_ALMS) {
77 		clkevt.event_handler(&clkevt);
78 		return IRQ_HANDLED;
79 	}
80 
81 	/* periodic mode should handle delayed ticks */
82 	if (sr & AT91_ST_PITS) {
83 		u32	crtr = read_CRTR();
84 
85 		while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
86 			last_crtr += RM9200_TIMER_LATCH;
87 			clkevt.event_handler(&clkevt);
88 		}
89 		return IRQ_HANDLED;
90 	}
91 
92 	/* this irq is shared ... */
93 	return IRQ_NONE;
94 }
95 
96 static cycle_t read_clk32k(struct clocksource *cs)
97 {
98 	return read_CRTR();
99 }
100 
101 static struct clocksource clk32k = {
102 	.name		= "32k_counter",
103 	.rating		= 150,
104 	.read		= read_clk32k,
105 	.mask		= CLOCKSOURCE_MASK(20),
106 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
107 };
108 
109 static void clkdev32k_disable_and_flush_irq(void)
110 {
111 	unsigned int val;
112 
113 	/* Disable and flush pending timer interrupts */
114 	regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
115 	regmap_read(regmap_st, AT91_ST_SR, &val);
116 	last_crtr = read_CRTR();
117 }
118 
119 static int clkevt32k_shutdown(struct clock_event_device *evt)
120 {
121 	clkdev32k_disable_and_flush_irq();
122 	irqmask = 0;
123 	regmap_write(regmap_st, AT91_ST_IER, irqmask);
124 	return 0;
125 }
126 
127 static int clkevt32k_set_oneshot(struct clock_event_device *dev)
128 {
129 	clkdev32k_disable_and_flush_irq();
130 
131 	/*
132 	 * ALM for oneshot irqs, set by next_event()
133 	 * before 32 seconds have passed.
134 	 */
135 	irqmask = AT91_ST_ALMS;
136 	regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
137 	regmap_write(regmap_st, AT91_ST_IER, irqmask);
138 	return 0;
139 }
140 
141 static int clkevt32k_set_periodic(struct clock_event_device *dev)
142 {
143 	clkdev32k_disable_and_flush_irq();
144 
145 	/* PIT for periodic irqs; fixed rate of 1/HZ */
146 	irqmask = AT91_ST_PITS;
147 	regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
148 	regmap_write(regmap_st, AT91_ST_IER, irqmask);
149 	return 0;
150 }
151 
152 static int
153 clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
154 {
155 	u32		alm;
156 	int		status = 0;
157 	unsigned int	val;
158 
159 	BUG_ON(delta < 2);
160 
161 	/* The alarm IRQ uses absolute time (now+delta), not the relative
162 	 * time (delta) in our calling convention.  Like all clockevents
163 	 * using such "match" hardware, we have a race to defend against.
164 	 *
165 	 * Our defense here is to have set up the clockevent device so the
166 	 * delta is at least two.  That way we never end up writing RTAR
167 	 * with the value then held in CRTR ... which would mean the match
168 	 * wouldn't trigger until 32 seconds later, after CRTR wraps.
169 	 */
170 	alm = read_CRTR();
171 
172 	/* Cancel any pending alarm; flush any pending IRQ */
173 	regmap_write(regmap_st, AT91_ST_RTAR, alm);
174 	regmap_read(regmap_st, AT91_ST_SR, &val);
175 
176 	/* Schedule alarm by writing RTAR. */
177 	alm += delta;
178 	regmap_write(regmap_st, AT91_ST_RTAR, alm);
179 
180 	return status;
181 }
182 
183 static struct clock_event_device clkevt = {
184 	.name			= "at91_tick",
185 	.features		= CLOCK_EVT_FEAT_PERIODIC |
186 				  CLOCK_EVT_FEAT_ONESHOT,
187 	.rating			= 150,
188 	.set_next_event		= clkevt32k_next_event,
189 	.set_state_shutdown	= clkevt32k_shutdown,
190 	.set_state_periodic	= clkevt32k_set_periodic,
191 	.set_state_oneshot	= clkevt32k_set_oneshot,
192 	.tick_resume		= clkevt32k_shutdown,
193 };
194 
195 /*
196  * ST (system timer) module supports both clockevents and clocksource.
197  */
198 static void __init atmel_st_timer_init(struct device_node *node)
199 {
200 	unsigned int val;
201 	int irq, ret;
202 
203 	regmap_st = syscon_node_to_regmap(node);
204 	if (IS_ERR(regmap_st))
205 		panic(pr_fmt("Unable to get regmap\n"));
206 
207 	/* Disable all timer interrupts, and clear any pending ones */
208 	regmap_write(regmap_st, AT91_ST_IDR,
209 		AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
210 	regmap_read(regmap_st, AT91_ST_SR, &val);
211 
212 	/* Get the interrupts property */
213 	irq  = irq_of_parse_and_map(node, 0);
214 	if (!irq)
215 		panic(pr_fmt("Unable to get IRQ from DT\n"));
216 
217 	/* Make IRQs happen for the system timer */
218 	ret = request_irq(irq, at91rm9200_timer_interrupt,
219 			  IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
220 			  "at91_tick", regmap_st);
221 	if (ret)
222 		panic(pr_fmt("Unable to setup IRQ\n"));
223 
224 	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
225 	 * directly for the clocksource and all clockevents, after adjusting
226 	 * its prescaler from the 1 Hz default.
227 	 */
228 	regmap_write(regmap_st, AT91_ST_RTMR, 1);
229 
230 	/* Setup timer clockevent, with minimum of two ticks (important!!) */
231 	clkevt.cpumask = cpumask_of(0);
232 	clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
233 					2, AT91_ST_ALMV);
234 
235 	/* register clocksource */
236 	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
237 }
238 CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
239 		       atmel_st_timer_init);
240