1b53cdd03SAlexandre Belloni /* 2b53cdd03SAlexandre Belloni * linux/arch/arm/mach-at91/at91rm9200_time.c 3b53cdd03SAlexandre Belloni * 4b53cdd03SAlexandre Belloni * Copyright (C) 2003 SAN People 5b53cdd03SAlexandre Belloni * Copyright (C) 2003 ATMEL 6b53cdd03SAlexandre Belloni * 7b53cdd03SAlexandre Belloni * This program is free software; you can redistribute it and/or modify 8b53cdd03SAlexandre Belloni * it under the terms of the GNU General Public License as published by 9b53cdd03SAlexandre Belloni * the Free Software Foundation; either version 2 of the License, or 10b53cdd03SAlexandre Belloni * (at your option) any later version. 11b53cdd03SAlexandre Belloni * 12b53cdd03SAlexandre Belloni * This program is distributed in the hope that it will be useful, 13b53cdd03SAlexandre Belloni * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b53cdd03SAlexandre Belloni * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b53cdd03SAlexandre Belloni * GNU General Public License for more details. 16b53cdd03SAlexandre Belloni * 17b53cdd03SAlexandre Belloni * You should have received a copy of the GNU General Public License 18b53cdd03SAlexandre Belloni * along with this program; if not, write to the Free Software 19b53cdd03SAlexandre Belloni * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20b53cdd03SAlexandre Belloni */ 21b53cdd03SAlexandre Belloni 22b53cdd03SAlexandre Belloni #include <linux/kernel.h> 23b53cdd03SAlexandre Belloni #include <linux/interrupt.h> 24b53cdd03SAlexandre Belloni #include <linux/irq.h> 25216ab8f1SAlexandre Belloni #include <linux/clk.h> 26b53cdd03SAlexandre Belloni #include <linux/clockchips.h> 27b53cdd03SAlexandre Belloni #include <linux/export.h> 28adf2edfdSAlexandre Belloni #include <linux/mfd/syscon.h> 29adf2edfdSAlexandre Belloni #include <linux/mfd/syscon/atmel-st.h> 30b53cdd03SAlexandre Belloni #include <linux/of_irq.h> 31adf2edfdSAlexandre Belloni #include <linux/regmap.h> 32b53cdd03SAlexandre Belloni 33b53cdd03SAlexandre Belloni static unsigned long last_crtr; 34b53cdd03SAlexandre Belloni static u32 irqmask; 35b53cdd03SAlexandre Belloni static struct clock_event_device clkevt; 36adf2edfdSAlexandre Belloni static struct regmap *regmap_st; 37216ab8f1SAlexandre Belloni static int timer_latch; 38b53cdd03SAlexandre Belloni 39b53cdd03SAlexandre Belloni /* 40b53cdd03SAlexandre Belloni * The ST_CRTR is updated asynchronously to the master clock ... but 41b53cdd03SAlexandre Belloni * the updates as seen by the CPU don't seem to be strictly monotonic. 42b53cdd03SAlexandre Belloni * Waiting until we read the same value twice avoids glitching. 43b53cdd03SAlexandre Belloni */ 44b53cdd03SAlexandre Belloni static inline unsigned long read_CRTR(void) 45b53cdd03SAlexandre Belloni { 46adf2edfdSAlexandre Belloni unsigned int x1, x2; 47b53cdd03SAlexandre Belloni 48adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_CRTR, &x1); 49b53cdd03SAlexandre Belloni do { 50adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_CRTR, &x2); 51b53cdd03SAlexandre Belloni if (x1 == x2) 52b53cdd03SAlexandre Belloni break; 53b53cdd03SAlexandre Belloni x1 = x2; 54b53cdd03SAlexandre Belloni } while (1); 55b53cdd03SAlexandre Belloni return x1; 56b53cdd03SAlexandre Belloni } 57b53cdd03SAlexandre Belloni 58b53cdd03SAlexandre Belloni /* 59b53cdd03SAlexandre Belloni * IRQ handler for the timer. 60b53cdd03SAlexandre Belloni */ 61b53cdd03SAlexandre Belloni static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) 62b53cdd03SAlexandre Belloni { 63adf2edfdSAlexandre Belloni u32 sr; 64adf2edfdSAlexandre Belloni 65adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &sr); 66adf2edfdSAlexandre Belloni sr &= irqmask; 67b53cdd03SAlexandre Belloni 68b53cdd03SAlexandre Belloni /* 69b53cdd03SAlexandre Belloni * irqs should be disabled here, but as the irq is shared they are only 70b53cdd03SAlexandre Belloni * guaranteed to be off if the timer irq is registered first. 71b53cdd03SAlexandre Belloni */ 72b53cdd03SAlexandre Belloni WARN_ON_ONCE(!irqs_disabled()); 73b53cdd03SAlexandre Belloni 74b53cdd03SAlexandre Belloni /* simulate "oneshot" timer with alarm */ 75b53cdd03SAlexandre Belloni if (sr & AT91_ST_ALMS) { 76b53cdd03SAlexandre Belloni clkevt.event_handler(&clkevt); 77b53cdd03SAlexandre Belloni return IRQ_HANDLED; 78b53cdd03SAlexandre Belloni } 79b53cdd03SAlexandre Belloni 80b53cdd03SAlexandre Belloni /* periodic mode should handle delayed ticks */ 81b53cdd03SAlexandre Belloni if (sr & AT91_ST_PITS) { 82b53cdd03SAlexandre Belloni u32 crtr = read_CRTR(); 83b53cdd03SAlexandre Belloni 84216ab8f1SAlexandre Belloni while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) { 85216ab8f1SAlexandre Belloni last_crtr += timer_latch; 86b53cdd03SAlexandre Belloni clkevt.event_handler(&clkevt); 87b53cdd03SAlexandre Belloni } 88b53cdd03SAlexandre Belloni return IRQ_HANDLED; 89b53cdd03SAlexandre Belloni } 90b53cdd03SAlexandre Belloni 91b53cdd03SAlexandre Belloni /* this irq is shared ... */ 92b53cdd03SAlexandre Belloni return IRQ_NONE; 93b53cdd03SAlexandre Belloni } 94b53cdd03SAlexandre Belloni 95b53cdd03SAlexandre Belloni static cycle_t read_clk32k(struct clocksource *cs) 96b53cdd03SAlexandre Belloni { 97b53cdd03SAlexandre Belloni return read_CRTR(); 98b53cdd03SAlexandre Belloni } 99b53cdd03SAlexandre Belloni 100b53cdd03SAlexandre Belloni static struct clocksource clk32k = { 101b53cdd03SAlexandre Belloni .name = "32k_counter", 102b53cdd03SAlexandre Belloni .rating = 150, 103b53cdd03SAlexandre Belloni .read = read_clk32k, 104b53cdd03SAlexandre Belloni .mask = CLOCKSOURCE_MASK(20), 105b53cdd03SAlexandre Belloni .flags = CLOCK_SOURCE_IS_CONTINUOUS, 106b53cdd03SAlexandre Belloni }; 107b53cdd03SAlexandre Belloni 1088ab28230SViresh Kumar static void clkdev32k_disable_and_flush_irq(void) 109b53cdd03SAlexandre Belloni { 110adf2edfdSAlexandre Belloni unsigned int val; 111adf2edfdSAlexandre Belloni 112b53cdd03SAlexandre Belloni /* Disable and flush pending timer interrupts */ 113adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); 114adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &val); 115b53cdd03SAlexandre Belloni last_crtr = read_CRTR(); 1168ab28230SViresh Kumar } 1178ab28230SViresh Kumar 1188ab28230SViresh Kumar static int clkevt32k_shutdown(struct clock_event_device *evt) 1198ab28230SViresh Kumar { 1208ab28230SViresh Kumar clkdev32k_disable_and_flush_irq(); 1218ab28230SViresh Kumar irqmask = 0; 1228ab28230SViresh Kumar regmap_write(regmap_st, AT91_ST_IER, irqmask); 1238ab28230SViresh Kumar return 0; 1248ab28230SViresh Kumar } 1258ab28230SViresh Kumar 1268ab28230SViresh Kumar static int clkevt32k_set_oneshot(struct clock_event_device *dev) 1278ab28230SViresh Kumar { 1288ab28230SViresh Kumar clkdev32k_disable_and_flush_irq(); 1298ab28230SViresh Kumar 1308ab28230SViresh Kumar /* 1318ab28230SViresh Kumar * ALM for oneshot irqs, set by next_event() 1328ab28230SViresh Kumar * before 32 seconds have passed. 133b53cdd03SAlexandre Belloni */ 134b53cdd03SAlexandre Belloni irqmask = AT91_ST_ALMS; 135adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTAR, last_crtr); 136adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_IER, irqmask); 1378ab28230SViresh Kumar return 0; 1388ab28230SViresh Kumar } 1398ab28230SViresh Kumar 1408ab28230SViresh Kumar static int clkevt32k_set_periodic(struct clock_event_device *dev) 1418ab28230SViresh Kumar { 1428ab28230SViresh Kumar clkdev32k_disable_and_flush_irq(); 1438ab28230SViresh Kumar 1448ab28230SViresh Kumar /* PIT for periodic irqs; fixed rate of 1/HZ */ 1458ab28230SViresh Kumar irqmask = AT91_ST_PITS; 146216ab8f1SAlexandre Belloni regmap_write(regmap_st, AT91_ST_PIMR, timer_latch); 1478ab28230SViresh Kumar regmap_write(regmap_st, AT91_ST_IER, irqmask); 1488ab28230SViresh Kumar return 0; 149b53cdd03SAlexandre Belloni } 150b53cdd03SAlexandre Belloni 151b53cdd03SAlexandre Belloni static int 152b53cdd03SAlexandre Belloni clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) 153b53cdd03SAlexandre Belloni { 154b53cdd03SAlexandre Belloni u32 alm; 155b53cdd03SAlexandre Belloni int status = 0; 156adf2edfdSAlexandre Belloni unsigned int val; 157b53cdd03SAlexandre Belloni 158b53cdd03SAlexandre Belloni BUG_ON(delta < 2); 159b53cdd03SAlexandre Belloni 160b53cdd03SAlexandre Belloni /* The alarm IRQ uses absolute time (now+delta), not the relative 161b53cdd03SAlexandre Belloni * time (delta) in our calling convention. Like all clockevents 162b53cdd03SAlexandre Belloni * using such "match" hardware, we have a race to defend against. 163b53cdd03SAlexandre Belloni * 164b53cdd03SAlexandre Belloni * Our defense here is to have set up the clockevent device so the 165b53cdd03SAlexandre Belloni * delta is at least two. That way we never end up writing RTAR 166b53cdd03SAlexandre Belloni * with the value then held in CRTR ... which would mean the match 167b53cdd03SAlexandre Belloni * wouldn't trigger until 32 seconds later, after CRTR wraps. 168b53cdd03SAlexandre Belloni */ 169b53cdd03SAlexandre Belloni alm = read_CRTR(); 170b53cdd03SAlexandre Belloni 171b53cdd03SAlexandre Belloni /* Cancel any pending alarm; flush any pending IRQ */ 172adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTAR, alm); 173adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &val); 174b53cdd03SAlexandre Belloni 175b53cdd03SAlexandre Belloni /* Schedule alarm by writing RTAR. */ 176b53cdd03SAlexandre Belloni alm += delta; 177adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTAR, alm); 178b53cdd03SAlexandre Belloni 179b53cdd03SAlexandre Belloni return status; 180b53cdd03SAlexandre Belloni } 181b53cdd03SAlexandre Belloni 182b53cdd03SAlexandre Belloni static struct clock_event_device clkevt = { 183b53cdd03SAlexandre Belloni .name = "at91_tick", 1848ab28230SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 1858ab28230SViresh Kumar CLOCK_EVT_FEAT_ONESHOT, 186b53cdd03SAlexandre Belloni .rating = 150, 187b53cdd03SAlexandre Belloni .set_next_event = clkevt32k_next_event, 1888ab28230SViresh Kumar .set_state_shutdown = clkevt32k_shutdown, 1898ab28230SViresh Kumar .set_state_periodic = clkevt32k_set_periodic, 1908ab28230SViresh Kumar .set_state_oneshot = clkevt32k_set_oneshot, 1918ab28230SViresh Kumar .tick_resume = clkevt32k_shutdown, 192b53cdd03SAlexandre Belloni }; 193b53cdd03SAlexandre Belloni 194b53cdd03SAlexandre Belloni /* 195b53cdd03SAlexandre Belloni * ST (system timer) module supports both clockevents and clocksource. 196b53cdd03SAlexandre Belloni */ 197b53cdd03SAlexandre Belloni static void __init atmel_st_timer_init(struct device_node *node) 198b53cdd03SAlexandre Belloni { 199216ab8f1SAlexandre Belloni struct clk *sclk; 200216ab8f1SAlexandre Belloni unsigned int sclk_rate, val; 2010afb46b2SAlexandre Belloni int irq, ret; 202adf2edfdSAlexandre Belloni 203adf2edfdSAlexandre Belloni regmap_st = syscon_node_to_regmap(node); 204adf2edfdSAlexandre Belloni if (IS_ERR(regmap_st)) 205adf2edfdSAlexandre Belloni panic(pr_fmt("Unable to get regmap\n")); 206b53cdd03SAlexandre Belloni 207b53cdd03SAlexandre Belloni /* Disable all timer interrupts, and clear any pending ones */ 208adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_IDR, 209b53cdd03SAlexandre Belloni AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); 210adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &val); 211adf2edfdSAlexandre Belloni 212adf2edfdSAlexandre Belloni /* Get the interrupts property */ 2130afb46b2SAlexandre Belloni irq = irq_of_parse_and_map(node, 0); 2140afb46b2SAlexandre Belloni if (!irq) 215adf2edfdSAlexandre Belloni panic(pr_fmt("Unable to get IRQ from DT\n")); 216b53cdd03SAlexandre Belloni 217b53cdd03SAlexandre Belloni /* Make IRQs happen for the system timer */ 2180afb46b2SAlexandre Belloni ret = request_irq(irq, at91rm9200_timer_interrupt, 2190afb46b2SAlexandre Belloni IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, 2200afb46b2SAlexandre Belloni "at91_tick", regmap_st); 2210afb46b2SAlexandre Belloni if (ret) 2220afb46b2SAlexandre Belloni panic(pr_fmt("Unable to setup IRQ\n")); 223b53cdd03SAlexandre Belloni 224216ab8f1SAlexandre Belloni sclk = of_clk_get(node, 0); 225216ab8f1SAlexandre Belloni if (IS_ERR(sclk)) 226216ab8f1SAlexandre Belloni panic(pr_fmt("Unable to get slow clock\n")); 227216ab8f1SAlexandre Belloni 228216ab8f1SAlexandre Belloni clk_prepare_enable(sclk); 229216ab8f1SAlexandre Belloni if (ret) 230216ab8f1SAlexandre Belloni panic(pr_fmt("Could not enable slow clock\n")); 231216ab8f1SAlexandre Belloni 232216ab8f1SAlexandre Belloni sclk_rate = clk_get_rate(sclk); 233216ab8f1SAlexandre Belloni if (!sclk_rate) 234216ab8f1SAlexandre Belloni panic(pr_fmt("Invalid slow clock rate\n")); 235216ab8f1SAlexandre Belloni timer_latch = (sclk_rate + HZ / 2) / HZ; 236216ab8f1SAlexandre Belloni 237b53cdd03SAlexandre Belloni /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used 238b53cdd03SAlexandre Belloni * directly for the clocksource and all clockevents, after adjusting 239b53cdd03SAlexandre Belloni * its prescaler from the 1 Hz default. 240b53cdd03SAlexandre Belloni */ 241adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTMR, 1); 242b53cdd03SAlexandre Belloni 243b53cdd03SAlexandre Belloni /* Setup timer clockevent, with minimum of two ticks (important!!) */ 244b53cdd03SAlexandre Belloni clkevt.cpumask = cpumask_of(0); 245216ab8f1SAlexandre Belloni clockevents_config_and_register(&clkevt, sclk_rate, 246b53cdd03SAlexandre Belloni 2, AT91_ST_ALMV); 247b53cdd03SAlexandre Belloni 248b53cdd03SAlexandre Belloni /* register clocksource */ 249216ab8f1SAlexandre Belloni clocksource_register_hz(&clk32k, sclk_rate); 250b53cdd03SAlexandre Belloni } 251b53cdd03SAlexandre Belloni CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st", 252b53cdd03SAlexandre Belloni atmel_st_timer_init); 253