1b53cdd03SAlexandre Belloni /* 2b53cdd03SAlexandre Belloni * linux/arch/arm/mach-at91/at91rm9200_time.c 3b53cdd03SAlexandre Belloni * 4b53cdd03SAlexandre Belloni * Copyright (C) 2003 SAN People 5b53cdd03SAlexandre Belloni * Copyright (C) 2003 ATMEL 6b53cdd03SAlexandre Belloni * 7b53cdd03SAlexandre Belloni * This program is free software; you can redistribute it and/or modify 8b53cdd03SAlexandre Belloni * it under the terms of the GNU General Public License as published by 9b53cdd03SAlexandre Belloni * the Free Software Foundation; either version 2 of the License, or 10b53cdd03SAlexandre Belloni * (at your option) any later version. 11b53cdd03SAlexandre Belloni * 12b53cdd03SAlexandre Belloni * This program is distributed in the hope that it will be useful, 13b53cdd03SAlexandre Belloni * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b53cdd03SAlexandre Belloni * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b53cdd03SAlexandre Belloni * GNU General Public License for more details. 16b53cdd03SAlexandre Belloni * 17b53cdd03SAlexandre Belloni * You should have received a copy of the GNU General Public License 18b53cdd03SAlexandre Belloni * along with this program; if not, write to the Free Software 19b53cdd03SAlexandre Belloni * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20b53cdd03SAlexandre Belloni */ 21b53cdd03SAlexandre Belloni 22b53cdd03SAlexandre Belloni #include <linux/kernel.h> 23b53cdd03SAlexandre Belloni #include <linux/interrupt.h> 24b53cdd03SAlexandre Belloni #include <linux/irq.h> 25b53cdd03SAlexandre Belloni #include <linux/clockchips.h> 26b53cdd03SAlexandre Belloni #include <linux/export.h> 27adf2edfdSAlexandre Belloni #include <linux/mfd/syscon.h> 28adf2edfdSAlexandre Belloni #include <linux/mfd/syscon/atmel-st.h> 29b53cdd03SAlexandre Belloni #include <linux/of_irq.h> 30adf2edfdSAlexandre Belloni #include <linux/regmap.h> 31b53cdd03SAlexandre Belloni 32b53cdd03SAlexandre Belloni static unsigned long last_crtr; 33b53cdd03SAlexandre Belloni static u32 irqmask; 34b53cdd03SAlexandre Belloni static struct clock_event_device clkevt; 35adf2edfdSAlexandre Belloni static struct regmap *regmap_st; 36b53cdd03SAlexandre Belloni 370afb46b2SAlexandre Belloni #define AT91_SLOW_CLOCK 32768 38b53cdd03SAlexandre Belloni #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) 39b53cdd03SAlexandre Belloni 40b53cdd03SAlexandre Belloni /* 41b53cdd03SAlexandre Belloni * The ST_CRTR is updated asynchronously to the master clock ... but 42b53cdd03SAlexandre Belloni * the updates as seen by the CPU don't seem to be strictly monotonic. 43b53cdd03SAlexandre Belloni * Waiting until we read the same value twice avoids glitching. 44b53cdd03SAlexandre Belloni */ 45b53cdd03SAlexandre Belloni static inline unsigned long read_CRTR(void) 46b53cdd03SAlexandre Belloni { 47adf2edfdSAlexandre Belloni unsigned int x1, x2; 48b53cdd03SAlexandre Belloni 49adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_CRTR, &x1); 50b53cdd03SAlexandre Belloni do { 51adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_CRTR, &x2); 52b53cdd03SAlexandre Belloni if (x1 == x2) 53b53cdd03SAlexandre Belloni break; 54b53cdd03SAlexandre Belloni x1 = x2; 55b53cdd03SAlexandre Belloni } while (1); 56b53cdd03SAlexandre Belloni return x1; 57b53cdd03SAlexandre Belloni } 58b53cdd03SAlexandre Belloni 59b53cdd03SAlexandre Belloni /* 60b53cdd03SAlexandre Belloni * IRQ handler for the timer. 61b53cdd03SAlexandre Belloni */ 62b53cdd03SAlexandre Belloni static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) 63b53cdd03SAlexandre Belloni { 64adf2edfdSAlexandre Belloni u32 sr; 65adf2edfdSAlexandre Belloni 66adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &sr); 67adf2edfdSAlexandre Belloni sr &= irqmask; 68b53cdd03SAlexandre Belloni 69b53cdd03SAlexandre Belloni /* 70b53cdd03SAlexandre Belloni * irqs should be disabled here, but as the irq is shared they are only 71b53cdd03SAlexandre Belloni * guaranteed to be off if the timer irq is registered first. 72b53cdd03SAlexandre Belloni */ 73b53cdd03SAlexandre Belloni WARN_ON_ONCE(!irqs_disabled()); 74b53cdd03SAlexandre Belloni 75b53cdd03SAlexandre Belloni /* simulate "oneshot" timer with alarm */ 76b53cdd03SAlexandre Belloni if (sr & AT91_ST_ALMS) { 77b53cdd03SAlexandre Belloni clkevt.event_handler(&clkevt); 78b53cdd03SAlexandre Belloni return IRQ_HANDLED; 79b53cdd03SAlexandre Belloni } 80b53cdd03SAlexandre Belloni 81b53cdd03SAlexandre Belloni /* periodic mode should handle delayed ticks */ 82b53cdd03SAlexandre Belloni if (sr & AT91_ST_PITS) { 83b53cdd03SAlexandre Belloni u32 crtr = read_CRTR(); 84b53cdd03SAlexandre Belloni 85b53cdd03SAlexandre Belloni while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { 86b53cdd03SAlexandre Belloni last_crtr += RM9200_TIMER_LATCH; 87b53cdd03SAlexandre Belloni clkevt.event_handler(&clkevt); 88b53cdd03SAlexandre Belloni } 89b53cdd03SAlexandre Belloni return IRQ_HANDLED; 90b53cdd03SAlexandre Belloni } 91b53cdd03SAlexandre Belloni 92b53cdd03SAlexandre Belloni /* this irq is shared ... */ 93b53cdd03SAlexandre Belloni return IRQ_NONE; 94b53cdd03SAlexandre Belloni } 95b53cdd03SAlexandre Belloni 96b53cdd03SAlexandre Belloni static cycle_t read_clk32k(struct clocksource *cs) 97b53cdd03SAlexandre Belloni { 98b53cdd03SAlexandre Belloni return read_CRTR(); 99b53cdd03SAlexandre Belloni } 100b53cdd03SAlexandre Belloni 101b53cdd03SAlexandre Belloni static struct clocksource clk32k = { 102b53cdd03SAlexandre Belloni .name = "32k_counter", 103b53cdd03SAlexandre Belloni .rating = 150, 104b53cdd03SAlexandre Belloni .read = read_clk32k, 105b53cdd03SAlexandre Belloni .mask = CLOCKSOURCE_MASK(20), 106b53cdd03SAlexandre Belloni .flags = CLOCK_SOURCE_IS_CONTINUOUS, 107b53cdd03SAlexandre Belloni }; 108b53cdd03SAlexandre Belloni 109b53cdd03SAlexandre Belloni static void 110b53cdd03SAlexandre Belloni clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) 111b53cdd03SAlexandre Belloni { 112adf2edfdSAlexandre Belloni unsigned int val; 113adf2edfdSAlexandre Belloni 114b53cdd03SAlexandre Belloni /* Disable and flush pending timer interrupts */ 115adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); 116adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &val); 117b53cdd03SAlexandre Belloni 118b53cdd03SAlexandre Belloni last_crtr = read_CRTR(); 119b53cdd03SAlexandre Belloni switch (mode) { 120b53cdd03SAlexandre Belloni case CLOCK_EVT_MODE_PERIODIC: 121b53cdd03SAlexandre Belloni /* PIT for periodic irqs; fixed rate of 1/HZ */ 122b53cdd03SAlexandre Belloni irqmask = AT91_ST_PITS; 123adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH); 124b53cdd03SAlexandre Belloni break; 125b53cdd03SAlexandre Belloni case CLOCK_EVT_MODE_ONESHOT: 126b53cdd03SAlexandre Belloni /* ALM for oneshot irqs, set by next_event() 127b53cdd03SAlexandre Belloni * before 32 seconds have passed 128b53cdd03SAlexandre Belloni */ 129b53cdd03SAlexandre Belloni irqmask = AT91_ST_ALMS; 130adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTAR, last_crtr); 131b53cdd03SAlexandre Belloni break; 132b53cdd03SAlexandre Belloni case CLOCK_EVT_MODE_SHUTDOWN: 133b53cdd03SAlexandre Belloni case CLOCK_EVT_MODE_UNUSED: 134b53cdd03SAlexandre Belloni case CLOCK_EVT_MODE_RESUME: 135b53cdd03SAlexandre Belloni irqmask = 0; 136b53cdd03SAlexandre Belloni break; 137b53cdd03SAlexandre Belloni } 138adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_IER, irqmask); 139b53cdd03SAlexandre Belloni } 140b53cdd03SAlexandre Belloni 141b53cdd03SAlexandre Belloni static int 142b53cdd03SAlexandre Belloni clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) 143b53cdd03SAlexandre Belloni { 144b53cdd03SAlexandre Belloni u32 alm; 145b53cdd03SAlexandre Belloni int status = 0; 146adf2edfdSAlexandre Belloni unsigned int val; 147b53cdd03SAlexandre Belloni 148b53cdd03SAlexandre Belloni BUG_ON(delta < 2); 149b53cdd03SAlexandre Belloni 150b53cdd03SAlexandre Belloni /* The alarm IRQ uses absolute time (now+delta), not the relative 151b53cdd03SAlexandre Belloni * time (delta) in our calling convention. Like all clockevents 152b53cdd03SAlexandre Belloni * using such "match" hardware, we have a race to defend against. 153b53cdd03SAlexandre Belloni * 154b53cdd03SAlexandre Belloni * Our defense here is to have set up the clockevent device so the 155b53cdd03SAlexandre Belloni * delta is at least two. That way we never end up writing RTAR 156b53cdd03SAlexandre Belloni * with the value then held in CRTR ... which would mean the match 157b53cdd03SAlexandre Belloni * wouldn't trigger until 32 seconds later, after CRTR wraps. 158b53cdd03SAlexandre Belloni */ 159b53cdd03SAlexandre Belloni alm = read_CRTR(); 160b53cdd03SAlexandre Belloni 161b53cdd03SAlexandre Belloni /* Cancel any pending alarm; flush any pending IRQ */ 162adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTAR, alm); 163adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &val); 164b53cdd03SAlexandre Belloni 165b53cdd03SAlexandre Belloni /* Schedule alarm by writing RTAR. */ 166b53cdd03SAlexandre Belloni alm += delta; 167adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTAR, alm); 168b53cdd03SAlexandre Belloni 169b53cdd03SAlexandre Belloni return status; 170b53cdd03SAlexandre Belloni } 171b53cdd03SAlexandre Belloni 172b53cdd03SAlexandre Belloni static struct clock_event_device clkevt = { 173b53cdd03SAlexandre Belloni .name = "at91_tick", 174b53cdd03SAlexandre Belloni .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 175b53cdd03SAlexandre Belloni .rating = 150, 176b53cdd03SAlexandre Belloni .set_next_event = clkevt32k_next_event, 177b53cdd03SAlexandre Belloni .set_mode = clkevt32k_mode, 178b53cdd03SAlexandre Belloni }; 179b53cdd03SAlexandre Belloni 180b53cdd03SAlexandre Belloni /* 181b53cdd03SAlexandre Belloni * ST (system timer) module supports both clockevents and clocksource. 182b53cdd03SAlexandre Belloni */ 183b53cdd03SAlexandre Belloni static void __init atmel_st_timer_init(struct device_node *node) 184b53cdd03SAlexandre Belloni { 185adf2edfdSAlexandre Belloni unsigned int val; 1860afb46b2SAlexandre Belloni int irq, ret; 187adf2edfdSAlexandre Belloni 188adf2edfdSAlexandre Belloni regmap_st = syscon_node_to_regmap(node); 189adf2edfdSAlexandre Belloni if (IS_ERR(regmap_st)) 190adf2edfdSAlexandre Belloni panic(pr_fmt("Unable to get regmap\n")); 191b53cdd03SAlexandre Belloni 192b53cdd03SAlexandre Belloni /* Disable all timer interrupts, and clear any pending ones */ 193adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_IDR, 194b53cdd03SAlexandre Belloni AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); 195adf2edfdSAlexandre Belloni regmap_read(regmap_st, AT91_ST_SR, &val); 196adf2edfdSAlexandre Belloni 197adf2edfdSAlexandre Belloni /* Get the interrupts property */ 1980afb46b2SAlexandre Belloni irq = irq_of_parse_and_map(node, 0); 1990afb46b2SAlexandre Belloni if (!irq) 200adf2edfdSAlexandre Belloni panic(pr_fmt("Unable to get IRQ from DT\n")); 201b53cdd03SAlexandre Belloni 202b53cdd03SAlexandre Belloni /* Make IRQs happen for the system timer */ 2030afb46b2SAlexandre Belloni ret = request_irq(irq, at91rm9200_timer_interrupt, 2040afb46b2SAlexandre Belloni IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, 2050afb46b2SAlexandre Belloni "at91_tick", regmap_st); 2060afb46b2SAlexandre Belloni if (ret) 2070afb46b2SAlexandre Belloni panic(pr_fmt("Unable to setup IRQ\n")); 208b53cdd03SAlexandre Belloni 209b53cdd03SAlexandre Belloni /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used 210b53cdd03SAlexandre Belloni * directly for the clocksource and all clockevents, after adjusting 211b53cdd03SAlexandre Belloni * its prescaler from the 1 Hz default. 212b53cdd03SAlexandre Belloni */ 213adf2edfdSAlexandre Belloni regmap_write(regmap_st, AT91_ST_RTMR, 1); 214b53cdd03SAlexandre Belloni 215b53cdd03SAlexandre Belloni /* Setup timer clockevent, with minimum of two ticks (important!!) */ 216b53cdd03SAlexandre Belloni clkevt.cpumask = cpumask_of(0); 217b53cdd03SAlexandre Belloni clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, 218b53cdd03SAlexandre Belloni 2, AT91_ST_ALMV); 219b53cdd03SAlexandre Belloni 220b53cdd03SAlexandre Belloni /* register clocksource */ 221b53cdd03SAlexandre Belloni clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); 222b53cdd03SAlexandre Belloni } 223b53cdd03SAlexandre Belloni CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st", 224b53cdd03SAlexandre Belloni atmel_st_timer_init); 225