1 /*
2  * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
3  *
4  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5  * Revision	 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6  * Converted to ClockSource/ClockEvents by David Brownell.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #define pr_fmt(fmt)	"AT91: PIT: " fmt
14 
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/slab.h>
24 
25 #define AT91_PIT_MR		0x00			/* Mode Register */
26 #define AT91_PIT_PITIEN			BIT(25)			/* Timer Interrupt Enable */
27 #define AT91_PIT_PITEN			BIT(24)			/* Timer Enabled */
28 #define AT91_PIT_PIV			GENMASK(19, 0)		/* Periodic Interval Value */
29 
30 #define AT91_PIT_SR		0x04			/* Status Register */
31 #define AT91_PIT_PITS			BIT(0)			/* Timer Status */
32 
33 #define AT91_PIT_PIVR		0x08			/* Periodic Interval Value Register */
34 #define AT91_PIT_PIIR		0x0c			/* Periodic Interval Image Register */
35 #define AT91_PIT_PICNT			GENMASK(31, 20)		/* Interval Counter */
36 #define AT91_PIT_CPIV			GENMASK(19, 0)		/* Inverval Value */
37 
38 #define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
39 #define PIT_PICNT(x)	(((x) & AT91_PIT_PICNT) >> 20)
40 
41 struct pit_data {
42 	struct clock_event_device	clkevt;
43 	struct clocksource		clksrc;
44 
45 	void __iomem	*base;
46 	u32		cycle;
47 	u32		cnt;
48 	unsigned int	irq;
49 	struct clk	*mck;
50 };
51 
52 static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
53 {
54 	return container_of(clksrc, struct pit_data, clksrc);
55 }
56 
57 static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
58 {
59 	return container_of(clkevt, struct pit_data, clkevt);
60 }
61 
62 static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
63 {
64 	return readl_relaxed(base + reg_offset);
65 }
66 
67 static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
68 {
69 	writel_relaxed(value, base + reg_offset);
70 }
71 
72 /*
73  * Clocksource:  just a monotonic counter of MCK/16 cycles.
74  * We don't care whether or not PIT irqs are enabled.
75  */
76 static u64 read_pit_clk(struct clocksource *cs)
77 {
78 	struct pit_data *data = clksrc_to_pit_data(cs);
79 	unsigned long flags;
80 	u32 elapsed;
81 	u32 t;
82 
83 	raw_local_irq_save(flags);
84 	elapsed = data->cnt;
85 	t = pit_read(data->base, AT91_PIT_PIIR);
86 	raw_local_irq_restore(flags);
87 
88 	elapsed += PIT_PICNT(t) * data->cycle;
89 	elapsed += PIT_CPIV(t);
90 	return elapsed;
91 }
92 
93 static int pit_clkevt_shutdown(struct clock_event_device *dev)
94 {
95 	struct pit_data *data = clkevt_to_pit_data(dev);
96 
97 	/* disable irq, leaving the clocksource active */
98 	pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);
99 	return 0;
100 }
101 
102 /*
103  * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
104  */
105 static int pit_clkevt_set_periodic(struct clock_event_device *dev)
106 {
107 	struct pit_data *data = clkevt_to_pit_data(dev);
108 
109 	/* update clocksource counter */
110 	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
111 	pit_write(data->base, AT91_PIT_MR,
112 		  (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
113 	return 0;
114 }
115 
116 static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
117 {
118 	struct pit_data *data = clkevt_to_pit_data(cedev);
119 
120 	/* Disable timer */
121 	pit_write(data->base, AT91_PIT_MR, 0);
122 }
123 
124 static void at91sam926x_pit_reset(struct pit_data *data)
125 {
126 	/* Disable timer and irqs */
127 	pit_write(data->base, AT91_PIT_MR, 0);
128 
129 	/* Clear any pending interrupts, wait for PIT to stop counting */
130 	while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
131 		cpu_relax();
132 
133 	/* Start PIT but don't enable IRQ */
134 	pit_write(data->base, AT91_PIT_MR,
135 		  (data->cycle - 1) | AT91_PIT_PITEN);
136 }
137 
138 static void at91sam926x_pit_resume(struct clock_event_device *cedev)
139 {
140 	struct pit_data *data = clkevt_to_pit_data(cedev);
141 
142 	at91sam926x_pit_reset(data);
143 }
144 
145 /*
146  * IRQ handler for the timer.
147  */
148 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
149 {
150 	struct pit_data *data = dev_id;
151 
152 	/* The PIT interrupt may be disabled, and is shared */
153 	if (clockevent_state_periodic(&data->clkevt) &&
154 	    (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
155 		/* Get number of ticks performed before irq, and ack it */
156 		data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
157 							      AT91_PIT_PIVR));
158 		data->clkevt.event_handler(&data->clkevt);
159 
160 		return IRQ_HANDLED;
161 	}
162 
163 	return IRQ_NONE;
164 }
165 
166 /*
167  * Set up both clocksource and clockevent support.
168  */
169 static int __init at91sam926x_pit_dt_init(struct device_node *node)
170 {
171 	unsigned long   pit_rate;
172 	unsigned        bits;
173 	int             ret;
174 	struct pit_data *data;
175 
176 	data = kzalloc(sizeof(*data), GFP_KERNEL);
177 	if (!data)
178 		return -ENOMEM;
179 
180 	data->base = of_iomap(node, 0);
181 	if (!data->base) {
182 		pr_err("Could not map PIT address\n");
183 		return -ENXIO;
184 	}
185 
186 	data->mck = of_clk_get(node, 0);
187 	if (IS_ERR(data->mck)) {
188 		pr_err("Unable to get mck clk\n");
189 		return PTR_ERR(data->mck);
190 	}
191 
192 	ret = clk_prepare_enable(data->mck);
193 	if (ret) {
194 		pr_err("Unable to enable mck\n");
195 		return ret;
196 	}
197 
198 	/* Get the interrupts property */
199 	data->irq = irq_of_parse_and_map(node, 0);
200 	if (!data->irq) {
201 		pr_err("Unable to get IRQ from DT\n");
202 		return -EINVAL;
203 	}
204 
205 	/*
206 	 * Use our actual MCK to figure out how many MCK/16 ticks per
207 	 * 1/HZ period (instead of a compile-time constant LATCH).
208 	 */
209 	pit_rate = clk_get_rate(data->mck) / 16;
210 	data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
211 	WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
212 
213 	/* Initialize and enable the timer */
214 	at91sam926x_pit_reset(data);
215 
216 	/*
217 	 * Register clocksource.  The high order bits of PIV are unused,
218 	 * so this isn't a 32-bit counter unless we get clockevent irqs.
219 	 */
220 	bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
221 	data->clksrc.mask = CLOCKSOURCE_MASK(bits);
222 	data->clksrc.name = "pit";
223 	data->clksrc.rating = 175;
224 	data->clksrc.read = read_pit_clk;
225 	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
226 
227 	ret = clocksource_register_hz(&data->clksrc, pit_rate);
228 	if (ret) {
229 		pr_err("Failed to register clocksource\n");
230 		return ret;
231 	}
232 
233 	/* Set up irq handler */
234 	ret = request_irq(data->irq, at91sam926x_pit_interrupt,
235 			  IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
236 			  "at91_tick", data);
237 	if (ret) {
238 		pr_err("Unable to setup IRQ\n");
239 		return ret;
240 	}
241 
242 	/* Set up and register clockevents */
243 	data->clkevt.name = "pit";
244 	data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
245 	data->clkevt.shift = 32;
246 	data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
247 	data->clkevt.rating = 100;
248 	data->clkevt.cpumask = cpumask_of(0);
249 
250 	data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
251 	data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
252 	data->clkevt.resume = at91sam926x_pit_resume;
253 	data->clkevt.suspend = at91sam926x_pit_suspend;
254 	clockevents_register_device(&data->clkevt);
255 
256 	return 0;
257 }
258 TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
259 		       at91sam926x_pit_dt_init);
260