1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH Timer Support - TMU 4 * 5 * Copyright (C) 2009 Magnus Damm 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clockchips.h> 10 #include <linux/clocksource.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/irq.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/sh_timer.h> 24 #include <linux/slab.h> 25 #include <linux/spinlock.h> 26 27 enum sh_tmu_model { 28 SH_TMU, 29 SH_TMU_SH3, 30 }; 31 32 struct sh_tmu_device; 33 34 struct sh_tmu_channel { 35 struct sh_tmu_device *tmu; 36 unsigned int index; 37 38 void __iomem *base; 39 int irq; 40 41 unsigned long periodic; 42 struct clock_event_device ced; 43 struct clocksource cs; 44 bool cs_enabled; 45 unsigned int enable_count; 46 }; 47 48 struct sh_tmu_device { 49 struct platform_device *pdev; 50 51 void __iomem *mapbase; 52 struct clk *clk; 53 unsigned long rate; 54 55 enum sh_tmu_model model; 56 57 raw_spinlock_t lock; /* Protect the shared start/stop register */ 58 59 struct sh_tmu_channel *channels; 60 unsigned int num_channels; 61 62 bool has_clockevent; 63 bool has_clocksource; 64 }; 65 66 #define TSTR -1 /* shared register */ 67 #define TCOR 0 /* channel register */ 68 #define TCNT 1 /* channel register */ 69 #define TCR 2 /* channel register */ 70 71 #define TCR_UNF (1 << 8) 72 #define TCR_UNIE (1 << 5) 73 #define TCR_TPSC_CLK4 (0 << 0) 74 #define TCR_TPSC_CLK16 (1 << 0) 75 #define TCR_TPSC_CLK64 (2 << 0) 76 #define TCR_TPSC_CLK256 (3 << 0) 77 #define TCR_TPSC_CLK1024 (4 << 0) 78 #define TCR_TPSC_MASK (7 << 0) 79 80 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) 81 { 82 unsigned long offs; 83 84 if (reg_nr == TSTR) { 85 switch (ch->tmu->model) { 86 case SH_TMU_SH3: 87 return ioread8(ch->tmu->mapbase + 2); 88 case SH_TMU: 89 return ioread8(ch->tmu->mapbase + 4); 90 } 91 } 92 93 offs = reg_nr << 2; 94 95 if (reg_nr == TCR) 96 return ioread16(ch->base + offs); 97 else 98 return ioread32(ch->base + offs); 99 } 100 101 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, 102 unsigned long value) 103 { 104 unsigned long offs; 105 106 if (reg_nr == TSTR) { 107 switch (ch->tmu->model) { 108 case SH_TMU_SH3: 109 return iowrite8(value, ch->tmu->mapbase + 2); 110 case SH_TMU: 111 return iowrite8(value, ch->tmu->mapbase + 4); 112 } 113 } 114 115 offs = reg_nr << 2; 116 117 if (reg_nr == TCR) 118 iowrite16(value, ch->base + offs); 119 else 120 iowrite32(value, ch->base + offs); 121 } 122 123 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) 124 { 125 unsigned long flags, value; 126 127 /* start stop register shared by multiple timer channels */ 128 raw_spin_lock_irqsave(&ch->tmu->lock, flags); 129 value = sh_tmu_read(ch, TSTR); 130 131 if (start) 132 value |= 1 << ch->index; 133 else 134 value &= ~(1 << ch->index); 135 136 sh_tmu_write(ch, TSTR, value); 137 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); 138 } 139 140 static int __sh_tmu_enable(struct sh_tmu_channel *ch) 141 { 142 int ret; 143 144 /* enable clock */ 145 ret = clk_enable(ch->tmu->clk); 146 if (ret) { 147 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", 148 ch->index); 149 return ret; 150 } 151 152 /* make sure channel is disabled */ 153 sh_tmu_start_stop_ch(ch, 0); 154 155 /* maximum timeout */ 156 sh_tmu_write(ch, TCOR, 0xffffffff); 157 sh_tmu_write(ch, TCNT, 0xffffffff); 158 159 /* configure channel to parent clock / 4, irq off */ 160 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); 161 162 /* enable channel */ 163 sh_tmu_start_stop_ch(ch, 1); 164 165 return 0; 166 } 167 168 static int sh_tmu_enable(struct sh_tmu_channel *ch) 169 { 170 if (ch->enable_count++ > 0) 171 return 0; 172 173 pm_runtime_get_sync(&ch->tmu->pdev->dev); 174 dev_pm_syscore_device(&ch->tmu->pdev->dev, true); 175 176 return __sh_tmu_enable(ch); 177 } 178 179 static void __sh_tmu_disable(struct sh_tmu_channel *ch) 180 { 181 /* disable channel */ 182 sh_tmu_start_stop_ch(ch, 0); 183 184 /* disable interrupts in TMU block */ 185 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); 186 187 /* stop clock */ 188 clk_disable(ch->tmu->clk); 189 } 190 191 static void sh_tmu_disable(struct sh_tmu_channel *ch) 192 { 193 if (WARN_ON(ch->enable_count == 0)) 194 return; 195 196 if (--ch->enable_count > 0) 197 return; 198 199 __sh_tmu_disable(ch); 200 201 dev_pm_syscore_device(&ch->tmu->pdev->dev, false); 202 pm_runtime_put(&ch->tmu->pdev->dev); 203 } 204 205 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, 206 int periodic) 207 { 208 /* stop timer */ 209 sh_tmu_start_stop_ch(ch, 0); 210 211 /* acknowledge interrupt */ 212 sh_tmu_read(ch, TCR); 213 214 /* enable interrupt */ 215 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); 216 217 /* reload delta value in case of periodic timer */ 218 if (periodic) 219 sh_tmu_write(ch, TCOR, delta); 220 else 221 sh_tmu_write(ch, TCOR, 0xffffffff); 222 223 sh_tmu_write(ch, TCNT, delta); 224 225 /* start timer */ 226 sh_tmu_start_stop_ch(ch, 1); 227 } 228 229 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) 230 { 231 struct sh_tmu_channel *ch = dev_id; 232 233 /* disable or acknowledge interrupt */ 234 if (clockevent_state_oneshot(&ch->ced)) 235 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); 236 else 237 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); 238 239 /* notify clockevent layer */ 240 ch->ced.event_handler(&ch->ced); 241 return IRQ_HANDLED; 242 } 243 244 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) 245 { 246 return container_of(cs, struct sh_tmu_channel, cs); 247 } 248 249 static u64 sh_tmu_clocksource_read(struct clocksource *cs) 250 { 251 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); 252 253 return sh_tmu_read(ch, TCNT) ^ 0xffffffff; 254 } 255 256 static int sh_tmu_clocksource_enable(struct clocksource *cs) 257 { 258 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); 259 int ret; 260 261 if (WARN_ON(ch->cs_enabled)) 262 return 0; 263 264 ret = sh_tmu_enable(ch); 265 if (!ret) 266 ch->cs_enabled = true; 267 268 return ret; 269 } 270 271 static void sh_tmu_clocksource_disable(struct clocksource *cs) 272 { 273 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); 274 275 if (WARN_ON(!ch->cs_enabled)) 276 return; 277 278 sh_tmu_disable(ch); 279 ch->cs_enabled = false; 280 } 281 282 static void sh_tmu_clocksource_suspend(struct clocksource *cs) 283 { 284 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); 285 286 if (!ch->cs_enabled) 287 return; 288 289 if (--ch->enable_count == 0) { 290 __sh_tmu_disable(ch); 291 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); 292 } 293 } 294 295 static void sh_tmu_clocksource_resume(struct clocksource *cs) 296 { 297 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); 298 299 if (!ch->cs_enabled) 300 return; 301 302 if (ch->enable_count++ == 0) { 303 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); 304 __sh_tmu_enable(ch); 305 } 306 } 307 308 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, 309 const char *name) 310 { 311 struct clocksource *cs = &ch->cs; 312 313 cs->name = name; 314 cs->rating = 200; 315 cs->read = sh_tmu_clocksource_read; 316 cs->enable = sh_tmu_clocksource_enable; 317 cs->disable = sh_tmu_clocksource_disable; 318 cs->suspend = sh_tmu_clocksource_suspend; 319 cs->resume = sh_tmu_clocksource_resume; 320 cs->mask = CLOCKSOURCE_MASK(32); 321 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 322 323 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", 324 ch->index); 325 326 clocksource_register_hz(cs, ch->tmu->rate); 327 return 0; 328 } 329 330 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) 331 { 332 return container_of(ced, struct sh_tmu_channel, ced); 333 } 334 335 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) 336 { 337 sh_tmu_enable(ch); 338 339 if (periodic) { 340 ch->periodic = (ch->tmu->rate + HZ/2) / HZ; 341 sh_tmu_set_next(ch, ch->periodic, 1); 342 } 343 } 344 345 static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced) 346 { 347 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); 348 349 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 350 sh_tmu_disable(ch); 351 return 0; 352 } 353 354 static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, 355 int periodic) 356 { 357 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); 358 359 /* deal with old setting first */ 360 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 361 sh_tmu_disable(ch); 362 363 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", 364 ch->index, periodic ? "periodic" : "oneshot"); 365 sh_tmu_clock_event_start(ch, periodic); 366 return 0; 367 } 368 369 static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced) 370 { 371 return sh_tmu_clock_event_set_state(ced, 0); 372 } 373 374 static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced) 375 { 376 return sh_tmu_clock_event_set_state(ced, 1); 377 } 378 379 static int sh_tmu_clock_event_next(unsigned long delta, 380 struct clock_event_device *ced) 381 { 382 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); 383 384 BUG_ON(!clockevent_state_oneshot(ced)); 385 386 /* program new delta value */ 387 sh_tmu_set_next(ch, delta, 0); 388 return 0; 389 } 390 391 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced) 392 { 393 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); 394 } 395 396 static void sh_tmu_clock_event_resume(struct clock_event_device *ced) 397 { 398 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); 399 } 400 401 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, 402 const char *name) 403 { 404 struct clock_event_device *ced = &ch->ced; 405 int ret; 406 407 ced->name = name; 408 ced->features = CLOCK_EVT_FEAT_PERIODIC; 409 ced->features |= CLOCK_EVT_FEAT_ONESHOT; 410 ced->rating = 200; 411 ced->cpumask = cpu_possible_mask; 412 ced->set_next_event = sh_tmu_clock_event_next; 413 ced->set_state_shutdown = sh_tmu_clock_event_shutdown; 414 ced->set_state_periodic = sh_tmu_clock_event_set_periodic; 415 ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; 416 ced->suspend = sh_tmu_clock_event_suspend; 417 ced->resume = sh_tmu_clock_event_resume; 418 419 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", 420 ch->index); 421 422 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); 423 424 ret = request_irq(ch->irq, sh_tmu_interrupt, 425 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, 426 dev_name(&ch->tmu->pdev->dev), ch); 427 if (ret) { 428 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", 429 ch->index, ch->irq); 430 return; 431 } 432 } 433 434 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, 435 bool clockevent, bool clocksource) 436 { 437 if (clockevent) { 438 ch->tmu->has_clockevent = true; 439 sh_tmu_register_clockevent(ch, name); 440 } else if (clocksource) { 441 ch->tmu->has_clocksource = true; 442 sh_tmu_register_clocksource(ch, name); 443 } 444 445 return 0; 446 } 447 448 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, 449 bool clockevent, bool clocksource, 450 struct sh_tmu_device *tmu) 451 { 452 /* Skip unused channels. */ 453 if (!clockevent && !clocksource) 454 return 0; 455 456 ch->tmu = tmu; 457 ch->index = index; 458 459 if (tmu->model == SH_TMU_SH3) 460 ch->base = tmu->mapbase + 4 + ch->index * 12; 461 else 462 ch->base = tmu->mapbase + 8 + ch->index * 12; 463 464 ch->irq = platform_get_irq(tmu->pdev, index); 465 if (ch->irq < 0) 466 return ch->irq; 467 468 ch->cs_enabled = false; 469 ch->enable_count = 0; 470 471 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), 472 clockevent, clocksource); 473 } 474 475 static int sh_tmu_map_memory(struct sh_tmu_device *tmu) 476 { 477 struct resource *res; 478 479 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); 480 if (!res) { 481 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); 482 return -ENXIO; 483 } 484 485 tmu->mapbase = ioremap_nocache(res->start, resource_size(res)); 486 if (tmu->mapbase == NULL) 487 return -ENXIO; 488 489 return 0; 490 } 491 492 static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) 493 { 494 struct device_node *np = tmu->pdev->dev.of_node; 495 496 tmu->model = SH_TMU; 497 tmu->num_channels = 3; 498 499 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); 500 501 if (tmu->num_channels != 2 && tmu->num_channels != 3) { 502 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", 503 tmu->num_channels); 504 return -EINVAL; 505 } 506 507 return 0; 508 } 509 510 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) 511 { 512 unsigned int i; 513 int ret; 514 515 tmu->pdev = pdev; 516 517 raw_spin_lock_init(&tmu->lock); 518 519 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 520 ret = sh_tmu_parse_dt(tmu); 521 if (ret < 0) 522 return ret; 523 } else if (pdev->dev.platform_data) { 524 const struct platform_device_id *id = pdev->id_entry; 525 struct sh_timer_config *cfg = pdev->dev.platform_data; 526 527 tmu->model = id->driver_data; 528 tmu->num_channels = hweight8(cfg->channels_mask); 529 } else { 530 dev_err(&tmu->pdev->dev, "missing platform data\n"); 531 return -ENXIO; 532 } 533 534 /* Get hold of clock. */ 535 tmu->clk = clk_get(&tmu->pdev->dev, "fck"); 536 if (IS_ERR(tmu->clk)) { 537 dev_err(&tmu->pdev->dev, "cannot get clock\n"); 538 return PTR_ERR(tmu->clk); 539 } 540 541 ret = clk_prepare(tmu->clk); 542 if (ret < 0) 543 goto err_clk_put; 544 545 /* Determine clock rate. */ 546 ret = clk_enable(tmu->clk); 547 if (ret < 0) 548 goto err_clk_unprepare; 549 550 tmu->rate = clk_get_rate(tmu->clk) / 4; 551 clk_disable(tmu->clk); 552 553 /* Map the memory resource. */ 554 ret = sh_tmu_map_memory(tmu); 555 if (ret < 0) { 556 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); 557 goto err_clk_unprepare; 558 } 559 560 /* Allocate and setup the channels. */ 561 tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels), 562 GFP_KERNEL); 563 if (tmu->channels == NULL) { 564 ret = -ENOMEM; 565 goto err_unmap; 566 } 567 568 /* 569 * Use the first channel as a clock event device and the second channel 570 * as a clock source. 571 */ 572 for (i = 0; i < tmu->num_channels; ++i) { 573 ret = sh_tmu_channel_setup(&tmu->channels[i], i, 574 i == 0, i == 1, tmu); 575 if (ret < 0) 576 goto err_unmap; 577 } 578 579 platform_set_drvdata(pdev, tmu); 580 581 return 0; 582 583 err_unmap: 584 kfree(tmu->channels); 585 iounmap(tmu->mapbase); 586 err_clk_unprepare: 587 clk_unprepare(tmu->clk); 588 err_clk_put: 589 clk_put(tmu->clk); 590 return ret; 591 } 592 593 static int sh_tmu_probe(struct platform_device *pdev) 594 { 595 struct sh_tmu_device *tmu = platform_get_drvdata(pdev); 596 int ret; 597 598 if (!is_early_platform_device(pdev)) { 599 pm_runtime_set_active(&pdev->dev); 600 pm_runtime_enable(&pdev->dev); 601 } 602 603 if (tmu) { 604 dev_info(&pdev->dev, "kept as earlytimer\n"); 605 goto out; 606 } 607 608 tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); 609 if (tmu == NULL) 610 return -ENOMEM; 611 612 ret = sh_tmu_setup(tmu, pdev); 613 if (ret) { 614 kfree(tmu); 615 pm_runtime_idle(&pdev->dev); 616 return ret; 617 } 618 if (is_early_platform_device(pdev)) 619 return 0; 620 621 out: 622 if (tmu->has_clockevent || tmu->has_clocksource) 623 pm_runtime_irq_safe(&pdev->dev); 624 else 625 pm_runtime_idle(&pdev->dev); 626 627 return 0; 628 } 629 630 static int sh_tmu_remove(struct platform_device *pdev) 631 { 632 return -EBUSY; /* cannot unregister clockevent and clocksource */ 633 } 634 635 static const struct platform_device_id sh_tmu_id_table[] = { 636 { "sh-tmu", SH_TMU }, 637 { "sh-tmu-sh3", SH_TMU_SH3 }, 638 { } 639 }; 640 MODULE_DEVICE_TABLE(platform, sh_tmu_id_table); 641 642 static const struct of_device_id sh_tmu_of_table[] __maybe_unused = { 643 { .compatible = "renesas,tmu" }, 644 { } 645 }; 646 MODULE_DEVICE_TABLE(of, sh_tmu_of_table); 647 648 static struct platform_driver sh_tmu_device_driver = { 649 .probe = sh_tmu_probe, 650 .remove = sh_tmu_remove, 651 .driver = { 652 .name = "sh_tmu", 653 .of_match_table = of_match_ptr(sh_tmu_of_table), 654 }, 655 .id_table = sh_tmu_id_table, 656 }; 657 658 static int __init sh_tmu_init(void) 659 { 660 return platform_driver_register(&sh_tmu_device_driver); 661 } 662 663 static void __exit sh_tmu_exit(void) 664 { 665 platform_driver_unregister(&sh_tmu_device_driver); 666 } 667 668 early_platform_init("earlytimer", &sh_tmu_device_driver); 669 subsys_initcall(sh_tmu_init); 670 module_exit(sh_tmu_exit); 671 672 MODULE_AUTHOR("Magnus Damm"); 673 MODULE_DESCRIPTION("SuperH TMU Timer Driver"); 674 MODULE_LICENSE("GPL v2"); 675