1 /* 2 * SuperH Timer Support - MTU2 3 * 4 * Copyright (C) 2009 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/delay.h> 26 #include <linux/io.h> 27 #include <linux/clk.h> 28 #include <linux/irq.h> 29 #include <linux/err.h> 30 #include <linux/clockchips.h> 31 #include <linux/sh_timer.h> 32 #include <linux/slab.h> 33 34 struct sh_mtu2_priv { 35 void __iomem *mapbase; 36 struct clk *clk; 37 struct irqaction irqaction; 38 struct platform_device *pdev; 39 unsigned long rate; 40 unsigned long periodic; 41 struct clock_event_device ced; 42 }; 43 44 static DEFINE_SPINLOCK(sh_mtu2_lock); 45 46 #define TSTR -1 /* shared register */ 47 #define TCR 0 /* channel register */ 48 #define TMDR 1 /* channel register */ 49 #define TIOR 2 /* channel register */ 50 #define TIER 3 /* channel register */ 51 #define TSR 4 /* channel register */ 52 #define TCNT 5 /* channel register */ 53 #define TGR 6 /* channel register */ 54 55 static unsigned long mtu2_reg_offs[] = { 56 [TCR] = 0, 57 [TMDR] = 1, 58 [TIOR] = 2, 59 [TIER] = 4, 60 [TSR] = 5, 61 [TCNT] = 6, 62 [TGR] = 8, 63 }; 64 65 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr) 66 { 67 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 68 void __iomem *base = p->mapbase; 69 unsigned long offs; 70 71 if (reg_nr == TSTR) 72 return ioread8(base + cfg->channel_offset); 73 74 offs = mtu2_reg_offs[reg_nr]; 75 76 if ((reg_nr == TCNT) || (reg_nr == TGR)) 77 return ioread16(base + offs); 78 else 79 return ioread8(base + offs); 80 } 81 82 static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr, 83 unsigned long value) 84 { 85 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 86 void __iomem *base = p->mapbase; 87 unsigned long offs; 88 89 if (reg_nr == TSTR) { 90 iowrite8(value, base + cfg->channel_offset); 91 return; 92 } 93 94 offs = mtu2_reg_offs[reg_nr]; 95 96 if ((reg_nr == TCNT) || (reg_nr == TGR)) 97 iowrite16(value, base + offs); 98 else 99 iowrite8(value, base + offs); 100 } 101 102 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start) 103 { 104 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 105 unsigned long flags, value; 106 107 /* start stop register shared by multiple timer channels */ 108 spin_lock_irqsave(&sh_mtu2_lock, flags); 109 value = sh_mtu2_read(p, TSTR); 110 111 if (start) 112 value |= 1 << cfg->timer_bit; 113 else 114 value &= ~(1 << cfg->timer_bit); 115 116 sh_mtu2_write(p, TSTR, value); 117 spin_unlock_irqrestore(&sh_mtu2_lock, flags); 118 } 119 120 static int sh_mtu2_enable(struct sh_mtu2_priv *p) 121 { 122 int ret; 123 124 /* enable clock */ 125 ret = clk_enable(p->clk); 126 if (ret) { 127 dev_err(&p->pdev->dev, "cannot enable clock\n"); 128 return ret; 129 } 130 131 /* make sure channel is disabled */ 132 sh_mtu2_start_stop_ch(p, 0); 133 134 p->rate = clk_get_rate(p->clk) / 64; 135 p->periodic = (p->rate + HZ/2) / HZ; 136 137 /* "Periodic Counter Operation" */ 138 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */ 139 sh_mtu2_write(p, TIOR, 0); 140 sh_mtu2_write(p, TGR, p->periodic); 141 sh_mtu2_write(p, TCNT, 0); 142 sh_mtu2_write(p, TMDR, 0); 143 sh_mtu2_write(p, TIER, 0x01); 144 145 /* enable channel */ 146 sh_mtu2_start_stop_ch(p, 1); 147 148 return 0; 149 } 150 151 static void sh_mtu2_disable(struct sh_mtu2_priv *p) 152 { 153 /* disable channel */ 154 sh_mtu2_start_stop_ch(p, 0); 155 156 /* stop clock */ 157 clk_disable(p->clk); 158 } 159 160 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) 161 { 162 struct sh_mtu2_priv *p = dev_id; 163 164 /* acknowledge interrupt */ 165 sh_mtu2_read(p, TSR); 166 sh_mtu2_write(p, TSR, 0xfe); 167 168 /* notify clockevent layer */ 169 p->ced.event_handler(&p->ced); 170 return IRQ_HANDLED; 171 } 172 173 static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced) 174 { 175 return container_of(ced, struct sh_mtu2_priv, ced); 176 } 177 178 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode, 179 struct clock_event_device *ced) 180 { 181 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced); 182 int disabled = 0; 183 184 /* deal with old setting first */ 185 switch (ced->mode) { 186 case CLOCK_EVT_MODE_PERIODIC: 187 sh_mtu2_disable(p); 188 disabled = 1; 189 break; 190 default: 191 break; 192 } 193 194 switch (mode) { 195 case CLOCK_EVT_MODE_PERIODIC: 196 dev_info(&p->pdev->dev, "used for periodic clock events\n"); 197 sh_mtu2_enable(p); 198 break; 199 case CLOCK_EVT_MODE_UNUSED: 200 if (!disabled) 201 sh_mtu2_disable(p); 202 break; 203 case CLOCK_EVT_MODE_SHUTDOWN: 204 default: 205 break; 206 } 207 } 208 209 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p, 210 char *name, unsigned long rating) 211 { 212 struct clock_event_device *ced = &p->ced; 213 int ret; 214 215 memset(ced, 0, sizeof(*ced)); 216 217 ced->name = name; 218 ced->features = CLOCK_EVT_FEAT_PERIODIC; 219 ced->rating = rating; 220 ced->cpumask = cpumask_of(0); 221 ced->set_mode = sh_mtu2_clock_event_mode; 222 223 dev_info(&p->pdev->dev, "used for clock events\n"); 224 clockevents_register_device(ced); 225 226 ret = setup_irq(p->irqaction.irq, &p->irqaction); 227 if (ret) { 228 dev_err(&p->pdev->dev, "failed to request irq %d\n", 229 p->irqaction.irq); 230 return; 231 } 232 } 233 234 static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name, 235 unsigned long clockevent_rating) 236 { 237 if (clockevent_rating) 238 sh_mtu2_register_clockevent(p, name, clockevent_rating); 239 240 return 0; 241 } 242 243 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev) 244 { 245 struct sh_timer_config *cfg = pdev->dev.platform_data; 246 struct resource *res; 247 int irq, ret; 248 ret = -ENXIO; 249 250 memset(p, 0, sizeof(*p)); 251 p->pdev = pdev; 252 253 if (!cfg) { 254 dev_err(&p->pdev->dev, "missing platform data\n"); 255 goto err0; 256 } 257 258 platform_set_drvdata(pdev, p); 259 260 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); 261 if (!res) { 262 dev_err(&p->pdev->dev, "failed to get I/O memory\n"); 263 goto err0; 264 } 265 266 irq = platform_get_irq(p->pdev, 0); 267 if (irq < 0) { 268 dev_err(&p->pdev->dev, "failed to get irq\n"); 269 goto err0; 270 } 271 272 /* map memory, let mapbase point to our channel */ 273 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 274 if (p->mapbase == NULL) { 275 dev_err(&p->pdev->dev, "failed to remap I/O memory\n"); 276 goto err0; 277 } 278 279 /* setup data for setup_irq() (too early for request_irq()) */ 280 p->irqaction.name = dev_name(&p->pdev->dev); 281 p->irqaction.handler = sh_mtu2_interrupt; 282 p->irqaction.dev_id = p; 283 p->irqaction.irq = irq; 284 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \ 285 IRQF_IRQPOLL | IRQF_NOBALANCING; 286 287 /* get hold of clock */ 288 p->clk = clk_get(&p->pdev->dev, "mtu2_fck"); 289 if (IS_ERR(p->clk)) { 290 dev_err(&p->pdev->dev, "cannot get clock\n"); 291 ret = PTR_ERR(p->clk); 292 goto err1; 293 } 294 295 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev), 296 cfg->clockevent_rating); 297 err1: 298 iounmap(p->mapbase); 299 err0: 300 return ret; 301 } 302 303 static int __devinit sh_mtu2_probe(struct platform_device *pdev) 304 { 305 struct sh_mtu2_priv *p = platform_get_drvdata(pdev); 306 int ret; 307 308 if (p) { 309 dev_info(&pdev->dev, "kept as earlytimer\n"); 310 return 0; 311 } 312 313 p = kmalloc(sizeof(*p), GFP_KERNEL); 314 if (p == NULL) { 315 dev_err(&pdev->dev, "failed to allocate driver data\n"); 316 return -ENOMEM; 317 } 318 319 ret = sh_mtu2_setup(p, pdev); 320 if (ret) { 321 kfree(p); 322 platform_set_drvdata(pdev, NULL); 323 } 324 return ret; 325 } 326 327 static int __devexit sh_mtu2_remove(struct platform_device *pdev) 328 { 329 return -EBUSY; /* cannot unregister clockevent */ 330 } 331 332 static struct platform_driver sh_mtu2_device_driver = { 333 .probe = sh_mtu2_probe, 334 .remove = __devexit_p(sh_mtu2_remove), 335 .driver = { 336 .name = "sh_mtu2", 337 } 338 }; 339 340 static int __init sh_mtu2_init(void) 341 { 342 return platform_driver_register(&sh_mtu2_device_driver); 343 } 344 345 static void __exit sh_mtu2_exit(void) 346 { 347 platform_driver_unregister(&sh_mtu2_device_driver); 348 } 349 350 early_platform_init("earlytimer", &sh_mtu2_device_driver); 351 module_init(sh_mtu2_init); 352 module_exit(sh_mtu2_exit); 353 354 MODULE_AUTHOR("Magnus Damm"); 355 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); 356 MODULE_LICENSE("GPL v2"); 357