1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH Timer Support - CMT 4 * 5 * Copyright (C) 2008 Magnus Damm 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clockchips.h> 10 #include <linux/clocksource.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/ioport.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sh_timer.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 28 #ifdef CONFIG_SUPERH 29 #include <asm/platform_early.h> 30 #endif 31 32 struct sh_cmt_device; 33 34 /* 35 * The CMT comes in 5 different identified flavours, depending not only on the 36 * SoC but also on the particular instance. The following table lists the main 37 * characteristics of those flavours. 38 * 39 * 16B 32B 32B-F 48B R-Car Gen2 40 * ----------------------------------------------------------------------------- 41 * Channels 2 1/4 1 6 2/8 42 * Control Width 16 16 16 16 32 43 * Counter Width 16 32 32 32/48 32/48 44 * Shared Start/Stop Y Y Y Y N 45 * 46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register 47 * located in the channel registers block. All other versions have a shared 48 * start/stop register located in the global space. 49 * 50 * Channels are indexed from 0 to N-1 in the documentation. The channel index 51 * infers the start/stop bit position in the control register and the channel 52 * registers block address. Some CMT instances have a subset of channels 53 * available, in which case the index in the documentation doesn't match the 54 * "real" index as implemented in hardware. This is for instance the case with 55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 56 * in the documentation but using start/stop bit 5 and having its registers 57 * block at 0x60. 58 * 59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit 60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. 61 */ 62 63 enum sh_cmt_model { 64 SH_CMT_16BIT, 65 SH_CMT_32BIT, 66 SH_CMT_48BIT, 67 SH_CMT0_RCAR_GEN2, 68 SH_CMT1_RCAR_GEN2, 69 }; 70 71 struct sh_cmt_info { 72 enum sh_cmt_model model; 73 74 unsigned int channels_mask; 75 76 unsigned long width; /* 16 or 32 bit version of hardware block */ 77 u32 overflow_bit; 78 u32 clear_bits; 79 80 /* callbacks for CMSTR and CMCSR access */ 81 u32 (*read_control)(void __iomem *base, unsigned long offs); 82 void (*write_control)(void __iomem *base, unsigned long offs, 83 u32 value); 84 85 /* callbacks for CMCNT and CMCOR access */ 86 u32 (*read_count)(void __iomem *base, unsigned long offs); 87 void (*write_count)(void __iomem *base, unsigned long offs, u32 value); 88 }; 89 90 struct sh_cmt_channel { 91 struct sh_cmt_device *cmt; 92 93 unsigned int index; /* Index in the documentation */ 94 unsigned int hwidx; /* Real hardware index */ 95 96 void __iomem *iostart; 97 void __iomem *ioctrl; 98 99 unsigned int timer_bit; 100 unsigned long flags; 101 u32 match_value; 102 u32 next_match_value; 103 u32 max_match_value; 104 raw_spinlock_t lock; 105 struct clock_event_device ced; 106 struct clocksource cs; 107 u64 total_cycles; 108 bool cs_enabled; 109 }; 110 111 struct sh_cmt_device { 112 struct platform_device *pdev; 113 114 const struct sh_cmt_info *info; 115 116 void __iomem *mapbase; 117 struct clk *clk; 118 unsigned long rate; 119 unsigned int reg_delay; 120 121 raw_spinlock_t lock; /* Protect the shared start/stop register */ 122 123 struct sh_cmt_channel *channels; 124 unsigned int num_channels; 125 unsigned int hw_channels; 126 127 bool has_clockevent; 128 bool has_clocksource; 129 }; 130 131 #define SH_CMT16_CMCSR_CMF (1 << 7) 132 #define SH_CMT16_CMCSR_CMIE (1 << 6) 133 #define SH_CMT16_CMCSR_CKS8 (0 << 0) 134 #define SH_CMT16_CMCSR_CKS32 (1 << 0) 135 #define SH_CMT16_CMCSR_CKS128 (2 << 0) 136 #define SH_CMT16_CMCSR_CKS512 (3 << 0) 137 #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) 138 139 #define SH_CMT32_CMCSR_CMF (1 << 15) 140 #define SH_CMT32_CMCSR_OVF (1 << 14) 141 #define SH_CMT32_CMCSR_WRFLG (1 << 13) 142 #define SH_CMT32_CMCSR_STTF (1 << 12) 143 #define SH_CMT32_CMCSR_STPF (1 << 11) 144 #define SH_CMT32_CMCSR_SSIE (1 << 10) 145 #define SH_CMT32_CMCSR_CMS (1 << 9) 146 #define SH_CMT32_CMCSR_CMM (1 << 8) 147 #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) 148 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) 149 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) 150 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) 151 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) 152 #define SH_CMT32_CMCSR_DBGIVD (1 << 3) 153 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) 154 #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) 155 #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) 156 #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) 157 #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) 158 159 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) 160 { 161 return ioread16(base + (offs << 1)); 162 } 163 164 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) 165 { 166 return ioread32(base + (offs << 2)); 167 } 168 169 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) 170 { 171 iowrite16(value, base + (offs << 1)); 172 } 173 174 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) 175 { 176 iowrite32(value, base + (offs << 2)); 177 } 178 179 static const struct sh_cmt_info sh_cmt_info[] = { 180 [SH_CMT_16BIT] = { 181 .model = SH_CMT_16BIT, 182 .width = 16, 183 .overflow_bit = SH_CMT16_CMCSR_CMF, 184 .clear_bits = ~SH_CMT16_CMCSR_CMF, 185 .read_control = sh_cmt_read16, 186 .write_control = sh_cmt_write16, 187 .read_count = sh_cmt_read16, 188 .write_count = sh_cmt_write16, 189 }, 190 [SH_CMT_32BIT] = { 191 .model = SH_CMT_32BIT, 192 .width = 32, 193 .overflow_bit = SH_CMT32_CMCSR_CMF, 194 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 195 .read_control = sh_cmt_read16, 196 .write_control = sh_cmt_write16, 197 .read_count = sh_cmt_read32, 198 .write_count = sh_cmt_write32, 199 }, 200 [SH_CMT_48BIT] = { 201 .model = SH_CMT_48BIT, 202 .channels_mask = 0x3f, 203 .width = 32, 204 .overflow_bit = SH_CMT32_CMCSR_CMF, 205 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 206 .read_control = sh_cmt_read32, 207 .write_control = sh_cmt_write32, 208 .read_count = sh_cmt_read32, 209 .write_count = sh_cmt_write32, 210 }, 211 [SH_CMT0_RCAR_GEN2] = { 212 .model = SH_CMT0_RCAR_GEN2, 213 .channels_mask = 0x60, 214 .width = 32, 215 .overflow_bit = SH_CMT32_CMCSR_CMF, 216 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 217 .read_control = sh_cmt_read32, 218 .write_control = sh_cmt_write32, 219 .read_count = sh_cmt_read32, 220 .write_count = sh_cmt_write32, 221 }, 222 [SH_CMT1_RCAR_GEN2] = { 223 .model = SH_CMT1_RCAR_GEN2, 224 .channels_mask = 0xff, 225 .width = 32, 226 .overflow_bit = SH_CMT32_CMCSR_CMF, 227 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 228 .read_control = sh_cmt_read32, 229 .write_control = sh_cmt_write32, 230 .read_count = sh_cmt_read32, 231 .write_count = sh_cmt_write32, 232 }, 233 }; 234 235 #define CMCSR 0 /* channel register */ 236 #define CMCNT 1 /* channel register */ 237 #define CMCOR 2 /* channel register */ 238 239 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */ 240 241 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) 242 { 243 if (ch->iostart) 244 return ch->cmt->info->read_control(ch->iostart, 0); 245 else 246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); 247 } 248 249 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) 250 { 251 u32 old_value = sh_cmt_read_cmstr(ch); 252 253 if (value != old_value) { 254 if (ch->iostart) { 255 ch->cmt->info->write_control(ch->iostart, 0, value); 256 udelay(ch->cmt->reg_delay); 257 } else { 258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); 259 udelay(ch->cmt->reg_delay); 260 } 261 } 262 } 263 264 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) 265 { 266 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); 267 } 268 269 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) 270 { 271 u32 old_value = sh_cmt_read_cmcsr(ch); 272 273 if (value != old_value) { 274 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); 275 udelay(ch->cmt->reg_delay); 276 } 277 } 278 279 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) 280 { 281 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); 282 } 283 284 static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) 285 { 286 /* Tests showed that we need to wait 3 clocks here */ 287 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); 288 u32 reg; 289 290 if (ch->cmt->info->model > SH_CMT_16BIT) { 291 int ret = read_poll_timeout_atomic(sh_cmt_read_cmcsr, reg, 292 !(reg & SH_CMT32_CMCSR_WRFLG), 293 1, cmcnt_delay, false, ch); 294 if (ret < 0) 295 return ret; 296 } 297 298 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); 299 udelay(cmcnt_delay); 300 return 0; 301 } 302 303 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) 304 { 305 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); 306 307 if (value != old_value) { 308 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); 309 udelay(ch->cmt->reg_delay); 310 } 311 } 312 313 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) 314 { 315 u32 v1, v2, v3; 316 u32 o1, o2; 317 318 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; 319 320 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 321 do { 322 o2 = o1; 323 v1 = sh_cmt_read_cmcnt(ch); 324 v2 = sh_cmt_read_cmcnt(ch); 325 v3 = sh_cmt_read_cmcnt(ch); 326 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; 327 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) 328 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); 329 330 *has_wrapped = o1; 331 return v2; 332 } 333 334 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) 335 { 336 unsigned long flags; 337 u32 value; 338 339 /* start stop register shared by multiple timer channels */ 340 raw_spin_lock_irqsave(&ch->cmt->lock, flags); 341 value = sh_cmt_read_cmstr(ch); 342 343 if (start) 344 value |= 1 << ch->timer_bit; 345 else 346 value &= ~(1 << ch->timer_bit); 347 348 sh_cmt_write_cmstr(ch, value); 349 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); 350 } 351 352 static int sh_cmt_enable(struct sh_cmt_channel *ch) 353 { 354 int ret; 355 356 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); 357 358 /* enable clock */ 359 ret = clk_enable(ch->cmt->clk); 360 if (ret) { 361 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", 362 ch->index); 363 goto err0; 364 } 365 366 /* make sure channel is disabled */ 367 sh_cmt_start_stop_ch(ch, 0); 368 369 /* configure channel, periodic mode and maximum timeout */ 370 if (ch->cmt->info->width == 16) { 371 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | 372 SH_CMT16_CMCSR_CKS512); 373 } else { 374 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? 375 SH_CMT32_CMCSR_CMTOUT_IE : 0; 376 sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM | 377 SH_CMT32_CMCSR_CMR_IRQ | 378 SH_CMT32_CMCSR_CKS_RCLK8); 379 } 380 381 sh_cmt_write_cmcor(ch, 0xffffffff); 382 ret = sh_cmt_write_cmcnt(ch, 0); 383 384 if (ret || sh_cmt_read_cmcnt(ch)) { 385 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", 386 ch->index); 387 ret = -ETIMEDOUT; 388 goto err1; 389 } 390 391 /* enable channel */ 392 sh_cmt_start_stop_ch(ch, 1); 393 return 0; 394 err1: 395 /* stop clock */ 396 clk_disable(ch->cmt->clk); 397 398 err0: 399 return ret; 400 } 401 402 static void sh_cmt_disable(struct sh_cmt_channel *ch) 403 { 404 /* disable channel */ 405 sh_cmt_start_stop_ch(ch, 0); 406 407 /* disable interrupts in CMT block */ 408 sh_cmt_write_cmcsr(ch, 0); 409 410 /* stop clock */ 411 clk_disable(ch->cmt->clk); 412 413 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); 414 } 415 416 /* private flags */ 417 #define FLAG_CLOCKEVENT (1 << 0) 418 #define FLAG_CLOCKSOURCE (1 << 1) 419 #define FLAG_REPROGRAM (1 << 2) 420 #define FLAG_SKIPEVENT (1 << 3) 421 #define FLAG_IRQCONTEXT (1 << 4) 422 423 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, 424 int absolute) 425 { 426 u32 value = ch->next_match_value; 427 u32 new_match; 428 u32 delay = 0; 429 u32 now = 0; 430 u32 has_wrapped; 431 432 now = sh_cmt_get_counter(ch, &has_wrapped); 433 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ 434 435 if (has_wrapped) { 436 /* we're competing with the interrupt handler. 437 * -> let the interrupt handler reprogram the timer. 438 * -> interrupt number two handles the event. 439 */ 440 ch->flags |= FLAG_SKIPEVENT; 441 return; 442 } 443 444 if (absolute) 445 now = 0; 446 447 do { 448 /* reprogram the timer hardware, 449 * but don't save the new match value yet. 450 */ 451 new_match = now + value + delay; 452 if (new_match > ch->max_match_value) 453 new_match = ch->max_match_value; 454 455 sh_cmt_write_cmcor(ch, new_match); 456 457 now = sh_cmt_get_counter(ch, &has_wrapped); 458 if (has_wrapped && (new_match > ch->match_value)) { 459 /* we are changing to a greater match value, 460 * so this wrap must be caused by the counter 461 * matching the old value. 462 * -> first interrupt reprograms the timer. 463 * -> interrupt number two handles the event. 464 */ 465 ch->flags |= FLAG_SKIPEVENT; 466 break; 467 } 468 469 if (has_wrapped) { 470 /* we are changing to a smaller match value, 471 * so the wrap must be caused by the counter 472 * matching the new value. 473 * -> save programmed match value. 474 * -> let isr handle the event. 475 */ 476 ch->match_value = new_match; 477 break; 478 } 479 480 /* be safe: verify hardware settings */ 481 if (now < new_match) { 482 /* timer value is below match value, all good. 483 * this makes sure we won't miss any match events. 484 * -> save programmed match value. 485 * -> let isr handle the event. 486 */ 487 ch->match_value = new_match; 488 break; 489 } 490 491 /* the counter has reached a value greater 492 * than our new match value. and since the 493 * has_wrapped flag isn't set we must have 494 * programmed a too close event. 495 * -> increase delay and retry. 496 */ 497 if (delay) 498 delay <<= 1; 499 else 500 delay = 1; 501 502 if (!delay) 503 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", 504 ch->index); 505 506 } while (delay); 507 } 508 509 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) 510 { 511 if (delta > ch->max_match_value) 512 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", 513 ch->index); 514 515 ch->next_match_value = delta; 516 sh_cmt_clock_event_program_verify(ch, 0); 517 } 518 519 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) 520 { 521 unsigned long flags; 522 523 raw_spin_lock_irqsave(&ch->lock, flags); 524 __sh_cmt_set_next(ch, delta); 525 raw_spin_unlock_irqrestore(&ch->lock, flags); 526 } 527 528 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) 529 { 530 struct sh_cmt_channel *ch = dev_id; 531 unsigned long flags; 532 533 /* clear flags */ 534 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & 535 ch->cmt->info->clear_bits); 536 537 /* update clock source counter to begin with if enabled 538 * the wrap flag should be cleared by the timer specific 539 * isr before we end up here. 540 */ 541 if (ch->flags & FLAG_CLOCKSOURCE) 542 ch->total_cycles += ch->match_value + 1; 543 544 if (!(ch->flags & FLAG_REPROGRAM)) 545 ch->next_match_value = ch->max_match_value; 546 547 ch->flags |= FLAG_IRQCONTEXT; 548 549 if (ch->flags & FLAG_CLOCKEVENT) { 550 if (!(ch->flags & FLAG_SKIPEVENT)) { 551 if (clockevent_state_oneshot(&ch->ced)) { 552 ch->next_match_value = ch->max_match_value; 553 ch->flags |= FLAG_REPROGRAM; 554 } 555 556 ch->ced.event_handler(&ch->ced); 557 } 558 } 559 560 ch->flags &= ~FLAG_SKIPEVENT; 561 562 raw_spin_lock_irqsave(&ch->lock, flags); 563 564 if (ch->flags & FLAG_REPROGRAM) { 565 ch->flags &= ~FLAG_REPROGRAM; 566 sh_cmt_clock_event_program_verify(ch, 1); 567 568 if (ch->flags & FLAG_CLOCKEVENT) 569 if ((clockevent_state_shutdown(&ch->ced)) 570 || (ch->match_value == ch->next_match_value)) 571 ch->flags &= ~FLAG_REPROGRAM; 572 } 573 574 ch->flags &= ~FLAG_IRQCONTEXT; 575 576 raw_spin_unlock_irqrestore(&ch->lock, flags); 577 578 return IRQ_HANDLED; 579 } 580 581 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) 582 { 583 int ret = 0; 584 unsigned long flags; 585 586 if (flag & FLAG_CLOCKSOURCE) 587 pm_runtime_get_sync(&ch->cmt->pdev->dev); 588 589 raw_spin_lock_irqsave(&ch->lock, flags); 590 591 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 592 if (flag & FLAG_CLOCKEVENT) 593 pm_runtime_get_sync(&ch->cmt->pdev->dev); 594 ret = sh_cmt_enable(ch); 595 } 596 597 if (ret) 598 goto out; 599 ch->flags |= flag; 600 601 /* setup timeout if no clockevent */ 602 if (ch->cmt->num_channels == 1 && 603 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) 604 __sh_cmt_set_next(ch, ch->max_match_value); 605 out: 606 raw_spin_unlock_irqrestore(&ch->lock, flags); 607 608 return ret; 609 } 610 611 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) 612 { 613 unsigned long flags; 614 unsigned long f; 615 616 raw_spin_lock_irqsave(&ch->lock, flags); 617 618 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 619 ch->flags &= ~flag; 620 621 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 622 sh_cmt_disable(ch); 623 if (flag & FLAG_CLOCKEVENT) 624 pm_runtime_put(&ch->cmt->pdev->dev); 625 } 626 627 /* adjust the timeout to maximum if only clocksource left */ 628 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) 629 __sh_cmt_set_next(ch, ch->max_match_value); 630 631 raw_spin_unlock_irqrestore(&ch->lock, flags); 632 633 if (flag & FLAG_CLOCKSOURCE) 634 pm_runtime_put(&ch->cmt->pdev->dev); 635 } 636 637 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) 638 { 639 return container_of(cs, struct sh_cmt_channel, cs); 640 } 641 642 static u64 sh_cmt_clocksource_read(struct clocksource *cs) 643 { 644 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 645 u32 has_wrapped; 646 647 if (ch->cmt->num_channels == 1) { 648 unsigned long flags; 649 u64 value; 650 u32 raw; 651 652 raw_spin_lock_irqsave(&ch->lock, flags); 653 value = ch->total_cycles; 654 raw = sh_cmt_get_counter(ch, &has_wrapped); 655 656 if (unlikely(has_wrapped)) 657 raw += ch->match_value + 1; 658 raw_spin_unlock_irqrestore(&ch->lock, flags); 659 660 return value + raw; 661 } 662 663 return sh_cmt_get_counter(ch, &has_wrapped); 664 } 665 666 static int sh_cmt_clocksource_enable(struct clocksource *cs) 667 { 668 int ret; 669 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 670 671 WARN_ON(ch->cs_enabled); 672 673 ch->total_cycles = 0; 674 675 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); 676 if (!ret) 677 ch->cs_enabled = true; 678 679 return ret; 680 } 681 682 static void sh_cmt_clocksource_disable(struct clocksource *cs) 683 { 684 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 685 686 WARN_ON(!ch->cs_enabled); 687 688 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 689 ch->cs_enabled = false; 690 } 691 692 static void sh_cmt_clocksource_suspend(struct clocksource *cs) 693 { 694 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 695 696 if (!ch->cs_enabled) 697 return; 698 699 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 700 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); 701 } 702 703 static void sh_cmt_clocksource_resume(struct clocksource *cs) 704 { 705 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 706 707 if (!ch->cs_enabled) 708 return; 709 710 dev_pm_genpd_resume(&ch->cmt->pdev->dev); 711 sh_cmt_start(ch, FLAG_CLOCKSOURCE); 712 } 713 714 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, 715 const char *name) 716 { 717 struct clocksource *cs = &ch->cs; 718 719 cs->name = name; 720 cs->rating = 125; 721 cs->read = sh_cmt_clocksource_read; 722 cs->enable = sh_cmt_clocksource_enable; 723 cs->disable = sh_cmt_clocksource_disable; 724 cs->suspend = sh_cmt_clocksource_suspend; 725 cs->resume = sh_cmt_clocksource_resume; 726 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); 727 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 728 729 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", 730 ch->index); 731 732 clocksource_register_hz(cs, ch->cmt->rate); 733 return 0; 734 } 735 736 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) 737 { 738 return container_of(ced, struct sh_cmt_channel, ced); 739 } 740 741 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) 742 { 743 sh_cmt_start(ch, FLAG_CLOCKEVENT); 744 745 if (periodic) 746 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); 747 else 748 sh_cmt_set_next(ch, ch->max_match_value); 749 } 750 751 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) 752 { 753 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 754 755 sh_cmt_stop(ch, FLAG_CLOCKEVENT); 756 return 0; 757 } 758 759 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, 760 int periodic) 761 { 762 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 763 764 /* deal with old setting first */ 765 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 766 sh_cmt_stop(ch, FLAG_CLOCKEVENT); 767 768 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", 769 ch->index, periodic ? "periodic" : "oneshot"); 770 sh_cmt_clock_event_start(ch, periodic); 771 return 0; 772 } 773 774 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) 775 { 776 return sh_cmt_clock_event_set_state(ced, 0); 777 } 778 779 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) 780 { 781 return sh_cmt_clock_event_set_state(ced, 1); 782 } 783 784 static int sh_cmt_clock_event_next(unsigned long delta, 785 struct clock_event_device *ced) 786 { 787 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 788 unsigned long flags; 789 790 BUG_ON(!clockevent_state_oneshot(ced)); 791 792 raw_spin_lock_irqsave(&ch->lock, flags); 793 794 if (likely(ch->flags & FLAG_IRQCONTEXT)) 795 ch->next_match_value = delta - 1; 796 else 797 __sh_cmt_set_next(ch, delta - 1); 798 799 raw_spin_unlock_irqrestore(&ch->lock, flags); 800 801 return 0; 802 } 803 804 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) 805 { 806 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 807 808 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); 809 clk_unprepare(ch->cmt->clk); 810 } 811 812 static void sh_cmt_clock_event_resume(struct clock_event_device *ced) 813 { 814 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 815 816 clk_prepare(ch->cmt->clk); 817 dev_pm_genpd_resume(&ch->cmt->pdev->dev); 818 } 819 820 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, 821 const char *name) 822 { 823 struct clock_event_device *ced = &ch->ced; 824 int irq; 825 int ret; 826 827 irq = platform_get_irq(ch->cmt->pdev, ch->index); 828 if (irq < 0) 829 return irq; 830 831 ret = request_irq(irq, sh_cmt_interrupt, 832 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, 833 dev_name(&ch->cmt->pdev->dev), ch); 834 if (ret) { 835 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", 836 ch->index, irq); 837 return ret; 838 } 839 840 ced->name = name; 841 ced->features = CLOCK_EVT_FEAT_PERIODIC; 842 ced->features |= CLOCK_EVT_FEAT_ONESHOT; 843 ced->rating = 125; 844 ced->cpumask = cpu_possible_mask; 845 ced->set_next_event = sh_cmt_clock_event_next; 846 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; 847 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; 848 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; 849 ced->suspend = sh_cmt_clock_event_suspend; 850 ced->resume = sh_cmt_clock_event_resume; 851 852 /* TODO: calculate good shift from rate and counter bit width */ 853 ced->shift = 32; 854 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); 855 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); 856 ced->max_delta_ticks = ch->max_match_value; 857 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); 858 ced->min_delta_ticks = 0x1f; 859 860 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", 861 ch->index); 862 clockevents_register_device(ced); 863 864 return 0; 865 } 866 867 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, 868 bool clockevent, bool clocksource) 869 { 870 int ret; 871 872 if (clockevent) { 873 ch->cmt->has_clockevent = true; 874 ret = sh_cmt_register_clockevent(ch, name); 875 if (ret < 0) 876 return ret; 877 } 878 879 if (clocksource) { 880 ch->cmt->has_clocksource = true; 881 sh_cmt_register_clocksource(ch, name); 882 } 883 884 return 0; 885 } 886 887 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, 888 unsigned int hwidx, bool clockevent, 889 bool clocksource, struct sh_cmt_device *cmt) 890 { 891 u32 value; 892 int ret; 893 894 /* Skip unused channels. */ 895 if (!clockevent && !clocksource) 896 return 0; 897 898 ch->cmt = cmt; 899 ch->index = index; 900 ch->hwidx = hwidx; 901 ch->timer_bit = hwidx; 902 903 /* 904 * Compute the address of the channel control register block. For the 905 * timers with a per-channel start/stop register, compute its address 906 * as well. 907 */ 908 switch (cmt->info->model) { 909 case SH_CMT_16BIT: 910 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; 911 break; 912 case SH_CMT_32BIT: 913 case SH_CMT_48BIT: 914 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; 915 break; 916 case SH_CMT0_RCAR_GEN2: 917 case SH_CMT1_RCAR_GEN2: 918 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; 919 ch->ioctrl = ch->iostart + 0x10; 920 ch->timer_bit = 0; 921 922 /* Enable the clock supply to the channel */ 923 value = ioread32(cmt->mapbase + CMCLKE); 924 value |= BIT(hwidx); 925 iowrite32(value, cmt->mapbase + CMCLKE); 926 break; 927 } 928 929 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) 930 ch->max_match_value = ~0; 931 else 932 ch->max_match_value = (1 << cmt->info->width) - 1; 933 934 ch->match_value = ch->max_match_value; 935 raw_spin_lock_init(&ch->lock); 936 937 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), 938 clockevent, clocksource); 939 if (ret) { 940 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", 941 ch->index); 942 return ret; 943 } 944 ch->cs_enabled = false; 945 946 return 0; 947 } 948 949 static int sh_cmt_map_memory(struct sh_cmt_device *cmt) 950 { 951 struct resource *mem; 952 953 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); 954 if (!mem) { 955 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); 956 return -ENXIO; 957 } 958 959 cmt->mapbase = ioremap(mem->start, resource_size(mem)); 960 if (cmt->mapbase == NULL) { 961 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); 962 return -ENXIO; 963 } 964 965 return 0; 966 } 967 968 static const struct platform_device_id sh_cmt_id_table[] = { 969 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, 970 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, 971 { } 972 }; 973 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); 974 975 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { 976 { 977 /* deprecated, preserved for backward compatibility */ 978 .compatible = "renesas,cmt-48", 979 .data = &sh_cmt_info[SH_CMT_48BIT] 980 }, 981 { 982 /* deprecated, preserved for backward compatibility */ 983 .compatible = "renesas,cmt-48-gen2", 984 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 985 }, 986 { 987 .compatible = "renesas,r8a7740-cmt1", 988 .data = &sh_cmt_info[SH_CMT_48BIT] 989 }, 990 { 991 .compatible = "renesas,sh73a0-cmt1", 992 .data = &sh_cmt_info[SH_CMT_48BIT] 993 }, 994 { 995 .compatible = "renesas,rcar-gen2-cmt0", 996 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 997 }, 998 { 999 .compatible = "renesas,rcar-gen2-cmt1", 1000 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] 1001 }, 1002 { 1003 .compatible = "renesas,rcar-gen3-cmt0", 1004 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 1005 }, 1006 { 1007 .compatible = "renesas,rcar-gen3-cmt1", 1008 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] 1009 }, 1010 { 1011 .compatible = "renesas,rcar-gen4-cmt0", 1012 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 1013 }, 1014 { 1015 .compatible = "renesas,rcar-gen4-cmt1", 1016 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] 1017 }, 1018 { } 1019 }; 1020 MODULE_DEVICE_TABLE(of, sh_cmt_of_table); 1021 1022 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) 1023 { 1024 unsigned int mask, i; 1025 unsigned long rate; 1026 int ret; 1027 1028 cmt->pdev = pdev; 1029 raw_spin_lock_init(&cmt->lock); 1030 1031 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 1032 cmt->info = of_device_get_match_data(&pdev->dev); 1033 cmt->hw_channels = cmt->info->channels_mask; 1034 } else if (pdev->dev.platform_data) { 1035 struct sh_timer_config *cfg = pdev->dev.platform_data; 1036 const struct platform_device_id *id = pdev->id_entry; 1037 1038 cmt->info = (const struct sh_cmt_info *)id->driver_data; 1039 cmt->hw_channels = cfg->channels_mask; 1040 } else { 1041 dev_err(&cmt->pdev->dev, "missing platform data\n"); 1042 return -ENXIO; 1043 } 1044 1045 /* Get hold of clock. */ 1046 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); 1047 if (IS_ERR(cmt->clk)) { 1048 dev_err(&cmt->pdev->dev, "cannot get clock\n"); 1049 return PTR_ERR(cmt->clk); 1050 } 1051 1052 ret = clk_prepare(cmt->clk); 1053 if (ret < 0) 1054 goto err_clk_put; 1055 1056 /* Determine clock rate. */ 1057 ret = clk_enable(cmt->clk); 1058 if (ret < 0) 1059 goto err_clk_unprepare; 1060 1061 rate = clk_get_rate(cmt->clk); 1062 if (!rate) { 1063 ret = -EINVAL; 1064 goto err_clk_disable; 1065 } 1066 1067 /* We shall wait 2 input clks after register writes */ 1068 if (cmt->info->model >= SH_CMT_48BIT) 1069 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate); 1070 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8); 1071 1072 /* Map the memory resource(s). */ 1073 ret = sh_cmt_map_memory(cmt); 1074 if (ret < 0) 1075 goto err_clk_disable; 1076 1077 /* Allocate and setup the channels. */ 1078 cmt->num_channels = hweight8(cmt->hw_channels); 1079 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), 1080 GFP_KERNEL); 1081 if (cmt->channels == NULL) { 1082 ret = -ENOMEM; 1083 goto err_unmap; 1084 } 1085 1086 /* 1087 * Use the first channel as a clock event device and the second channel 1088 * as a clock source. If only one channel is available use it for both. 1089 */ 1090 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { 1091 unsigned int hwidx = ffs(mask) - 1; 1092 bool clocksource = i == 1 || cmt->num_channels == 1; 1093 bool clockevent = i == 0; 1094 1095 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, 1096 clockevent, clocksource, cmt); 1097 if (ret < 0) 1098 goto err_unmap; 1099 1100 mask &= ~(1 << hwidx); 1101 } 1102 1103 clk_disable(cmt->clk); 1104 1105 platform_set_drvdata(pdev, cmt); 1106 1107 return 0; 1108 1109 err_unmap: 1110 kfree(cmt->channels); 1111 iounmap(cmt->mapbase); 1112 err_clk_disable: 1113 clk_disable(cmt->clk); 1114 err_clk_unprepare: 1115 clk_unprepare(cmt->clk); 1116 err_clk_put: 1117 clk_put(cmt->clk); 1118 return ret; 1119 } 1120 1121 static int sh_cmt_probe(struct platform_device *pdev) 1122 { 1123 struct sh_cmt_device *cmt = platform_get_drvdata(pdev); 1124 int ret; 1125 1126 if (!is_sh_early_platform_device(pdev)) { 1127 pm_runtime_set_active(&pdev->dev); 1128 pm_runtime_enable(&pdev->dev); 1129 } 1130 1131 if (cmt) { 1132 dev_info(&pdev->dev, "kept as earlytimer\n"); 1133 goto out; 1134 } 1135 1136 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); 1137 if (cmt == NULL) 1138 return -ENOMEM; 1139 1140 ret = sh_cmt_setup(cmt, pdev); 1141 if (ret) { 1142 kfree(cmt); 1143 pm_runtime_idle(&pdev->dev); 1144 return ret; 1145 } 1146 if (is_sh_early_platform_device(pdev)) 1147 return 0; 1148 1149 out: 1150 if (cmt->has_clockevent || cmt->has_clocksource) 1151 pm_runtime_irq_safe(&pdev->dev); 1152 else 1153 pm_runtime_idle(&pdev->dev); 1154 1155 return 0; 1156 } 1157 1158 static struct platform_driver sh_cmt_device_driver = { 1159 .probe = sh_cmt_probe, 1160 .driver = { 1161 .name = "sh_cmt", 1162 .of_match_table = of_match_ptr(sh_cmt_of_table), 1163 .suppress_bind_attrs = true, 1164 }, 1165 .id_table = sh_cmt_id_table, 1166 }; 1167 1168 static int __init sh_cmt_init(void) 1169 { 1170 return platform_driver_register(&sh_cmt_device_driver); 1171 } 1172 1173 static void __exit sh_cmt_exit(void) 1174 { 1175 platform_driver_unregister(&sh_cmt_device_driver); 1176 } 1177 1178 #ifdef CONFIG_SUPERH 1179 sh_early_platform_init("earlytimer", &sh_cmt_device_driver); 1180 #endif 1181 1182 subsys_initcall(sh_cmt_init); 1183 module_exit(sh_cmt_exit); 1184 1185 MODULE_AUTHOR("Magnus Damm"); 1186 MODULE_DESCRIPTION("SuperH CMT Timer Driver"); 1187