1 /* 2 * SuperH Timer Support - CMT 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clockchips.h> 18 #include <linux/clocksource.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/irq.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_domain.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/sh_timer.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 35 struct sh_cmt_device; 36 37 /* 38 * The CMT comes in 5 different identified flavours, depending not only on the 39 * SoC but also on the particular instance. The following table lists the main 40 * characteristics of those flavours. 41 * 42 * 16B 32B 32B-F 48B 48B-2 43 * ----------------------------------------------------------------------------- 44 * Channels 2 1/4 1 6 2/8 45 * Control Width 16 16 16 16 32 46 * Counter Width 16 32 32 32/48 32/48 47 * Shared Start/Stop Y Y Y Y N 48 * 49 * The 48-bit gen2 version has a per-channel start/stop register located in the 50 * channel registers block. All other versions have a shared start/stop register 51 * located in the global space. 52 * 53 * Channels are indexed from 0 to N-1 in the documentation. The channel index 54 * infers the start/stop bit position in the control register and the channel 55 * registers block address. Some CMT instances have a subset of channels 56 * available, in which case the index in the documentation doesn't match the 57 * "real" index as implemented in hardware. This is for instance the case with 58 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 59 * in the documentation but using start/stop bit 5 and having its registers 60 * block at 0x60. 61 * 62 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit 63 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. 64 */ 65 66 enum sh_cmt_model { 67 SH_CMT_16BIT, 68 SH_CMT_32BIT, 69 SH_CMT_32BIT_FAST, 70 SH_CMT_48BIT, 71 SH_CMT_48BIT_GEN2, 72 }; 73 74 struct sh_cmt_info { 75 enum sh_cmt_model model; 76 77 unsigned long width; /* 16 or 32 bit version of hardware block */ 78 unsigned long overflow_bit; 79 unsigned long clear_bits; 80 81 /* callbacks for CMSTR and CMCSR access */ 82 unsigned long (*read_control)(void __iomem *base, unsigned long offs); 83 void (*write_control)(void __iomem *base, unsigned long offs, 84 unsigned long value); 85 86 /* callbacks for CMCNT and CMCOR access */ 87 unsigned long (*read_count)(void __iomem *base, unsigned long offs); 88 void (*write_count)(void __iomem *base, unsigned long offs, 89 unsigned long value); 90 }; 91 92 struct sh_cmt_channel { 93 struct sh_cmt_device *cmt; 94 95 unsigned int index; /* Index in the documentation */ 96 unsigned int hwidx; /* Real hardware index */ 97 98 void __iomem *iostart; 99 void __iomem *ioctrl; 100 101 unsigned int timer_bit; 102 unsigned long flags; 103 unsigned long match_value; 104 unsigned long next_match_value; 105 unsigned long max_match_value; 106 raw_spinlock_t lock; 107 struct clock_event_device ced; 108 struct clocksource cs; 109 unsigned long total_cycles; 110 bool cs_enabled; 111 }; 112 113 struct sh_cmt_device { 114 struct platform_device *pdev; 115 116 const struct sh_cmt_info *info; 117 118 void __iomem *mapbase; 119 struct clk *clk; 120 unsigned long rate; 121 122 raw_spinlock_t lock; /* Protect the shared start/stop register */ 123 124 struct sh_cmt_channel *channels; 125 unsigned int num_channels; 126 unsigned int hw_channels; 127 128 bool has_clockevent; 129 bool has_clocksource; 130 }; 131 132 #define SH_CMT16_CMCSR_CMF (1 << 7) 133 #define SH_CMT16_CMCSR_CMIE (1 << 6) 134 #define SH_CMT16_CMCSR_CKS8 (0 << 0) 135 #define SH_CMT16_CMCSR_CKS32 (1 << 0) 136 #define SH_CMT16_CMCSR_CKS128 (2 << 0) 137 #define SH_CMT16_CMCSR_CKS512 (3 << 0) 138 #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) 139 140 #define SH_CMT32_CMCSR_CMF (1 << 15) 141 #define SH_CMT32_CMCSR_OVF (1 << 14) 142 #define SH_CMT32_CMCSR_WRFLG (1 << 13) 143 #define SH_CMT32_CMCSR_STTF (1 << 12) 144 #define SH_CMT32_CMCSR_STPF (1 << 11) 145 #define SH_CMT32_CMCSR_SSIE (1 << 10) 146 #define SH_CMT32_CMCSR_CMS (1 << 9) 147 #define SH_CMT32_CMCSR_CMM (1 << 8) 148 #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) 149 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) 150 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) 151 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) 152 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) 153 #define SH_CMT32_CMCSR_DBGIVD (1 << 3) 154 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) 155 #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) 156 #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) 157 #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) 158 #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) 159 160 static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) 161 { 162 return ioread16(base + (offs << 1)); 163 } 164 165 static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) 166 { 167 return ioread32(base + (offs << 2)); 168 } 169 170 static void sh_cmt_write16(void __iomem *base, unsigned long offs, 171 unsigned long value) 172 { 173 iowrite16(value, base + (offs << 1)); 174 } 175 176 static void sh_cmt_write32(void __iomem *base, unsigned long offs, 177 unsigned long value) 178 { 179 iowrite32(value, base + (offs << 2)); 180 } 181 182 static const struct sh_cmt_info sh_cmt_info[] = { 183 [SH_CMT_16BIT] = { 184 .model = SH_CMT_16BIT, 185 .width = 16, 186 .overflow_bit = SH_CMT16_CMCSR_CMF, 187 .clear_bits = ~SH_CMT16_CMCSR_CMF, 188 .read_control = sh_cmt_read16, 189 .write_control = sh_cmt_write16, 190 .read_count = sh_cmt_read16, 191 .write_count = sh_cmt_write16, 192 }, 193 [SH_CMT_32BIT] = { 194 .model = SH_CMT_32BIT, 195 .width = 32, 196 .overflow_bit = SH_CMT32_CMCSR_CMF, 197 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 198 .read_control = sh_cmt_read16, 199 .write_control = sh_cmt_write16, 200 .read_count = sh_cmt_read32, 201 .write_count = sh_cmt_write32, 202 }, 203 [SH_CMT_32BIT_FAST] = { 204 .model = SH_CMT_32BIT_FAST, 205 .width = 32, 206 .overflow_bit = SH_CMT32_CMCSR_CMF, 207 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 208 .read_control = sh_cmt_read16, 209 .write_control = sh_cmt_write16, 210 .read_count = sh_cmt_read32, 211 .write_count = sh_cmt_write32, 212 }, 213 [SH_CMT_48BIT] = { 214 .model = SH_CMT_48BIT, 215 .width = 32, 216 .overflow_bit = SH_CMT32_CMCSR_CMF, 217 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 218 .read_control = sh_cmt_read32, 219 .write_control = sh_cmt_write32, 220 .read_count = sh_cmt_read32, 221 .write_count = sh_cmt_write32, 222 }, 223 [SH_CMT_48BIT_GEN2] = { 224 .model = SH_CMT_48BIT_GEN2, 225 .width = 32, 226 .overflow_bit = SH_CMT32_CMCSR_CMF, 227 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 228 .read_control = sh_cmt_read32, 229 .write_control = sh_cmt_write32, 230 .read_count = sh_cmt_read32, 231 .write_count = sh_cmt_write32, 232 }, 233 }; 234 235 #define CMCSR 0 /* channel register */ 236 #define CMCNT 1 /* channel register */ 237 #define CMCOR 2 /* channel register */ 238 239 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) 240 { 241 if (ch->iostart) 242 return ch->cmt->info->read_control(ch->iostart, 0); 243 else 244 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); 245 } 246 247 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, 248 unsigned long value) 249 { 250 if (ch->iostart) 251 ch->cmt->info->write_control(ch->iostart, 0, value); 252 else 253 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); 254 } 255 256 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) 257 { 258 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); 259 } 260 261 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, 262 unsigned long value) 263 { 264 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); 265 } 266 267 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) 268 { 269 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); 270 } 271 272 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, 273 unsigned long value) 274 { 275 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); 276 } 277 278 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, 279 unsigned long value) 280 { 281 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); 282 } 283 284 static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, 285 int *has_wrapped) 286 { 287 unsigned long v1, v2, v3; 288 int o1, o2; 289 290 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; 291 292 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 293 do { 294 o2 = o1; 295 v1 = sh_cmt_read_cmcnt(ch); 296 v2 = sh_cmt_read_cmcnt(ch); 297 v3 = sh_cmt_read_cmcnt(ch); 298 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; 299 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) 300 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); 301 302 *has_wrapped = o1; 303 return v2; 304 } 305 306 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) 307 { 308 unsigned long flags, value; 309 310 /* start stop register shared by multiple timer channels */ 311 raw_spin_lock_irqsave(&ch->cmt->lock, flags); 312 value = sh_cmt_read_cmstr(ch); 313 314 if (start) 315 value |= 1 << ch->timer_bit; 316 else 317 value &= ~(1 << ch->timer_bit); 318 319 sh_cmt_write_cmstr(ch, value); 320 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); 321 } 322 323 static int sh_cmt_enable(struct sh_cmt_channel *ch) 324 { 325 int k, ret; 326 327 pm_runtime_get_sync(&ch->cmt->pdev->dev); 328 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); 329 330 /* enable clock */ 331 ret = clk_enable(ch->cmt->clk); 332 if (ret) { 333 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", 334 ch->index); 335 goto err0; 336 } 337 338 /* make sure channel is disabled */ 339 sh_cmt_start_stop_ch(ch, 0); 340 341 /* configure channel, periodic mode and maximum timeout */ 342 if (ch->cmt->info->width == 16) { 343 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | 344 SH_CMT16_CMCSR_CKS512); 345 } else { 346 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | 347 SH_CMT32_CMCSR_CMTOUT_IE | 348 SH_CMT32_CMCSR_CMR_IRQ | 349 SH_CMT32_CMCSR_CKS_RCLK8); 350 } 351 352 sh_cmt_write_cmcor(ch, 0xffffffff); 353 sh_cmt_write_cmcnt(ch, 0); 354 355 /* 356 * According to the sh73a0 user's manual, as CMCNT can be operated 357 * only by the RCLK (Pseudo 32 KHz), there's one restriction on 358 * modifying CMCNT register; two RCLK cycles are necessary before 359 * this register is either read or any modification of the value 360 * it holds is reflected in the LSI's actual operation. 361 * 362 * While at it, we're supposed to clear out the CMCNT as of this 363 * moment, so make sure it's processed properly here. This will 364 * take RCLKx2 at maximum. 365 */ 366 for (k = 0; k < 100; k++) { 367 if (!sh_cmt_read_cmcnt(ch)) 368 break; 369 udelay(1); 370 } 371 372 if (sh_cmt_read_cmcnt(ch)) { 373 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", 374 ch->index); 375 ret = -ETIMEDOUT; 376 goto err1; 377 } 378 379 /* enable channel */ 380 sh_cmt_start_stop_ch(ch, 1); 381 return 0; 382 err1: 383 /* stop clock */ 384 clk_disable(ch->cmt->clk); 385 386 err0: 387 return ret; 388 } 389 390 static void sh_cmt_disable(struct sh_cmt_channel *ch) 391 { 392 /* disable channel */ 393 sh_cmt_start_stop_ch(ch, 0); 394 395 /* disable interrupts in CMT block */ 396 sh_cmt_write_cmcsr(ch, 0); 397 398 /* stop clock */ 399 clk_disable(ch->cmt->clk); 400 401 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); 402 pm_runtime_put(&ch->cmt->pdev->dev); 403 } 404 405 /* private flags */ 406 #define FLAG_CLOCKEVENT (1 << 0) 407 #define FLAG_CLOCKSOURCE (1 << 1) 408 #define FLAG_REPROGRAM (1 << 2) 409 #define FLAG_SKIPEVENT (1 << 3) 410 #define FLAG_IRQCONTEXT (1 << 4) 411 412 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, 413 int absolute) 414 { 415 unsigned long new_match; 416 unsigned long value = ch->next_match_value; 417 unsigned long delay = 0; 418 unsigned long now = 0; 419 int has_wrapped; 420 421 now = sh_cmt_get_counter(ch, &has_wrapped); 422 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ 423 424 if (has_wrapped) { 425 /* we're competing with the interrupt handler. 426 * -> let the interrupt handler reprogram the timer. 427 * -> interrupt number two handles the event. 428 */ 429 ch->flags |= FLAG_SKIPEVENT; 430 return; 431 } 432 433 if (absolute) 434 now = 0; 435 436 do { 437 /* reprogram the timer hardware, 438 * but don't save the new match value yet. 439 */ 440 new_match = now + value + delay; 441 if (new_match > ch->max_match_value) 442 new_match = ch->max_match_value; 443 444 sh_cmt_write_cmcor(ch, new_match); 445 446 now = sh_cmt_get_counter(ch, &has_wrapped); 447 if (has_wrapped && (new_match > ch->match_value)) { 448 /* we are changing to a greater match value, 449 * so this wrap must be caused by the counter 450 * matching the old value. 451 * -> first interrupt reprograms the timer. 452 * -> interrupt number two handles the event. 453 */ 454 ch->flags |= FLAG_SKIPEVENT; 455 break; 456 } 457 458 if (has_wrapped) { 459 /* we are changing to a smaller match value, 460 * so the wrap must be caused by the counter 461 * matching the new value. 462 * -> save programmed match value. 463 * -> let isr handle the event. 464 */ 465 ch->match_value = new_match; 466 break; 467 } 468 469 /* be safe: verify hardware settings */ 470 if (now < new_match) { 471 /* timer value is below match value, all good. 472 * this makes sure we won't miss any match events. 473 * -> save programmed match value. 474 * -> let isr handle the event. 475 */ 476 ch->match_value = new_match; 477 break; 478 } 479 480 /* the counter has reached a value greater 481 * than our new match value. and since the 482 * has_wrapped flag isn't set we must have 483 * programmed a too close event. 484 * -> increase delay and retry. 485 */ 486 if (delay) 487 delay <<= 1; 488 else 489 delay = 1; 490 491 if (!delay) 492 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", 493 ch->index); 494 495 } while (delay); 496 } 497 498 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) 499 { 500 if (delta > ch->max_match_value) 501 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", 502 ch->index); 503 504 ch->next_match_value = delta; 505 sh_cmt_clock_event_program_verify(ch, 0); 506 } 507 508 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) 509 { 510 unsigned long flags; 511 512 raw_spin_lock_irqsave(&ch->lock, flags); 513 __sh_cmt_set_next(ch, delta); 514 raw_spin_unlock_irqrestore(&ch->lock, flags); 515 } 516 517 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) 518 { 519 struct sh_cmt_channel *ch = dev_id; 520 521 /* clear flags */ 522 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & 523 ch->cmt->info->clear_bits); 524 525 /* update clock source counter to begin with if enabled 526 * the wrap flag should be cleared by the timer specific 527 * isr before we end up here. 528 */ 529 if (ch->flags & FLAG_CLOCKSOURCE) 530 ch->total_cycles += ch->match_value + 1; 531 532 if (!(ch->flags & FLAG_REPROGRAM)) 533 ch->next_match_value = ch->max_match_value; 534 535 ch->flags |= FLAG_IRQCONTEXT; 536 537 if (ch->flags & FLAG_CLOCKEVENT) { 538 if (!(ch->flags & FLAG_SKIPEVENT)) { 539 if (clockevent_state_oneshot(&ch->ced)) { 540 ch->next_match_value = ch->max_match_value; 541 ch->flags |= FLAG_REPROGRAM; 542 } 543 544 ch->ced.event_handler(&ch->ced); 545 } 546 } 547 548 ch->flags &= ~FLAG_SKIPEVENT; 549 550 if (ch->flags & FLAG_REPROGRAM) { 551 ch->flags &= ~FLAG_REPROGRAM; 552 sh_cmt_clock_event_program_verify(ch, 1); 553 554 if (ch->flags & FLAG_CLOCKEVENT) 555 if ((clockevent_state_shutdown(&ch->ced)) 556 || (ch->match_value == ch->next_match_value)) 557 ch->flags &= ~FLAG_REPROGRAM; 558 } 559 560 ch->flags &= ~FLAG_IRQCONTEXT; 561 562 return IRQ_HANDLED; 563 } 564 565 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) 566 { 567 int ret = 0; 568 unsigned long flags; 569 570 raw_spin_lock_irqsave(&ch->lock, flags); 571 572 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 573 ret = sh_cmt_enable(ch); 574 575 if (ret) 576 goto out; 577 ch->flags |= flag; 578 579 /* setup timeout if no clockevent */ 580 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) 581 __sh_cmt_set_next(ch, ch->max_match_value); 582 out: 583 raw_spin_unlock_irqrestore(&ch->lock, flags); 584 585 return ret; 586 } 587 588 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) 589 { 590 unsigned long flags; 591 unsigned long f; 592 593 raw_spin_lock_irqsave(&ch->lock, flags); 594 595 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 596 ch->flags &= ~flag; 597 598 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 599 sh_cmt_disable(ch); 600 601 /* adjust the timeout to maximum if only clocksource left */ 602 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) 603 __sh_cmt_set_next(ch, ch->max_match_value); 604 605 raw_spin_unlock_irqrestore(&ch->lock, flags); 606 } 607 608 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) 609 { 610 return container_of(cs, struct sh_cmt_channel, cs); 611 } 612 613 static u64 sh_cmt_clocksource_read(struct clocksource *cs) 614 { 615 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 616 unsigned long flags, raw; 617 unsigned long value; 618 int has_wrapped; 619 620 raw_spin_lock_irqsave(&ch->lock, flags); 621 value = ch->total_cycles; 622 raw = sh_cmt_get_counter(ch, &has_wrapped); 623 624 if (unlikely(has_wrapped)) 625 raw += ch->match_value + 1; 626 raw_spin_unlock_irqrestore(&ch->lock, flags); 627 628 return value + raw; 629 } 630 631 static int sh_cmt_clocksource_enable(struct clocksource *cs) 632 { 633 int ret; 634 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 635 636 WARN_ON(ch->cs_enabled); 637 638 ch->total_cycles = 0; 639 640 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); 641 if (!ret) 642 ch->cs_enabled = true; 643 644 return ret; 645 } 646 647 static void sh_cmt_clocksource_disable(struct clocksource *cs) 648 { 649 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 650 651 WARN_ON(!ch->cs_enabled); 652 653 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 654 ch->cs_enabled = false; 655 } 656 657 static void sh_cmt_clocksource_suspend(struct clocksource *cs) 658 { 659 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 660 661 if (!ch->cs_enabled) 662 return; 663 664 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 665 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); 666 } 667 668 static void sh_cmt_clocksource_resume(struct clocksource *cs) 669 { 670 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 671 672 if (!ch->cs_enabled) 673 return; 674 675 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); 676 sh_cmt_start(ch, FLAG_CLOCKSOURCE); 677 } 678 679 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, 680 const char *name) 681 { 682 struct clocksource *cs = &ch->cs; 683 684 cs->name = name; 685 cs->rating = 125; 686 cs->read = sh_cmt_clocksource_read; 687 cs->enable = sh_cmt_clocksource_enable; 688 cs->disable = sh_cmt_clocksource_disable; 689 cs->suspend = sh_cmt_clocksource_suspend; 690 cs->resume = sh_cmt_clocksource_resume; 691 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 692 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 693 694 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", 695 ch->index); 696 697 clocksource_register_hz(cs, ch->cmt->rate); 698 return 0; 699 } 700 701 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) 702 { 703 return container_of(ced, struct sh_cmt_channel, ced); 704 } 705 706 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) 707 { 708 sh_cmt_start(ch, FLAG_CLOCKEVENT); 709 710 if (periodic) 711 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); 712 else 713 sh_cmt_set_next(ch, ch->max_match_value); 714 } 715 716 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) 717 { 718 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 719 720 sh_cmt_stop(ch, FLAG_CLOCKEVENT); 721 return 0; 722 } 723 724 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, 725 int periodic) 726 { 727 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 728 729 /* deal with old setting first */ 730 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 731 sh_cmt_stop(ch, FLAG_CLOCKEVENT); 732 733 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", 734 ch->index, periodic ? "periodic" : "oneshot"); 735 sh_cmt_clock_event_start(ch, periodic); 736 return 0; 737 } 738 739 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) 740 { 741 return sh_cmt_clock_event_set_state(ced, 0); 742 } 743 744 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) 745 { 746 return sh_cmt_clock_event_set_state(ced, 1); 747 } 748 749 static int sh_cmt_clock_event_next(unsigned long delta, 750 struct clock_event_device *ced) 751 { 752 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 753 754 BUG_ON(!clockevent_state_oneshot(ced)); 755 if (likely(ch->flags & FLAG_IRQCONTEXT)) 756 ch->next_match_value = delta - 1; 757 else 758 sh_cmt_set_next(ch, delta - 1); 759 760 return 0; 761 } 762 763 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) 764 { 765 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 766 767 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); 768 clk_unprepare(ch->cmt->clk); 769 } 770 771 static void sh_cmt_clock_event_resume(struct clock_event_device *ced) 772 { 773 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 774 775 clk_prepare(ch->cmt->clk); 776 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); 777 } 778 779 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, 780 const char *name) 781 { 782 struct clock_event_device *ced = &ch->ced; 783 int irq; 784 int ret; 785 786 irq = platform_get_irq(ch->cmt->pdev, ch->index); 787 if (irq < 0) { 788 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", 789 ch->index); 790 return irq; 791 } 792 793 ret = request_irq(irq, sh_cmt_interrupt, 794 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, 795 dev_name(&ch->cmt->pdev->dev), ch); 796 if (ret) { 797 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", 798 ch->index, irq); 799 return ret; 800 } 801 802 ced->name = name; 803 ced->features = CLOCK_EVT_FEAT_PERIODIC; 804 ced->features |= CLOCK_EVT_FEAT_ONESHOT; 805 ced->rating = 125; 806 ced->cpumask = cpu_possible_mask; 807 ced->set_next_event = sh_cmt_clock_event_next; 808 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; 809 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; 810 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; 811 ced->suspend = sh_cmt_clock_event_suspend; 812 ced->resume = sh_cmt_clock_event_resume; 813 814 /* TODO: calculate good shift from rate and counter bit width */ 815 ced->shift = 32; 816 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); 817 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); 818 ced->max_delta_ticks = ch->max_match_value; 819 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); 820 ced->min_delta_ticks = 0x1f; 821 822 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", 823 ch->index); 824 clockevents_register_device(ced); 825 826 return 0; 827 } 828 829 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, 830 bool clockevent, bool clocksource) 831 { 832 int ret; 833 834 if (clockevent) { 835 ch->cmt->has_clockevent = true; 836 ret = sh_cmt_register_clockevent(ch, name); 837 if (ret < 0) 838 return ret; 839 } 840 841 if (clocksource) { 842 ch->cmt->has_clocksource = true; 843 sh_cmt_register_clocksource(ch, name); 844 } 845 846 return 0; 847 } 848 849 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, 850 unsigned int hwidx, bool clockevent, 851 bool clocksource, struct sh_cmt_device *cmt) 852 { 853 int ret; 854 855 /* Skip unused channels. */ 856 if (!clockevent && !clocksource) 857 return 0; 858 859 ch->cmt = cmt; 860 ch->index = index; 861 ch->hwidx = hwidx; 862 863 /* 864 * Compute the address of the channel control register block. For the 865 * timers with a per-channel start/stop register, compute its address 866 * as well. 867 */ 868 switch (cmt->info->model) { 869 case SH_CMT_16BIT: 870 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; 871 break; 872 case SH_CMT_32BIT: 873 case SH_CMT_48BIT: 874 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; 875 break; 876 case SH_CMT_32BIT_FAST: 877 /* 878 * The 32-bit "fast" timer has a single channel at hwidx 5 but 879 * is located at offset 0x40 instead of 0x60 for some reason. 880 */ 881 ch->ioctrl = cmt->mapbase + 0x40; 882 break; 883 case SH_CMT_48BIT_GEN2: 884 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; 885 ch->ioctrl = ch->iostart + 0x10; 886 break; 887 } 888 889 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) 890 ch->max_match_value = ~0; 891 else 892 ch->max_match_value = (1 << cmt->info->width) - 1; 893 894 ch->match_value = ch->max_match_value; 895 raw_spin_lock_init(&ch->lock); 896 897 ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; 898 899 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), 900 clockevent, clocksource); 901 if (ret) { 902 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", 903 ch->index); 904 return ret; 905 } 906 ch->cs_enabled = false; 907 908 return 0; 909 } 910 911 static int sh_cmt_map_memory(struct sh_cmt_device *cmt) 912 { 913 struct resource *mem; 914 915 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); 916 if (!mem) { 917 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); 918 return -ENXIO; 919 } 920 921 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); 922 if (cmt->mapbase == NULL) { 923 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); 924 return -ENXIO; 925 } 926 927 return 0; 928 } 929 930 static const struct platform_device_id sh_cmt_id_table[] = { 931 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, 932 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, 933 { } 934 }; 935 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); 936 937 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { 938 { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, 939 { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, 940 { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, 941 { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, 942 { } 943 }; 944 MODULE_DEVICE_TABLE(of, sh_cmt_of_table); 945 946 static int sh_cmt_parse_dt(struct sh_cmt_device *cmt) 947 { 948 struct device_node *np = cmt->pdev->dev.of_node; 949 950 return of_property_read_u32(np, "renesas,channels-mask", 951 &cmt->hw_channels); 952 } 953 954 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) 955 { 956 unsigned int mask; 957 unsigned int i; 958 int ret; 959 960 cmt->pdev = pdev; 961 raw_spin_lock_init(&cmt->lock); 962 963 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 964 const struct of_device_id *id; 965 966 id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); 967 cmt->info = id->data; 968 969 ret = sh_cmt_parse_dt(cmt); 970 if (ret < 0) 971 return ret; 972 } else if (pdev->dev.platform_data) { 973 struct sh_timer_config *cfg = pdev->dev.platform_data; 974 const struct platform_device_id *id = pdev->id_entry; 975 976 cmt->info = (const struct sh_cmt_info *)id->driver_data; 977 cmt->hw_channels = cfg->channels_mask; 978 } else { 979 dev_err(&cmt->pdev->dev, "missing platform data\n"); 980 return -ENXIO; 981 } 982 983 /* Get hold of clock. */ 984 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); 985 if (IS_ERR(cmt->clk)) { 986 dev_err(&cmt->pdev->dev, "cannot get clock\n"); 987 return PTR_ERR(cmt->clk); 988 } 989 990 ret = clk_prepare(cmt->clk); 991 if (ret < 0) 992 goto err_clk_put; 993 994 /* Determine clock rate. */ 995 ret = clk_enable(cmt->clk); 996 if (ret < 0) 997 goto err_clk_unprepare; 998 999 if (cmt->info->width == 16) 1000 cmt->rate = clk_get_rate(cmt->clk) / 512; 1001 else 1002 cmt->rate = clk_get_rate(cmt->clk) / 8; 1003 1004 clk_disable(cmt->clk); 1005 1006 /* Map the memory resource(s). */ 1007 ret = sh_cmt_map_memory(cmt); 1008 if (ret < 0) 1009 goto err_clk_unprepare; 1010 1011 /* Allocate and setup the channels. */ 1012 cmt->num_channels = hweight8(cmt->hw_channels); 1013 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), 1014 GFP_KERNEL); 1015 if (cmt->channels == NULL) { 1016 ret = -ENOMEM; 1017 goto err_unmap; 1018 } 1019 1020 /* 1021 * Use the first channel as a clock event device and the second channel 1022 * as a clock source. If only one channel is available use it for both. 1023 */ 1024 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { 1025 unsigned int hwidx = ffs(mask) - 1; 1026 bool clocksource = i == 1 || cmt->num_channels == 1; 1027 bool clockevent = i == 0; 1028 1029 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, 1030 clockevent, clocksource, cmt); 1031 if (ret < 0) 1032 goto err_unmap; 1033 1034 mask &= ~(1 << hwidx); 1035 } 1036 1037 platform_set_drvdata(pdev, cmt); 1038 1039 return 0; 1040 1041 err_unmap: 1042 kfree(cmt->channels); 1043 iounmap(cmt->mapbase); 1044 err_clk_unprepare: 1045 clk_unprepare(cmt->clk); 1046 err_clk_put: 1047 clk_put(cmt->clk); 1048 return ret; 1049 } 1050 1051 static int sh_cmt_probe(struct platform_device *pdev) 1052 { 1053 struct sh_cmt_device *cmt = platform_get_drvdata(pdev); 1054 int ret; 1055 1056 if (!is_early_platform_device(pdev)) { 1057 pm_runtime_set_active(&pdev->dev); 1058 pm_runtime_enable(&pdev->dev); 1059 } 1060 1061 if (cmt) { 1062 dev_info(&pdev->dev, "kept as earlytimer\n"); 1063 goto out; 1064 } 1065 1066 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); 1067 if (cmt == NULL) 1068 return -ENOMEM; 1069 1070 ret = sh_cmt_setup(cmt, pdev); 1071 if (ret) { 1072 kfree(cmt); 1073 pm_runtime_idle(&pdev->dev); 1074 return ret; 1075 } 1076 if (is_early_platform_device(pdev)) 1077 return 0; 1078 1079 out: 1080 if (cmt->has_clockevent || cmt->has_clocksource) 1081 pm_runtime_irq_safe(&pdev->dev); 1082 else 1083 pm_runtime_idle(&pdev->dev); 1084 1085 return 0; 1086 } 1087 1088 static int sh_cmt_remove(struct platform_device *pdev) 1089 { 1090 return -EBUSY; /* cannot unregister clockevent and clocksource */ 1091 } 1092 1093 static struct platform_driver sh_cmt_device_driver = { 1094 .probe = sh_cmt_probe, 1095 .remove = sh_cmt_remove, 1096 .driver = { 1097 .name = "sh_cmt", 1098 .of_match_table = of_match_ptr(sh_cmt_of_table), 1099 }, 1100 .id_table = sh_cmt_id_table, 1101 }; 1102 1103 static int __init sh_cmt_init(void) 1104 { 1105 return platform_driver_register(&sh_cmt_device_driver); 1106 } 1107 1108 static void __exit sh_cmt_exit(void) 1109 { 1110 platform_driver_unregister(&sh_cmt_device_driver); 1111 } 1112 1113 early_platform_init("earlytimer", &sh_cmt_device_driver); 1114 subsys_initcall(sh_cmt_init); 1115 module_exit(sh_cmt_exit); 1116 1117 MODULE_AUTHOR("Magnus Damm"); 1118 MODULE_DESCRIPTION("SuperH CMT Timer Driver"); 1119 MODULE_LICENSE("GPL v2"); 1120