1 /* 2 * SuperH Timer Support - CMT 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/io.h> 26 #include <linux/clk.h> 27 #include <linux/irq.h> 28 #include <linux/err.h> 29 #include <linux/delay.h> 30 #include <linux/clocksource.h> 31 #include <linux/clockchips.h> 32 #include <linux/sh_timer.h> 33 #include <linux/slab.h> 34 #include <linux/module.h> 35 #include <linux/pm_domain.h> 36 #include <linux/pm_runtime.h> 37 38 struct sh_cmt_priv { 39 void __iomem *mapbase; 40 struct clk *clk; 41 unsigned long width; /* 16 or 32 bit version of hardware block */ 42 unsigned long overflow_bit; 43 unsigned long clear_bits; 44 struct irqaction irqaction; 45 struct platform_device *pdev; 46 47 unsigned long flags; 48 unsigned long match_value; 49 unsigned long next_match_value; 50 unsigned long max_match_value; 51 unsigned long rate; 52 raw_spinlock_t lock; 53 struct clock_event_device ced; 54 struct clocksource cs; 55 unsigned long total_cycles; 56 bool cs_enabled; 57 58 /* callbacks for CMSTR and CMCSR access */ 59 unsigned long (*read_control)(void __iomem *base, unsigned long offs); 60 void (*write_control)(void __iomem *base, unsigned long offs, 61 unsigned long value); 62 63 /* callbacks for CMCNT and CMCOR access */ 64 unsigned long (*read_count)(void __iomem *base, unsigned long offs); 65 void (*write_count)(void __iomem *base, unsigned long offs, 66 unsigned long value); 67 }; 68 69 /* Examples of supported CMT timer register layouts and I/O access widths: 70 * 71 * "16-bit counter and 16-bit control" as found on sh7263: 72 * CMSTR 0xfffec000 16-bit 73 * CMCSR 0xfffec002 16-bit 74 * CMCNT 0xfffec004 16-bit 75 * CMCOR 0xfffec006 16-bit 76 * 77 * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740: 78 * CMSTR 0xffca0000 16-bit 79 * CMCSR 0xffca0060 16-bit 80 * CMCNT 0xffca0064 32-bit 81 * CMCOR 0xffca0068 32-bit 82 */ 83 84 static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) 85 { 86 return ioread16(base + (offs << 1)); 87 } 88 89 static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) 90 { 91 return ioread32(base + (offs << 2)); 92 } 93 94 static void sh_cmt_write16(void __iomem *base, unsigned long offs, 95 unsigned long value) 96 { 97 iowrite16(value, base + (offs << 1)); 98 } 99 100 static void sh_cmt_write32(void __iomem *base, unsigned long offs, 101 unsigned long value) 102 { 103 iowrite32(value, base + (offs << 2)); 104 } 105 106 #define CMCSR 0 /* channel register */ 107 #define CMCNT 1 /* channel register */ 108 #define CMCOR 2 /* channel register */ 109 110 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p) 111 { 112 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 113 114 return p->read_control(p->mapbase - cfg->channel_offset, 0); 115 } 116 117 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p) 118 { 119 return p->read_control(p->mapbase, CMCSR); 120 } 121 122 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p) 123 { 124 return p->read_count(p->mapbase, CMCNT); 125 } 126 127 static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p, 128 unsigned long value) 129 { 130 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 131 132 p->write_control(p->mapbase - cfg->channel_offset, 0, value); 133 } 134 135 static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p, 136 unsigned long value) 137 { 138 p->write_control(p->mapbase, CMCSR, value); 139 } 140 141 static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p, 142 unsigned long value) 143 { 144 p->write_count(p->mapbase, CMCNT, value); 145 } 146 147 static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p, 148 unsigned long value) 149 { 150 p->write_count(p->mapbase, CMCOR, value); 151 } 152 153 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p, 154 int *has_wrapped) 155 { 156 unsigned long v1, v2, v3; 157 int o1, o2; 158 159 o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit; 160 161 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 162 do { 163 o2 = o1; 164 v1 = sh_cmt_read_cmcnt(p); 165 v2 = sh_cmt_read_cmcnt(p); 166 v3 = sh_cmt_read_cmcnt(p); 167 o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit; 168 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) 169 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); 170 171 *has_wrapped = o1; 172 return v2; 173 } 174 175 static DEFINE_RAW_SPINLOCK(sh_cmt_lock); 176 177 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) 178 { 179 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 180 unsigned long flags, value; 181 182 /* start stop register shared by multiple timer channels */ 183 raw_spin_lock_irqsave(&sh_cmt_lock, flags); 184 value = sh_cmt_read_cmstr(p); 185 186 if (start) 187 value |= 1 << cfg->timer_bit; 188 else 189 value &= ~(1 << cfg->timer_bit); 190 191 sh_cmt_write_cmstr(p, value); 192 raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); 193 } 194 195 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) 196 { 197 int k, ret; 198 199 pm_runtime_get_sync(&p->pdev->dev); 200 dev_pm_syscore_device(&p->pdev->dev, true); 201 202 /* enable clock */ 203 ret = clk_enable(p->clk); 204 if (ret) { 205 dev_err(&p->pdev->dev, "cannot enable clock\n"); 206 goto err0; 207 } 208 209 /* make sure channel is disabled */ 210 sh_cmt_start_stop_ch(p, 0); 211 212 /* configure channel, periodic mode and maximum timeout */ 213 if (p->width == 16) { 214 *rate = clk_get_rate(p->clk) / 512; 215 sh_cmt_write_cmcsr(p, 0x43); 216 } else { 217 *rate = clk_get_rate(p->clk) / 8; 218 sh_cmt_write_cmcsr(p, 0x01a4); 219 } 220 221 sh_cmt_write_cmcor(p, 0xffffffff); 222 sh_cmt_write_cmcnt(p, 0); 223 224 /* 225 * According to the sh73a0 user's manual, as CMCNT can be operated 226 * only by the RCLK (Pseudo 32 KHz), there's one restriction on 227 * modifying CMCNT register; two RCLK cycles are necessary before 228 * this register is either read or any modification of the value 229 * it holds is reflected in the LSI's actual operation. 230 * 231 * While at it, we're supposed to clear out the CMCNT as of this 232 * moment, so make sure it's processed properly here. This will 233 * take RCLKx2 at maximum. 234 */ 235 for (k = 0; k < 100; k++) { 236 if (!sh_cmt_read_cmcnt(p)) 237 break; 238 udelay(1); 239 } 240 241 if (sh_cmt_read_cmcnt(p)) { 242 dev_err(&p->pdev->dev, "cannot clear CMCNT\n"); 243 ret = -ETIMEDOUT; 244 goto err1; 245 } 246 247 /* enable channel */ 248 sh_cmt_start_stop_ch(p, 1); 249 return 0; 250 err1: 251 /* stop clock */ 252 clk_disable(p->clk); 253 254 err0: 255 return ret; 256 } 257 258 static void sh_cmt_disable(struct sh_cmt_priv *p) 259 { 260 /* disable channel */ 261 sh_cmt_start_stop_ch(p, 0); 262 263 /* disable interrupts in CMT block */ 264 sh_cmt_write_cmcsr(p, 0); 265 266 /* stop clock */ 267 clk_disable(p->clk); 268 269 dev_pm_syscore_device(&p->pdev->dev, false); 270 pm_runtime_put(&p->pdev->dev); 271 } 272 273 /* private flags */ 274 #define FLAG_CLOCKEVENT (1 << 0) 275 #define FLAG_CLOCKSOURCE (1 << 1) 276 #define FLAG_REPROGRAM (1 << 2) 277 #define FLAG_SKIPEVENT (1 << 3) 278 #define FLAG_IRQCONTEXT (1 << 4) 279 280 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p, 281 int absolute) 282 { 283 unsigned long new_match; 284 unsigned long value = p->next_match_value; 285 unsigned long delay = 0; 286 unsigned long now = 0; 287 int has_wrapped; 288 289 now = sh_cmt_get_counter(p, &has_wrapped); 290 p->flags |= FLAG_REPROGRAM; /* force reprogram */ 291 292 if (has_wrapped) { 293 /* we're competing with the interrupt handler. 294 * -> let the interrupt handler reprogram the timer. 295 * -> interrupt number two handles the event. 296 */ 297 p->flags |= FLAG_SKIPEVENT; 298 return; 299 } 300 301 if (absolute) 302 now = 0; 303 304 do { 305 /* reprogram the timer hardware, 306 * but don't save the new match value yet. 307 */ 308 new_match = now + value + delay; 309 if (new_match > p->max_match_value) 310 new_match = p->max_match_value; 311 312 sh_cmt_write_cmcor(p, new_match); 313 314 now = sh_cmt_get_counter(p, &has_wrapped); 315 if (has_wrapped && (new_match > p->match_value)) { 316 /* we are changing to a greater match value, 317 * so this wrap must be caused by the counter 318 * matching the old value. 319 * -> first interrupt reprograms the timer. 320 * -> interrupt number two handles the event. 321 */ 322 p->flags |= FLAG_SKIPEVENT; 323 break; 324 } 325 326 if (has_wrapped) { 327 /* we are changing to a smaller match value, 328 * so the wrap must be caused by the counter 329 * matching the new value. 330 * -> save programmed match value. 331 * -> let isr handle the event. 332 */ 333 p->match_value = new_match; 334 break; 335 } 336 337 /* be safe: verify hardware settings */ 338 if (now < new_match) { 339 /* timer value is below match value, all good. 340 * this makes sure we won't miss any match events. 341 * -> save programmed match value. 342 * -> let isr handle the event. 343 */ 344 p->match_value = new_match; 345 break; 346 } 347 348 /* the counter has reached a value greater 349 * than our new match value. and since the 350 * has_wrapped flag isn't set we must have 351 * programmed a too close event. 352 * -> increase delay and retry. 353 */ 354 if (delay) 355 delay <<= 1; 356 else 357 delay = 1; 358 359 if (!delay) 360 dev_warn(&p->pdev->dev, "too long delay\n"); 361 362 } while (delay); 363 } 364 365 static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) 366 { 367 if (delta > p->max_match_value) 368 dev_warn(&p->pdev->dev, "delta out of range\n"); 369 370 p->next_match_value = delta; 371 sh_cmt_clock_event_program_verify(p, 0); 372 } 373 374 static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) 375 { 376 unsigned long flags; 377 378 raw_spin_lock_irqsave(&p->lock, flags); 379 __sh_cmt_set_next(p, delta); 380 raw_spin_unlock_irqrestore(&p->lock, flags); 381 } 382 383 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) 384 { 385 struct sh_cmt_priv *p = dev_id; 386 387 /* clear flags */ 388 sh_cmt_write_cmcsr(p, sh_cmt_read_cmcsr(p) & p->clear_bits); 389 390 /* update clock source counter to begin with if enabled 391 * the wrap flag should be cleared by the timer specific 392 * isr before we end up here. 393 */ 394 if (p->flags & FLAG_CLOCKSOURCE) 395 p->total_cycles += p->match_value + 1; 396 397 if (!(p->flags & FLAG_REPROGRAM)) 398 p->next_match_value = p->max_match_value; 399 400 p->flags |= FLAG_IRQCONTEXT; 401 402 if (p->flags & FLAG_CLOCKEVENT) { 403 if (!(p->flags & FLAG_SKIPEVENT)) { 404 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) { 405 p->next_match_value = p->max_match_value; 406 p->flags |= FLAG_REPROGRAM; 407 } 408 409 p->ced.event_handler(&p->ced); 410 } 411 } 412 413 p->flags &= ~FLAG_SKIPEVENT; 414 415 if (p->flags & FLAG_REPROGRAM) { 416 p->flags &= ~FLAG_REPROGRAM; 417 sh_cmt_clock_event_program_verify(p, 1); 418 419 if (p->flags & FLAG_CLOCKEVENT) 420 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) 421 || (p->match_value == p->next_match_value)) 422 p->flags &= ~FLAG_REPROGRAM; 423 } 424 425 p->flags &= ~FLAG_IRQCONTEXT; 426 427 return IRQ_HANDLED; 428 } 429 430 static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag) 431 { 432 int ret = 0; 433 unsigned long flags; 434 435 raw_spin_lock_irqsave(&p->lock, flags); 436 437 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 438 ret = sh_cmt_enable(p, &p->rate); 439 440 if (ret) 441 goto out; 442 p->flags |= flag; 443 444 /* setup timeout if no clockevent */ 445 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT))) 446 __sh_cmt_set_next(p, p->max_match_value); 447 out: 448 raw_spin_unlock_irqrestore(&p->lock, flags); 449 450 return ret; 451 } 452 453 static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag) 454 { 455 unsigned long flags; 456 unsigned long f; 457 458 raw_spin_lock_irqsave(&p->lock, flags); 459 460 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 461 p->flags &= ~flag; 462 463 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 464 sh_cmt_disable(p); 465 466 /* adjust the timeout to maximum if only clocksource left */ 467 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE)) 468 __sh_cmt_set_next(p, p->max_match_value); 469 470 raw_spin_unlock_irqrestore(&p->lock, flags); 471 } 472 473 static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs) 474 { 475 return container_of(cs, struct sh_cmt_priv, cs); 476 } 477 478 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) 479 { 480 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 481 unsigned long flags, raw; 482 unsigned long value; 483 int has_wrapped; 484 485 raw_spin_lock_irqsave(&p->lock, flags); 486 value = p->total_cycles; 487 raw = sh_cmt_get_counter(p, &has_wrapped); 488 489 if (unlikely(has_wrapped)) 490 raw += p->match_value + 1; 491 raw_spin_unlock_irqrestore(&p->lock, flags); 492 493 return value + raw; 494 } 495 496 static int sh_cmt_clocksource_enable(struct clocksource *cs) 497 { 498 int ret; 499 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 500 501 WARN_ON(p->cs_enabled); 502 503 p->total_cycles = 0; 504 505 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); 506 if (!ret) { 507 __clocksource_updatefreq_hz(cs, p->rate); 508 p->cs_enabled = true; 509 } 510 return ret; 511 } 512 513 static void sh_cmt_clocksource_disable(struct clocksource *cs) 514 { 515 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 516 517 WARN_ON(!p->cs_enabled); 518 519 sh_cmt_stop(p, FLAG_CLOCKSOURCE); 520 p->cs_enabled = false; 521 } 522 523 static void sh_cmt_clocksource_suspend(struct clocksource *cs) 524 { 525 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 526 527 sh_cmt_stop(p, FLAG_CLOCKSOURCE); 528 pm_genpd_syscore_poweroff(&p->pdev->dev); 529 } 530 531 static void sh_cmt_clocksource_resume(struct clocksource *cs) 532 { 533 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 534 535 pm_genpd_syscore_poweron(&p->pdev->dev); 536 sh_cmt_start(p, FLAG_CLOCKSOURCE); 537 } 538 539 static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, 540 char *name, unsigned long rating) 541 { 542 struct clocksource *cs = &p->cs; 543 544 cs->name = name; 545 cs->rating = rating; 546 cs->read = sh_cmt_clocksource_read; 547 cs->enable = sh_cmt_clocksource_enable; 548 cs->disable = sh_cmt_clocksource_disable; 549 cs->suspend = sh_cmt_clocksource_suspend; 550 cs->resume = sh_cmt_clocksource_resume; 551 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 552 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 553 554 dev_info(&p->pdev->dev, "used as clock source\n"); 555 556 /* Register with dummy 1 Hz value, gets updated in ->enable() */ 557 clocksource_register_hz(cs, 1); 558 return 0; 559 } 560 561 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) 562 { 563 return container_of(ced, struct sh_cmt_priv, ced); 564 } 565 566 static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic) 567 { 568 struct clock_event_device *ced = &p->ced; 569 570 sh_cmt_start(p, FLAG_CLOCKEVENT); 571 572 /* TODO: calculate good shift from rate and counter bit width */ 573 574 ced->shift = 32; 575 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); 576 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced); 577 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); 578 579 if (periodic) 580 sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1); 581 else 582 sh_cmt_set_next(p, p->max_match_value); 583 } 584 585 static void sh_cmt_clock_event_mode(enum clock_event_mode mode, 586 struct clock_event_device *ced) 587 { 588 struct sh_cmt_priv *p = ced_to_sh_cmt(ced); 589 590 /* deal with old setting first */ 591 switch (ced->mode) { 592 case CLOCK_EVT_MODE_PERIODIC: 593 case CLOCK_EVT_MODE_ONESHOT: 594 sh_cmt_stop(p, FLAG_CLOCKEVENT); 595 break; 596 default: 597 break; 598 } 599 600 switch (mode) { 601 case CLOCK_EVT_MODE_PERIODIC: 602 dev_info(&p->pdev->dev, "used for periodic clock events\n"); 603 sh_cmt_clock_event_start(p, 1); 604 break; 605 case CLOCK_EVT_MODE_ONESHOT: 606 dev_info(&p->pdev->dev, "used for oneshot clock events\n"); 607 sh_cmt_clock_event_start(p, 0); 608 break; 609 case CLOCK_EVT_MODE_SHUTDOWN: 610 case CLOCK_EVT_MODE_UNUSED: 611 sh_cmt_stop(p, FLAG_CLOCKEVENT); 612 break; 613 default: 614 break; 615 } 616 } 617 618 static int sh_cmt_clock_event_next(unsigned long delta, 619 struct clock_event_device *ced) 620 { 621 struct sh_cmt_priv *p = ced_to_sh_cmt(ced); 622 623 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); 624 if (likely(p->flags & FLAG_IRQCONTEXT)) 625 p->next_match_value = delta - 1; 626 else 627 sh_cmt_set_next(p, delta - 1); 628 629 return 0; 630 } 631 632 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) 633 { 634 pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev); 635 } 636 637 static void sh_cmt_clock_event_resume(struct clock_event_device *ced) 638 { 639 pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev); 640 } 641 642 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p, 643 char *name, unsigned long rating) 644 { 645 struct clock_event_device *ced = &p->ced; 646 647 memset(ced, 0, sizeof(*ced)); 648 649 ced->name = name; 650 ced->features = CLOCK_EVT_FEAT_PERIODIC; 651 ced->features |= CLOCK_EVT_FEAT_ONESHOT; 652 ced->rating = rating; 653 ced->cpumask = cpumask_of(0); 654 ced->set_next_event = sh_cmt_clock_event_next; 655 ced->set_mode = sh_cmt_clock_event_mode; 656 ced->suspend = sh_cmt_clock_event_suspend; 657 ced->resume = sh_cmt_clock_event_resume; 658 659 dev_info(&p->pdev->dev, "used for clock events\n"); 660 clockevents_register_device(ced); 661 } 662 663 static int sh_cmt_register(struct sh_cmt_priv *p, char *name, 664 unsigned long clockevent_rating, 665 unsigned long clocksource_rating) 666 { 667 if (clockevent_rating) 668 sh_cmt_register_clockevent(p, name, clockevent_rating); 669 670 if (clocksource_rating) 671 sh_cmt_register_clocksource(p, name, clocksource_rating); 672 673 return 0; 674 } 675 676 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) 677 { 678 struct sh_timer_config *cfg = pdev->dev.platform_data; 679 struct resource *res; 680 int irq, ret; 681 ret = -ENXIO; 682 683 memset(p, 0, sizeof(*p)); 684 p->pdev = pdev; 685 686 if (!cfg) { 687 dev_err(&p->pdev->dev, "missing platform data\n"); 688 goto err0; 689 } 690 691 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); 692 if (!res) { 693 dev_err(&p->pdev->dev, "failed to get I/O memory\n"); 694 goto err0; 695 } 696 697 irq = platform_get_irq(p->pdev, 0); 698 if (irq < 0) { 699 dev_err(&p->pdev->dev, "failed to get irq\n"); 700 goto err0; 701 } 702 703 /* map memory, let mapbase point to our channel */ 704 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 705 if (p->mapbase == NULL) { 706 dev_err(&p->pdev->dev, "failed to remap I/O memory\n"); 707 goto err0; 708 } 709 710 /* request irq using setup_irq() (too early for request_irq()) */ 711 p->irqaction.name = dev_name(&p->pdev->dev); 712 p->irqaction.handler = sh_cmt_interrupt; 713 p->irqaction.dev_id = p; 714 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \ 715 IRQF_IRQPOLL | IRQF_NOBALANCING; 716 717 /* get hold of clock */ 718 p->clk = clk_get(&p->pdev->dev, "cmt_fck"); 719 if (IS_ERR(p->clk)) { 720 dev_err(&p->pdev->dev, "cannot get clock\n"); 721 ret = PTR_ERR(p->clk); 722 goto err1; 723 } 724 725 p->read_control = sh_cmt_read16; 726 p->write_control = sh_cmt_write16; 727 728 if (resource_size(res) == 6) { 729 p->width = 16; 730 p->read_count = sh_cmt_read16; 731 p->write_count = sh_cmt_write16; 732 p->overflow_bit = 0x80; 733 p->clear_bits = ~0x80; 734 } else { 735 p->width = 32; 736 p->read_count = sh_cmt_read32; 737 p->write_count = sh_cmt_write32; 738 p->overflow_bit = 0x8000; 739 p->clear_bits = ~0xc000; 740 } 741 742 if (p->width == (sizeof(p->max_match_value) * 8)) 743 p->max_match_value = ~0; 744 else 745 p->max_match_value = (1 << p->width) - 1; 746 747 p->match_value = p->max_match_value; 748 raw_spin_lock_init(&p->lock); 749 750 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev), 751 cfg->clockevent_rating, 752 cfg->clocksource_rating); 753 if (ret) { 754 dev_err(&p->pdev->dev, "registration failed\n"); 755 goto err2; 756 } 757 p->cs_enabled = false; 758 759 ret = setup_irq(irq, &p->irqaction); 760 if (ret) { 761 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq); 762 goto err2; 763 } 764 765 platform_set_drvdata(pdev, p); 766 767 return 0; 768 err2: 769 clk_put(p->clk); 770 771 err1: 772 iounmap(p->mapbase); 773 err0: 774 return ret; 775 } 776 777 static int sh_cmt_probe(struct platform_device *pdev) 778 { 779 struct sh_cmt_priv *p = platform_get_drvdata(pdev); 780 struct sh_timer_config *cfg = pdev->dev.platform_data; 781 int ret; 782 783 if (!is_early_platform_device(pdev)) { 784 pm_runtime_set_active(&pdev->dev); 785 pm_runtime_enable(&pdev->dev); 786 } 787 788 if (p) { 789 dev_info(&pdev->dev, "kept as earlytimer\n"); 790 goto out; 791 } 792 793 p = kmalloc(sizeof(*p), GFP_KERNEL); 794 if (p == NULL) { 795 dev_err(&pdev->dev, "failed to allocate driver data\n"); 796 return -ENOMEM; 797 } 798 799 ret = sh_cmt_setup(p, pdev); 800 if (ret) { 801 kfree(p); 802 pm_runtime_idle(&pdev->dev); 803 return ret; 804 } 805 if (is_early_platform_device(pdev)) 806 return 0; 807 808 out: 809 if (cfg->clockevent_rating || cfg->clocksource_rating) 810 pm_runtime_irq_safe(&pdev->dev); 811 else 812 pm_runtime_idle(&pdev->dev); 813 814 return 0; 815 } 816 817 static int sh_cmt_remove(struct platform_device *pdev) 818 { 819 return -EBUSY; /* cannot unregister clockevent and clocksource */ 820 } 821 822 static struct platform_driver sh_cmt_device_driver = { 823 .probe = sh_cmt_probe, 824 .remove = sh_cmt_remove, 825 .driver = { 826 .name = "sh_cmt", 827 } 828 }; 829 830 static int __init sh_cmt_init(void) 831 { 832 return platform_driver_register(&sh_cmt_device_driver); 833 } 834 835 static void __exit sh_cmt_exit(void) 836 { 837 platform_driver_unregister(&sh_cmt_device_driver); 838 } 839 840 early_platform_init("earlytimer", &sh_cmt_device_driver); 841 subsys_initcall(sh_cmt_init); 842 module_exit(sh_cmt_exit); 843 844 MODULE_AUTHOR("Magnus Damm"); 845 MODULE_DESCRIPTION("SuperH CMT Timer Driver"); 846 MODULE_LICENSE("GPL v2"); 847