1 /*
2  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3  *		http://www.samsung.com/
4  *
5  * samsung - Common hr-timer support (s3c and s5p)
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10 */
11 
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/sched_clock.h>
25 
26 #include <clocksource/samsung_pwm.h>
27 
28 
29 /*
30  * Clocksource driver
31  */
32 
33 #define REG_TCFG0			0x00
34 #define REG_TCFG1			0x04
35 #define REG_TCON			0x08
36 #define REG_TINT_CSTAT			0x44
37 
38 #define REG_TCNTB(chan)			(0x0c + 12 * (chan))
39 #define REG_TCMPB(chan)			(0x10 + 12 * (chan))
40 
41 #define TCFG0_PRESCALER_MASK		0xff
42 #define TCFG0_PRESCALER1_SHIFT		8
43 
44 #define TCFG1_SHIFT(x)	  		((x) * 4)
45 #define TCFG1_MUX_MASK	  		0xf
46 
47 /*
48  * Each channel occupies 4 bits in TCON register, but there is a gap of 4
49  * bits (one channel) after channel 0, so channels have different numbering
50  * when accessing TCON register.
51  *
52  * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
53  * in its set of bits is 2 as opposed to 3 for other channels.
54  */
55 #define TCON_START(chan)		(1 << (4 * (chan) + 0))
56 #define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
57 #define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
58 #define _TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))
59 #define _TCON_AUTORELOAD4(chan)		(1 << (4 * (chan) + 2))
60 #define TCON_AUTORELOAD(chan)		\
61 	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
62 
63 DEFINE_SPINLOCK(samsung_pwm_lock);
64 EXPORT_SYMBOL(samsung_pwm_lock);
65 
66 struct samsung_pwm_clocksource {
67 	void __iomem *base;
68 	void __iomem *source_reg;
69 	unsigned int irq[SAMSUNG_PWM_NUM];
70 	struct samsung_pwm_variant variant;
71 
72 	struct clk *timerclk;
73 
74 	unsigned int event_id;
75 	unsigned int source_id;
76 	unsigned int tcnt_max;
77 	unsigned int tscaler_div;
78 	unsigned int tdiv;
79 
80 	unsigned long clock_count_per_tick;
81 };
82 
83 static struct samsung_pwm_clocksource pwm;
84 
85 static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
86 {
87 	unsigned long flags;
88 	u8 shift = 0;
89 	u32 reg;
90 
91 	if (channel >= 2)
92 		shift = TCFG0_PRESCALER1_SHIFT;
93 
94 	spin_lock_irqsave(&samsung_pwm_lock, flags);
95 
96 	reg = readl(pwm.base + REG_TCFG0);
97 	reg &= ~(TCFG0_PRESCALER_MASK << shift);
98 	reg |= (prescale - 1) << shift;
99 	writel(reg, pwm.base + REG_TCFG0);
100 
101 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
102 }
103 
104 static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
105 {
106 	u8 shift = TCFG1_SHIFT(channel);
107 	unsigned long flags;
108 	u32 reg;
109 	u8 bits;
110 
111 	bits = (fls(divisor) - 1) - pwm.variant.div_base;
112 
113 	spin_lock_irqsave(&samsung_pwm_lock, flags);
114 
115 	reg = readl(pwm.base + REG_TCFG1);
116 	reg &= ~(TCFG1_MUX_MASK << shift);
117 	reg |= bits << shift;
118 	writel(reg, pwm.base + REG_TCFG1);
119 
120 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
121 }
122 
123 static void samsung_time_stop(unsigned int channel)
124 {
125 	unsigned long tcon;
126 	unsigned long flags;
127 
128 	if (channel > 0)
129 		++channel;
130 
131 	spin_lock_irqsave(&samsung_pwm_lock, flags);
132 
133 	tcon = readl_relaxed(pwm.base + REG_TCON);
134 	tcon &= ~TCON_START(channel);
135 	writel_relaxed(tcon, pwm.base + REG_TCON);
136 
137 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
138 }
139 
140 static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
141 {
142 	unsigned long tcon;
143 	unsigned long flags;
144 	unsigned int tcon_chan = channel;
145 
146 	if (tcon_chan > 0)
147 		++tcon_chan;
148 
149 	spin_lock_irqsave(&samsung_pwm_lock, flags);
150 
151 	tcon = readl_relaxed(pwm.base + REG_TCON);
152 
153 	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
154 	tcon |= TCON_MANUALUPDATE(tcon_chan);
155 
156 	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
157 	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
158 	writel_relaxed(tcon, pwm.base + REG_TCON);
159 
160 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
161 }
162 
163 static void samsung_time_start(unsigned int channel, bool periodic)
164 {
165 	unsigned long tcon;
166 	unsigned long flags;
167 
168 	if (channel > 0)
169 		++channel;
170 
171 	spin_lock_irqsave(&samsung_pwm_lock, flags);
172 
173 	tcon = readl_relaxed(pwm.base + REG_TCON);
174 
175 	tcon &= ~TCON_MANUALUPDATE(channel);
176 	tcon |= TCON_START(channel);
177 
178 	if (periodic)
179 		tcon |= TCON_AUTORELOAD(channel);
180 	else
181 		tcon &= ~TCON_AUTORELOAD(channel);
182 
183 	writel_relaxed(tcon, pwm.base + REG_TCON);
184 
185 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
186 }
187 
188 static int samsung_set_next_event(unsigned long cycles,
189 				struct clock_event_device *evt)
190 {
191 	/*
192 	 * This check is needed to account for internal rounding
193 	 * errors inside clockevents core, which might result in
194 	 * passing cycles = 0, which in turn would not generate any
195 	 * timer interrupt and hang the system.
196 	 *
197 	 * Another solution would be to set up the clockevent device
198 	 * with min_delta = 2, but this would unnecessarily increase
199 	 * the minimum sleep period.
200 	 */
201 	if (!cycles)
202 		cycles = 1;
203 
204 	samsung_time_setup(pwm.event_id, cycles);
205 	samsung_time_start(pwm.event_id, false);
206 
207 	return 0;
208 }
209 
210 static int samsung_shutdown(struct clock_event_device *evt)
211 {
212 	samsung_time_stop(pwm.event_id);
213 	return 0;
214 }
215 
216 static int samsung_set_periodic(struct clock_event_device *evt)
217 {
218 	samsung_time_stop(pwm.event_id);
219 	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
220 	samsung_time_start(pwm.event_id, true);
221 	return 0;
222 }
223 
224 static void samsung_clockevent_resume(struct clock_event_device *cev)
225 {
226 	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
227 	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
228 
229 	if (pwm.variant.has_tint_cstat) {
230 		u32 mask = (1 << pwm.event_id);
231 		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
232 	}
233 }
234 
235 static struct clock_event_device time_event_device = {
236 	.name			= "samsung_event_timer",
237 	.features		= CLOCK_EVT_FEAT_PERIODIC |
238 				  CLOCK_EVT_FEAT_ONESHOT,
239 	.rating			= 200,
240 	.set_next_event		= samsung_set_next_event,
241 	.set_state_shutdown	= samsung_shutdown,
242 	.set_state_periodic	= samsung_set_periodic,
243 	.set_state_oneshot	= samsung_shutdown,
244 	.tick_resume		= samsung_shutdown,
245 	.resume			= samsung_clockevent_resume,
246 };
247 
248 static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
249 {
250 	struct clock_event_device *evt = dev_id;
251 
252 	if (pwm.variant.has_tint_cstat) {
253 		u32 mask = (1 << pwm.event_id);
254 		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
255 	}
256 
257 	evt->event_handler(evt);
258 
259 	return IRQ_HANDLED;
260 }
261 
262 static struct irqaction samsung_clock_event_irq = {
263 	.name		= "samsung_time_irq",
264 	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
265 	.handler	= samsung_clock_event_isr,
266 	.dev_id		= &time_event_device,
267 };
268 
269 static void __init samsung_clockevent_init(void)
270 {
271 	unsigned long pclk;
272 	unsigned long clock_rate;
273 	unsigned int irq_number;
274 
275 	pclk = clk_get_rate(pwm.timerclk);
276 
277 	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
278 	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
279 
280 	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
281 	pwm.clock_count_per_tick = clock_rate / HZ;
282 
283 	time_event_device.cpumask = cpumask_of(0);
284 	clockevents_config_and_register(&time_event_device,
285 						clock_rate, 1, pwm.tcnt_max);
286 
287 	irq_number = pwm.irq[pwm.event_id];
288 	setup_irq(irq_number, &samsung_clock_event_irq);
289 
290 	if (pwm.variant.has_tint_cstat) {
291 		u32 mask = (1 << pwm.event_id);
292 		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
293 	}
294 }
295 
296 static void samsung_clocksource_suspend(struct clocksource *cs)
297 {
298 	samsung_time_stop(pwm.source_id);
299 }
300 
301 static void samsung_clocksource_resume(struct clocksource *cs)
302 {
303 	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
304 	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
305 
306 	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
307 	samsung_time_start(pwm.source_id, true);
308 }
309 
310 static cycle_t notrace samsung_clocksource_read(struct clocksource *c)
311 {
312 	return ~readl_relaxed(pwm.source_reg);
313 }
314 
315 static struct clocksource samsung_clocksource = {
316 	.name		= "samsung_clocksource_timer",
317 	.rating		= 250,
318 	.read		= samsung_clocksource_read,
319 	.suspend	= samsung_clocksource_suspend,
320 	.resume		= samsung_clocksource_resume,
321 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
322 };
323 
324 /*
325  * Override the global weak sched_clock symbol with this
326  * local implementation which uses the clocksource to get some
327  * better resolution when scheduling the kernel. We accept that
328  * this wraps around for now, since it is just a relative time
329  * stamp. (Inspired by U300 implementation.)
330  */
331 static u64 notrace samsung_read_sched_clock(void)
332 {
333 	return samsung_clocksource_read(NULL);
334 }
335 
336 static int __init samsung_clocksource_init(void)
337 {
338 	unsigned long pclk;
339 	unsigned long clock_rate;
340 
341 	pclk = clk_get_rate(pwm.timerclk);
342 
343 	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
344 	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
345 
346 	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
347 
348 	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
349 	samsung_time_start(pwm.source_id, true);
350 
351 	if (pwm.source_id == 4)
352 		pwm.source_reg = pwm.base + 0x40;
353 	else
354 		pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
355 
356 	sched_clock_register(samsung_read_sched_clock,
357 						pwm.variant.bits, clock_rate);
358 
359 	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
360 	return clocksource_register_hz(&samsung_clocksource, clock_rate);
361 }
362 
363 static void __init samsung_timer_resources(void)
364 {
365 	clk_prepare_enable(pwm.timerclk);
366 
367 	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
368 	if (pwm.variant.bits == 16) {
369 		pwm.tscaler_div = 25;
370 		pwm.tdiv = 2;
371 	} else {
372 		pwm.tscaler_div = 2;
373 		pwm.tdiv = 1;
374 	}
375 }
376 
377 /*
378  * PWM master driver
379  */
380 static int __init _samsung_pwm_clocksource_init(void)
381 {
382 	u8 mask;
383 	int channel;
384 
385 	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
386 	channel = fls(mask) - 1;
387 	if (channel < 0) {
388 		pr_crit("failed to find PWM channel for clocksource");
389 		return -EINVAL;
390 	}
391 	pwm.source_id = channel;
392 
393 	mask &= ~(1 << channel);
394 	channel = fls(mask) - 1;
395 	if (channel < 0) {
396 		pr_crit("failed to find PWM channel for clock event");
397 		return -EINVAL;
398 	}
399 	pwm.event_id = channel;
400 
401 	samsung_timer_resources();
402 	samsung_clockevent_init();
403 
404 	return samsung_clocksource_init();
405 }
406 
407 void __init samsung_pwm_clocksource_init(void __iomem *base,
408 			unsigned int *irqs, struct samsung_pwm_variant *variant)
409 {
410 	pwm.base = base;
411 	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
412 	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
413 
414 	pwm.timerclk = clk_get(NULL, "timers");
415 	if (IS_ERR(pwm.timerclk))
416 		panic("failed to get timers clock for timer");
417 
418 	_samsung_pwm_clocksource_init();
419 }
420 
421 #ifdef CONFIG_CLKSRC_OF
422 static int __init samsung_pwm_alloc(struct device_node *np,
423 				    const struct samsung_pwm_variant *variant)
424 {
425 	struct property *prop;
426 	const __be32 *cur;
427 	u32 val;
428 	int i;
429 
430 	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
431 	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
432 		pwm.irq[i] = irq_of_parse_and_map(np, i);
433 
434 	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
435 		if (val >= SAMSUNG_PWM_NUM) {
436 			pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
437 								__func__);
438 			continue;
439 		}
440 		pwm.variant.output_mask |= 1 << val;
441 	}
442 
443 	pwm.base = of_iomap(np, 0);
444 	if (!pwm.base) {
445 		pr_err("%s: failed to map PWM registers\n", __func__);
446 		return -ENXIO;
447 	}
448 
449 	pwm.timerclk = of_clk_get_by_name(np, "timers");
450 	if (IS_ERR(pwm.timerclk)) {
451 		pr_crit("failed to get timers clock for timer");
452 		return PTR_ERR(pwm.timerclk);
453 	}
454 
455 	return _samsung_pwm_clocksource_init();
456 }
457 
458 static const struct samsung_pwm_variant s3c24xx_variant = {
459 	.bits		= 16,
460 	.div_base	= 1,
461 	.has_tint_cstat	= false,
462 	.tclk_mask	= (1 << 4),
463 };
464 
465 static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
466 {
467 	return samsung_pwm_alloc(np, &s3c24xx_variant);
468 }
469 CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
470 
471 static const struct samsung_pwm_variant s3c64xx_variant = {
472 	.bits		= 32,
473 	.div_base	= 0,
474 	.has_tint_cstat	= true,
475 	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
476 };
477 
478 static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
479 {
480 	return samsung_pwm_alloc(np, &s3c64xx_variant);
481 }
482 CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
483 
484 static const struct samsung_pwm_variant s5p64x0_variant = {
485 	.bits		= 32,
486 	.div_base	= 0,
487 	.has_tint_cstat	= true,
488 	.tclk_mask	= 0,
489 };
490 
491 static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
492 {
493 	return samsung_pwm_alloc(np, &s5p64x0_variant);
494 }
495 CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
496 
497 static const struct samsung_pwm_variant s5p_variant = {
498 	.bits		= 32,
499 	.div_base	= 0,
500 	.has_tint_cstat	= true,
501 	.tclk_mask	= (1 << 5),
502 };
503 
504 static int __init s5p_pwm_clocksource_init(struct device_node *np)
505 {
506 	return samsung_pwm_alloc(np, &s5p_variant);
507 }
508 CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
509 #endif
510