1 /* 2 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com/ 4 * 5 * samsung - Common hr-timer support (s3c and s5p) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/err.h> 15 #include <linux/clk.h> 16 #include <linux/clockchips.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/sched_clock.h> 25 26 #include <clocksource/samsung_pwm.h> 27 28 29 /* 30 * Clocksource driver 31 */ 32 33 #define REG_TCFG0 0x00 34 #define REG_TCFG1 0x04 35 #define REG_TCON 0x08 36 #define REG_TINT_CSTAT 0x44 37 38 #define REG_TCNTB(chan) (0x0c + 12 * (chan)) 39 #define REG_TCMPB(chan) (0x10 + 12 * (chan)) 40 41 #define TCFG0_PRESCALER_MASK 0xff 42 #define TCFG0_PRESCALER1_SHIFT 8 43 44 #define TCFG1_SHIFT(x) ((x) * 4) 45 #define TCFG1_MUX_MASK 0xf 46 47 /* 48 * Each channel occupies 4 bits in TCON register, but there is a gap of 4 49 * bits (one channel) after channel 0, so channels have different numbering 50 * when accessing TCON register. 51 * 52 * In addition, the location of autoreload bit for channel 4 (TCON channel 5) 53 * in its set of bits is 2 as opposed to 3 for other channels. 54 */ 55 #define TCON_START(chan) (1 << (4 * (chan) + 0)) 56 #define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1)) 57 #define TCON_INVERT(chan) (1 << (4 * (chan) + 2)) 58 #define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3)) 59 #define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2)) 60 #define TCON_AUTORELOAD(chan) \ 61 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) 62 63 DEFINE_SPINLOCK(samsung_pwm_lock); 64 EXPORT_SYMBOL(samsung_pwm_lock); 65 66 struct samsung_pwm_clocksource { 67 void __iomem *base; 68 void __iomem *source_reg; 69 unsigned int irq[SAMSUNG_PWM_NUM]; 70 struct samsung_pwm_variant variant; 71 72 struct clk *timerclk; 73 74 unsigned int event_id; 75 unsigned int source_id; 76 unsigned int tcnt_max; 77 unsigned int tscaler_div; 78 unsigned int tdiv; 79 80 unsigned long clock_count_per_tick; 81 }; 82 83 static struct samsung_pwm_clocksource pwm; 84 85 static void samsung_timer_set_prescale(unsigned int channel, u16 prescale) 86 { 87 unsigned long flags; 88 u8 shift = 0; 89 u32 reg; 90 91 if (channel >= 2) 92 shift = TCFG0_PRESCALER1_SHIFT; 93 94 spin_lock_irqsave(&samsung_pwm_lock, flags); 95 96 reg = readl(pwm.base + REG_TCFG0); 97 reg &= ~(TCFG0_PRESCALER_MASK << shift); 98 reg |= (prescale - 1) << shift; 99 writel(reg, pwm.base + REG_TCFG0); 100 101 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 102 } 103 104 static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) 105 { 106 u8 shift = TCFG1_SHIFT(channel); 107 unsigned long flags; 108 u32 reg; 109 u8 bits; 110 111 bits = (fls(divisor) - 1) - pwm.variant.div_base; 112 113 spin_lock_irqsave(&samsung_pwm_lock, flags); 114 115 reg = readl(pwm.base + REG_TCFG1); 116 reg &= ~(TCFG1_MUX_MASK << shift); 117 reg |= bits << shift; 118 writel(reg, pwm.base + REG_TCFG1); 119 120 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 121 } 122 123 static void samsung_time_stop(unsigned int channel) 124 { 125 unsigned long tcon; 126 unsigned long flags; 127 128 if (channel > 0) 129 ++channel; 130 131 spin_lock_irqsave(&samsung_pwm_lock, flags); 132 133 tcon = __raw_readl(pwm.base + REG_TCON); 134 tcon &= ~TCON_START(channel); 135 __raw_writel(tcon, pwm.base + REG_TCON); 136 137 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 138 } 139 140 static void samsung_time_setup(unsigned int channel, unsigned long tcnt) 141 { 142 unsigned long tcon; 143 unsigned long flags; 144 unsigned int tcon_chan = channel; 145 146 if (tcon_chan > 0) 147 ++tcon_chan; 148 149 spin_lock_irqsave(&samsung_pwm_lock, flags); 150 151 tcon = __raw_readl(pwm.base + REG_TCON); 152 153 tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); 154 tcon |= TCON_MANUALUPDATE(tcon_chan); 155 156 __raw_writel(tcnt, pwm.base + REG_TCNTB(channel)); 157 __raw_writel(tcnt, pwm.base + REG_TCMPB(channel)); 158 __raw_writel(tcon, pwm.base + REG_TCON); 159 160 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 161 } 162 163 static void samsung_time_start(unsigned int channel, bool periodic) 164 { 165 unsigned long tcon; 166 unsigned long flags; 167 168 if (channel > 0) 169 ++channel; 170 171 spin_lock_irqsave(&samsung_pwm_lock, flags); 172 173 tcon = __raw_readl(pwm.base + REG_TCON); 174 175 tcon &= ~TCON_MANUALUPDATE(channel); 176 tcon |= TCON_START(channel); 177 178 if (periodic) 179 tcon |= TCON_AUTORELOAD(channel); 180 else 181 tcon &= ~TCON_AUTORELOAD(channel); 182 183 __raw_writel(tcon, pwm.base + REG_TCON); 184 185 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 186 } 187 188 static int samsung_set_next_event(unsigned long cycles, 189 struct clock_event_device *evt) 190 { 191 /* 192 * This check is needed to account for internal rounding 193 * errors inside clockevents core, which might result in 194 * passing cycles = 0, which in turn would not generate any 195 * timer interrupt and hang the system. 196 * 197 * Another solution would be to set up the clockevent device 198 * with min_delta = 2, but this would unnecessarily increase 199 * the minimum sleep period. 200 */ 201 if (!cycles) 202 cycles = 1; 203 204 samsung_time_setup(pwm.event_id, cycles); 205 samsung_time_start(pwm.event_id, false); 206 207 return 0; 208 } 209 210 static void samsung_set_mode(enum clock_event_mode mode, 211 struct clock_event_device *evt) 212 { 213 samsung_time_stop(pwm.event_id); 214 215 switch (mode) { 216 case CLOCK_EVT_MODE_PERIODIC: 217 samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1); 218 samsung_time_start(pwm.event_id, true); 219 break; 220 221 case CLOCK_EVT_MODE_ONESHOT: 222 break; 223 224 case CLOCK_EVT_MODE_UNUSED: 225 case CLOCK_EVT_MODE_SHUTDOWN: 226 case CLOCK_EVT_MODE_RESUME: 227 break; 228 } 229 } 230 231 static void samsung_clockevent_resume(struct clock_event_device *cev) 232 { 233 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); 234 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); 235 236 if (pwm.variant.has_tint_cstat) { 237 u32 mask = (1 << pwm.event_id); 238 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); 239 } 240 } 241 242 static struct clock_event_device time_event_device = { 243 .name = "samsung_event_timer", 244 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 245 .rating = 200, 246 .set_next_event = samsung_set_next_event, 247 .set_mode = samsung_set_mode, 248 .resume = samsung_clockevent_resume, 249 }; 250 251 static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) 252 { 253 struct clock_event_device *evt = dev_id; 254 255 if (pwm.variant.has_tint_cstat) { 256 u32 mask = (1 << pwm.event_id); 257 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); 258 } 259 260 evt->event_handler(evt); 261 262 return IRQ_HANDLED; 263 } 264 265 static struct irqaction samsung_clock_event_irq = { 266 .name = "samsung_time_irq", 267 .flags = IRQF_TIMER | IRQF_IRQPOLL, 268 .handler = samsung_clock_event_isr, 269 .dev_id = &time_event_device, 270 }; 271 272 static void __init samsung_clockevent_init(void) 273 { 274 unsigned long pclk; 275 unsigned long clock_rate; 276 unsigned int irq_number; 277 278 pclk = clk_get_rate(pwm.timerclk); 279 280 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); 281 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); 282 283 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); 284 pwm.clock_count_per_tick = clock_rate / HZ; 285 286 time_event_device.cpumask = cpumask_of(0); 287 clockevents_config_and_register(&time_event_device, 288 clock_rate, 1, pwm.tcnt_max); 289 290 irq_number = pwm.irq[pwm.event_id]; 291 setup_irq(irq_number, &samsung_clock_event_irq); 292 293 if (pwm.variant.has_tint_cstat) { 294 u32 mask = (1 << pwm.event_id); 295 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); 296 } 297 } 298 299 static void samsung_clocksource_suspend(struct clocksource *cs) 300 { 301 samsung_time_stop(pwm.source_id); 302 } 303 304 static void samsung_clocksource_resume(struct clocksource *cs) 305 { 306 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); 307 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); 308 309 samsung_time_setup(pwm.source_id, pwm.tcnt_max); 310 samsung_time_start(pwm.source_id, true); 311 } 312 313 static cycle_t samsung_clocksource_read(struct clocksource *c) 314 { 315 return ~readl_relaxed(pwm.source_reg); 316 } 317 318 static struct clocksource samsung_clocksource = { 319 .name = "samsung_clocksource_timer", 320 .rating = 250, 321 .read = samsung_clocksource_read, 322 .suspend = samsung_clocksource_suspend, 323 .resume = samsung_clocksource_resume, 324 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 325 }; 326 327 /* 328 * Override the global weak sched_clock symbol with this 329 * local implementation which uses the clocksource to get some 330 * better resolution when scheduling the kernel. We accept that 331 * this wraps around for now, since it is just a relative time 332 * stamp. (Inspired by U300 implementation.) 333 */ 334 static u64 notrace samsung_read_sched_clock(void) 335 { 336 return samsung_clocksource_read(NULL); 337 } 338 339 static void __init samsung_clocksource_init(void) 340 { 341 unsigned long pclk; 342 unsigned long clock_rate; 343 int ret; 344 345 pclk = clk_get_rate(pwm.timerclk); 346 347 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); 348 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); 349 350 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); 351 352 samsung_time_setup(pwm.source_id, pwm.tcnt_max); 353 samsung_time_start(pwm.source_id, true); 354 355 if (pwm.source_id == 4) 356 pwm.source_reg = pwm.base + 0x40; 357 else 358 pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; 359 360 sched_clock_register(samsung_read_sched_clock, 361 pwm.variant.bits, clock_rate); 362 363 samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits); 364 ret = clocksource_register_hz(&samsung_clocksource, clock_rate); 365 if (ret) 366 panic("samsung_clocksource_timer: can't register clocksource\n"); 367 } 368 369 static void __init samsung_timer_resources(void) 370 { 371 clk_prepare_enable(pwm.timerclk); 372 373 pwm.tcnt_max = (1UL << pwm.variant.bits) - 1; 374 if (pwm.variant.bits == 16) { 375 pwm.tscaler_div = 25; 376 pwm.tdiv = 2; 377 } else { 378 pwm.tscaler_div = 2; 379 pwm.tdiv = 1; 380 } 381 } 382 383 /* 384 * PWM master driver 385 */ 386 static void __init _samsung_pwm_clocksource_init(void) 387 { 388 u8 mask; 389 int channel; 390 391 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); 392 channel = fls(mask) - 1; 393 if (channel < 0) 394 panic("failed to find PWM channel for clocksource"); 395 pwm.source_id = channel; 396 397 mask &= ~(1 << channel); 398 channel = fls(mask) - 1; 399 if (channel < 0) 400 panic("failed to find PWM channel for clock event"); 401 pwm.event_id = channel; 402 403 samsung_timer_resources(); 404 samsung_clockevent_init(); 405 samsung_clocksource_init(); 406 } 407 408 void __init samsung_pwm_clocksource_init(void __iomem *base, 409 unsigned int *irqs, struct samsung_pwm_variant *variant) 410 { 411 pwm.base = base; 412 memcpy(&pwm.variant, variant, sizeof(pwm.variant)); 413 memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs)); 414 415 pwm.timerclk = clk_get(NULL, "timers"); 416 if (IS_ERR(pwm.timerclk)) 417 panic("failed to get timers clock for timer"); 418 419 _samsung_pwm_clocksource_init(); 420 } 421 422 #ifdef CONFIG_CLKSRC_OF 423 static void __init samsung_pwm_alloc(struct device_node *np, 424 const struct samsung_pwm_variant *variant) 425 { 426 struct property *prop; 427 const __be32 *cur; 428 u32 val; 429 int i; 430 431 memcpy(&pwm.variant, variant, sizeof(pwm.variant)); 432 for (i = 0; i < SAMSUNG_PWM_NUM; ++i) 433 pwm.irq[i] = irq_of_parse_and_map(np, i); 434 435 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { 436 if (val >= SAMSUNG_PWM_NUM) { 437 pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n", 438 __func__); 439 continue; 440 } 441 pwm.variant.output_mask |= 1 << val; 442 } 443 444 pwm.base = of_iomap(np, 0); 445 if (!pwm.base) { 446 pr_err("%s: failed to map PWM registers\n", __func__); 447 return; 448 } 449 450 pwm.timerclk = of_clk_get_by_name(np, "timers"); 451 if (IS_ERR(pwm.timerclk)) 452 panic("failed to get timers clock for timer"); 453 454 _samsung_pwm_clocksource_init(); 455 } 456 457 static const struct samsung_pwm_variant s3c24xx_variant = { 458 .bits = 16, 459 .div_base = 1, 460 .has_tint_cstat = false, 461 .tclk_mask = (1 << 4), 462 }; 463 464 static void __init s3c2410_pwm_clocksource_init(struct device_node *np) 465 { 466 samsung_pwm_alloc(np, &s3c24xx_variant); 467 } 468 CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init); 469 470 static const struct samsung_pwm_variant s3c64xx_variant = { 471 .bits = 32, 472 .div_base = 0, 473 .has_tint_cstat = true, 474 .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), 475 }; 476 477 static void __init s3c64xx_pwm_clocksource_init(struct device_node *np) 478 { 479 samsung_pwm_alloc(np, &s3c64xx_variant); 480 } 481 CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init); 482 483 static const struct samsung_pwm_variant s5p64x0_variant = { 484 .bits = 32, 485 .div_base = 0, 486 .has_tint_cstat = true, 487 .tclk_mask = 0, 488 }; 489 490 static void __init s5p64x0_pwm_clocksource_init(struct device_node *np) 491 { 492 samsung_pwm_alloc(np, &s5p64x0_variant); 493 } 494 CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init); 495 496 static const struct samsung_pwm_variant s5p_variant = { 497 .bits = 32, 498 .div_base = 0, 499 .has_tint_cstat = true, 500 .tclk_mask = (1 << 5), 501 }; 502 503 static void __init s5p_pwm_clocksource_init(struct device_node *np) 504 { 505 samsung_pwm_alloc(np, &s5p_variant); 506 } 507 CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init); 508 #endif 509