1 /* 2 * Renesas Timer Support - OSTM 3 * 4 * Copyright (C) 2017 Renesas Electronics America, Inc. 5 * Copyright (C) 2017 Chris Brandt 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/clk.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/sched_clock.h> 24 #include <linux/slab.h> 25 26 /* 27 * The OSTM contains independent channels. 28 * The first OSTM channel probed will be set up as a free running 29 * clocksource. Additionally we will use this clocksource for the system 30 * schedule timer sched_clock(). 31 * 32 * The second (or more) channel probed will be set up as an interrupt 33 * driven clock event. 34 */ 35 36 struct ostm_device { 37 void __iomem *base; 38 unsigned long ticks_per_jiffy; 39 struct clock_event_device ced; 40 }; 41 42 static void __iomem *system_clock; /* For sched_clock() */ 43 44 /* OSTM REGISTERS */ 45 #define OSTM_CMP 0x000 /* RW,32 */ 46 #define OSTM_CNT 0x004 /* R,32 */ 47 #define OSTM_TE 0x010 /* R,8 */ 48 #define OSTM_TS 0x014 /* W,8 */ 49 #define OSTM_TT 0x018 /* W,8 */ 50 #define OSTM_CTL 0x020 /* RW,8 */ 51 52 #define TE 0x01 53 #define TS 0x01 54 #define TT 0x01 55 #define CTL_PERIODIC 0x00 56 #define CTL_ONESHOT 0x02 57 #define CTL_FREERUN 0x02 58 59 static struct ostm_device *ced_to_ostm(struct clock_event_device *ced) 60 { 61 return container_of(ced, struct ostm_device, ced); 62 } 63 64 static void ostm_timer_stop(struct ostm_device *ostm) 65 { 66 if (readb(ostm->base + OSTM_TE) & TE) { 67 writeb(TT, ostm->base + OSTM_TT); 68 69 /* 70 * Read back the register simply to confirm the write operation 71 * has completed since I/O writes can sometimes get queued by 72 * the bus architecture. 73 */ 74 while (readb(ostm->base + OSTM_TE) & TE) 75 ; 76 } 77 } 78 79 static int __init ostm_init_clksrc(struct ostm_device *ostm, unsigned long rate) 80 { 81 /* 82 * irq not used (clock sources don't use interrupts) 83 */ 84 85 ostm_timer_stop(ostm); 86 87 writel(0, ostm->base + OSTM_CMP); 88 writeb(CTL_FREERUN, ostm->base + OSTM_CTL); 89 writeb(TS, ostm->base + OSTM_TS); 90 91 return clocksource_mmio_init(ostm->base + OSTM_CNT, 92 "ostm", rate, 93 300, 32, clocksource_mmio_readl_up); 94 } 95 96 static u64 notrace ostm_read_sched_clock(void) 97 { 98 return readl(system_clock); 99 } 100 101 static void __init ostm_init_sched_clock(struct ostm_device *ostm, 102 unsigned long rate) 103 { 104 system_clock = ostm->base + OSTM_CNT; 105 sched_clock_register(ostm_read_sched_clock, 32, rate); 106 } 107 108 static int ostm_clock_event_next(unsigned long delta, 109 struct clock_event_device *ced) 110 { 111 struct ostm_device *ostm = ced_to_ostm(ced); 112 113 ostm_timer_stop(ostm); 114 115 writel(delta, ostm->base + OSTM_CMP); 116 writeb(CTL_ONESHOT, ostm->base + OSTM_CTL); 117 writeb(TS, ostm->base + OSTM_TS); 118 119 return 0; 120 } 121 122 static int ostm_shutdown(struct clock_event_device *ced) 123 { 124 struct ostm_device *ostm = ced_to_ostm(ced); 125 126 ostm_timer_stop(ostm); 127 128 return 0; 129 } 130 static int ostm_set_periodic(struct clock_event_device *ced) 131 { 132 struct ostm_device *ostm = ced_to_ostm(ced); 133 134 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 135 ostm_timer_stop(ostm); 136 137 writel(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP); 138 writeb(CTL_PERIODIC, ostm->base + OSTM_CTL); 139 writeb(TS, ostm->base + OSTM_TS); 140 141 return 0; 142 } 143 144 static int ostm_set_oneshot(struct clock_event_device *ced) 145 { 146 struct ostm_device *ostm = ced_to_ostm(ced); 147 148 ostm_timer_stop(ostm); 149 150 return 0; 151 } 152 153 static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id) 154 { 155 struct ostm_device *ostm = dev_id; 156 157 if (clockevent_state_oneshot(&ostm->ced)) 158 ostm_timer_stop(ostm); 159 160 /* notify clockevent layer */ 161 if (ostm->ced.event_handler) 162 ostm->ced.event_handler(&ostm->ced); 163 164 return IRQ_HANDLED; 165 } 166 167 static int __init ostm_init_clkevt(struct ostm_device *ostm, int irq, 168 unsigned long rate) 169 { 170 struct clock_event_device *ced = &ostm->ced; 171 int ret = -ENXIO; 172 173 ret = request_irq(irq, ostm_timer_interrupt, 174 IRQF_TIMER | IRQF_IRQPOLL, 175 "ostm", ostm); 176 if (ret) { 177 pr_err("ostm: failed to request irq\n"); 178 return ret; 179 } 180 181 ced->name = "ostm"; 182 ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; 183 ced->set_state_shutdown = ostm_shutdown; 184 ced->set_state_periodic = ostm_set_periodic; 185 ced->set_state_oneshot = ostm_set_oneshot; 186 ced->set_next_event = ostm_clock_event_next; 187 ced->shift = 32; 188 ced->rating = 300; 189 ced->cpumask = cpumask_of(0); 190 clockevents_config_and_register(ced, rate, 0xf, 0xffffffff); 191 192 return 0; 193 } 194 195 static int __init ostm_init(struct device_node *np) 196 { 197 struct ostm_device *ostm; 198 int ret = -EFAULT; 199 struct clk *ostm_clk = NULL; 200 int irq; 201 unsigned long rate; 202 203 ostm = kzalloc(sizeof(*ostm), GFP_KERNEL); 204 if (!ostm) 205 return -ENOMEM; 206 207 ostm->base = of_iomap(np, 0); 208 if (!ostm->base) { 209 pr_err("ostm: failed to remap I/O memory\n"); 210 goto err; 211 } 212 213 irq = irq_of_parse_and_map(np, 0); 214 if (irq < 0) { 215 pr_err("ostm: Failed to get irq\n"); 216 goto err; 217 } 218 219 ostm_clk = of_clk_get(np, 0); 220 if (IS_ERR(ostm_clk)) { 221 pr_err("ostm: Failed to get clock\n"); 222 ostm_clk = NULL; 223 goto err; 224 } 225 226 ret = clk_prepare_enable(ostm_clk); 227 if (ret) { 228 pr_err("ostm: Failed to enable clock\n"); 229 goto err; 230 } 231 232 rate = clk_get_rate(ostm_clk); 233 ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ; 234 235 /* 236 * First probed device will be used as system clocksource. Any 237 * additional devices will be used as clock events. 238 */ 239 if (!system_clock) { 240 ret = ostm_init_clksrc(ostm, rate); 241 242 if (!ret) { 243 ostm_init_sched_clock(ostm, rate); 244 pr_info("ostm: used for clocksource\n"); 245 } 246 247 } else { 248 ret = ostm_init_clkevt(ostm, irq, rate); 249 250 if (!ret) 251 pr_info("ostm: used for clock events\n"); 252 } 253 254 err: 255 if (ret) { 256 clk_disable_unprepare(ostm_clk); 257 iounmap(ostm->base); 258 kfree(ostm); 259 return ret; 260 } 261 262 return 0; 263 } 264 265 TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init); 266