1 /* 2 * Copyright (C) 2000-2001 Deep Blue Solutions 3 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 4 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) 5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 6 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 20 * MA 02110-1301, USA. 21 */ 22 23 #include <linux/err.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/clockchips.h> 27 #include <linux/clk.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/stmp_device.h> 32 #include <linux/sched_clock.h> 33 34 #include <asm/mach/time.h> 35 36 /* 37 * There are 2 versions of the timrot on Freescale MXS-based SoCs. 38 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28 39 * extends the counter to 32 bits. 40 * 41 * The implementation uses two timers, one for clock_event and 42 * another for clocksource. MX28 uses timrot 0 and 1, while MX23 43 * uses 0 and 2. 44 */ 45 46 #define MX23_TIMROT_VERSION_OFFSET 0x0a0 47 #define MX28_TIMROT_VERSION_OFFSET 0x120 48 #define BP_TIMROT_MAJOR_VERSION 24 49 #define BV_TIMROT_VERSION_1 0x01 50 #define BV_TIMROT_VERSION_2 0x02 51 #define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1) 52 53 /* 54 * There are 4 registers for each timrotv2 instance, and 2 registers 55 * for each timrotv1. So address step 0x40 in macros below strides 56 * one instance of timrotv2 while two instances of timrotv1. 57 * 58 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1 59 * on MX28 while timrot2 on MX23. 60 */ 61 /* common between v1 and v2 */ 62 #define HW_TIMROT_ROTCTRL 0x00 63 #define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40) 64 /* v1 only */ 65 #define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40) 66 /* v2 only */ 67 #define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40) 68 #define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40) 69 70 #define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6) 71 #define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7) 72 #define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14) 73 #define BM_TIMROT_TIMCTRLn_IRQ (1 << 15) 74 #define BP_TIMROT_TIMCTRLn_SELECT 0 75 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 76 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb 77 #define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf 78 79 static struct clock_event_device mxs_clockevent_device; 80 81 static void __iomem *mxs_timrot_base; 82 static u32 timrot_major_version; 83 84 static inline void timrot_irq_disable(void) 85 { 86 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + 87 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); 88 } 89 90 static inline void timrot_irq_enable(void) 91 { 92 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + 93 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET); 94 } 95 96 static void timrot_irq_acknowledge(void) 97 { 98 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base + 99 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); 100 } 101 102 static cycle_t timrotv1_get_cycles(struct clocksource *cs) 103 { 104 return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)) 105 & 0xffff0000) >> 16); 106 } 107 108 static int timrotv1_set_next_event(unsigned long evt, 109 struct clock_event_device *dev) 110 { 111 /* timrot decrements the count */ 112 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0)); 113 114 return 0; 115 } 116 117 static int timrotv2_set_next_event(unsigned long evt, 118 struct clock_event_device *dev) 119 { 120 /* timrot decrements the count */ 121 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0)); 122 123 return 0; 124 } 125 126 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id) 127 { 128 struct clock_event_device *evt = dev_id; 129 130 timrot_irq_acknowledge(); 131 evt->event_handler(evt); 132 133 return IRQ_HANDLED; 134 } 135 136 static struct irqaction mxs_timer_irq = { 137 .name = "MXS Timer Tick", 138 .dev_id = &mxs_clockevent_device, 139 .flags = IRQF_TIMER | IRQF_IRQPOLL, 140 .handler = mxs_timer_interrupt, 141 }; 142 143 static void mxs_irq_clear(char *state) 144 { 145 /* Disable interrupt in timer module */ 146 timrot_irq_disable(); 147 148 /* Set event time into the furthest future */ 149 if (timrot_is_v1()) 150 __raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); 151 else 152 __raw_writel(0xffffffff, 153 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1)); 154 155 /* Clear pending interrupt */ 156 timrot_irq_acknowledge(); 157 158 #ifdef DEBUG 159 pr_info("%s: changing mode to %s\n", __func__, state) 160 #endif /* DEBUG */ 161 } 162 163 static int mxs_shutdown(struct clock_event_device *evt) 164 { 165 mxs_irq_clear("shutdown"); 166 167 return 0; 168 } 169 170 static int mxs_set_oneshot(struct clock_event_device *evt) 171 { 172 if (clockevent_state_oneshot(evt)) 173 mxs_irq_clear("oneshot"); 174 timrot_irq_enable(); 175 return 0; 176 } 177 178 static struct clock_event_device mxs_clockevent_device = { 179 .name = "mxs_timrot", 180 .features = CLOCK_EVT_FEAT_ONESHOT, 181 .set_state_shutdown = mxs_shutdown, 182 .set_state_oneshot = mxs_set_oneshot, 183 .tick_resume = mxs_shutdown, 184 .set_next_event = timrotv2_set_next_event, 185 .rating = 200, 186 }; 187 188 static int __init mxs_clockevent_init(struct clk *timer_clk) 189 { 190 if (timrot_is_v1()) 191 mxs_clockevent_device.set_next_event = timrotv1_set_next_event; 192 mxs_clockevent_device.cpumask = cpumask_of(0); 193 clockevents_config_and_register(&mxs_clockevent_device, 194 clk_get_rate(timer_clk), 195 timrot_is_v1() ? 0xf : 0x2, 196 timrot_is_v1() ? 0xfffe : 0xfffffffe); 197 198 return 0; 199 } 200 201 static struct clocksource clocksource_mxs = { 202 .name = "mxs_timer", 203 .rating = 200, 204 .read = timrotv1_get_cycles, 205 .mask = CLOCKSOURCE_MASK(16), 206 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 207 }; 208 209 static u64 notrace mxs_read_sched_clock_v2(void) 210 { 211 return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); 212 } 213 214 static int __init mxs_clocksource_init(struct clk *timer_clk) 215 { 216 unsigned int c = clk_get_rate(timer_clk); 217 218 if (timrot_is_v1()) 219 clocksource_register_hz(&clocksource_mxs, c); 220 else { 221 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), 222 "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); 223 sched_clock_register(mxs_read_sched_clock_v2, 32, c); 224 } 225 226 return 0; 227 } 228 229 static void __init mxs_timer_init(struct device_node *np) 230 { 231 struct clk *timer_clk; 232 int irq; 233 234 mxs_timrot_base = of_iomap(np, 0); 235 WARN_ON(!mxs_timrot_base); 236 237 timer_clk = of_clk_get(np, 0); 238 if (IS_ERR(timer_clk)) { 239 pr_err("%s: failed to get clk\n", __func__); 240 return; 241 } 242 243 clk_prepare_enable(timer_clk); 244 245 /* 246 * Initialize timers to a known state 247 */ 248 stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); 249 250 /* get timrot version */ 251 timrot_major_version = __raw_readl(mxs_timrot_base + 252 (of_device_is_compatible(np, "fsl,imx23-timrot") ? 253 MX23_TIMROT_VERSION_OFFSET : 254 MX28_TIMROT_VERSION_OFFSET)); 255 timrot_major_version >>= BP_TIMROT_MAJOR_VERSION; 256 257 /* one for clock_event */ 258 __raw_writel((timrot_is_v1() ? 259 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : 260 BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) | 261 BM_TIMROT_TIMCTRLn_UPDATE | 262 BM_TIMROT_TIMCTRLn_IRQ_EN, 263 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); 264 265 /* another for clocksource */ 266 __raw_writel((timrot_is_v1() ? 267 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : 268 BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) | 269 BM_TIMROT_TIMCTRLn_RELOAD, 270 mxs_timrot_base + HW_TIMROT_TIMCTRLn(1)); 271 272 /* set clocksource timer fixed count to the maximum */ 273 if (timrot_is_v1()) 274 __raw_writel(0xffff, 275 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); 276 else 277 __raw_writel(0xffffffff, 278 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1)); 279 280 /* init and register the timer to the framework */ 281 mxs_clocksource_init(timer_clk); 282 mxs_clockevent_init(timer_clk); 283 284 /* Make irqs happen */ 285 irq = irq_of_parse_and_map(np, 0); 286 setup_irq(irq, &mxs_timer_irq); 287 } 288 CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init); 289