1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
7  */
8 #include <linux/clk.h>
9 #include <linux/clockchips.h>
10 #include <linux/cpu.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irqchip/mips-gic.h>
14 #include <linux/notifier.h>
15 #include <linux/of_irq.h>
16 #include <linux/percpu.h>
17 #include <linux/smp.h>
18 #include <linux/time.h>
19 
20 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
21 static int gic_timer_irq;
22 static unsigned int gic_frequency;
23 
24 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
25 {
26 	u64 cnt;
27 	int res;
28 
29 	cnt = gic_read_count();
30 	cnt += (u64)delta;
31 	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
32 	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
33 	return res;
34 }
35 
36 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
37 {
38 	struct clock_event_device *cd = dev_id;
39 
40 	gic_write_compare(gic_read_compare());
41 	cd->event_handler(cd);
42 	return IRQ_HANDLED;
43 }
44 
45 struct irqaction gic_compare_irqaction = {
46 	.handler = gic_compare_interrupt,
47 	.percpu_dev_id = &gic_clockevent_device,
48 	.flags = IRQF_PERCPU | IRQF_TIMER,
49 	.name = "timer",
50 };
51 
52 static void gic_clockevent_cpu_init(unsigned int cpu,
53 				    struct clock_event_device *cd)
54 {
55 	cd->name		= "MIPS GIC";
56 	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
57 				  CLOCK_EVT_FEAT_C3STOP;
58 
59 	cd->rating		= 350;
60 	cd->irq			= gic_timer_irq;
61 	cd->cpumask		= cpumask_of(cpu);
62 	cd->set_next_event	= gic_next_event;
63 
64 	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
65 
66 	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
67 }
68 
69 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
70 {
71 	disable_percpu_irq(gic_timer_irq);
72 }
73 
74 static void gic_update_frequency(void *data)
75 {
76 	unsigned long rate = (unsigned long)data;
77 
78 	clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
79 }
80 
81 static int gic_starting_cpu(unsigned int cpu)
82 {
83 	gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
84 	return 0;
85 }
86 
87 static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
88 			    void *data)
89 {
90 	struct clk_notifier_data *cnd = data;
91 
92 	if (action == POST_RATE_CHANGE)
93 		on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
94 
95 	return NOTIFY_OK;
96 }
97 
98 static int gic_dying_cpu(unsigned int cpu)
99 {
100 	gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
101 	return 0;
102 }
103 
104 static struct notifier_block gic_clk_nb = {
105 	.notifier_call = gic_clk_notifier,
106 };
107 
108 static int gic_clockevent_init(void)
109 {
110 	int ret;
111 
112 	if (!gic_frequency)
113 		return -ENXIO;
114 
115 	ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
116 	if (ret < 0) {
117 		pr_err("GIC timer IRQ %d setup failed: %d\n",
118 		       gic_timer_irq, ret);
119 		return ret;
120 	}
121 
122 	cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
123 			  "clockevents/mips/gic/timer:starting",
124 			  gic_starting_cpu, gic_dying_cpu);
125 	return 0;
126 }
127 
128 static u64 gic_hpt_read(struct clocksource *cs)
129 {
130 	return gic_read_count();
131 }
132 
133 static struct clocksource gic_clocksource = {
134 	.name		= "GIC",
135 	.read		= gic_hpt_read,
136 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
137 	.archdata	= { .vdso_clock_mode = VDSO_CLOCK_GIC },
138 };
139 
140 static int __init __gic_clocksource_init(void)
141 {
142 	int ret;
143 
144 	/* Set clocksource mask. */
145 	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
146 
147 	/* Calculate a somewhat reasonable rating value. */
148 	gic_clocksource.rating = 200 + gic_frequency / 10000000;
149 
150 	ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
151 	if (ret < 0)
152 		pr_warn("GIC: Unable to register clocksource\n");
153 
154 	return ret;
155 }
156 
157 void __init gic_clocksource_init(unsigned int frequency)
158 {
159 	gic_frequency = frequency;
160 	gic_timer_irq = MIPS_GIC_IRQ_BASE +
161 		GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
162 
163 	__gic_clocksource_init();
164 	gic_clockevent_init();
165 
166 	/* And finally start the counter */
167 	gic_start_count();
168 }
169 
170 static int __init gic_clocksource_of_init(struct device_node *node)
171 {
172 	struct clk *clk;
173 	int ret;
174 
175 	if (!gic_present || !node->parent ||
176 	    !of_device_is_compatible(node->parent, "mti,gic")) {
177 		pr_warn("No DT definition for the mips gic driver");
178 		return -ENXIO;
179 	}
180 
181 	clk = of_clk_get(node, 0);
182 	if (!IS_ERR(clk)) {
183 		if (clk_prepare_enable(clk) < 0) {
184 			pr_err("GIC failed to enable clock\n");
185 			clk_put(clk);
186 			return PTR_ERR(clk);
187 		}
188 
189 		gic_frequency = clk_get_rate(clk);
190 	} else if (of_property_read_u32(node, "clock-frequency",
191 					&gic_frequency)) {
192 		pr_err("GIC frequency not specified.\n");
193 		return -EINVAL;;
194 	}
195 	gic_timer_irq = irq_of_parse_and_map(node, 0);
196 	if (!gic_timer_irq) {
197 		pr_err("GIC timer IRQ not specified.\n");
198 		return -EINVAL;;
199 	}
200 
201 	ret = __gic_clocksource_init();
202 	if (ret)
203 		return ret;
204 
205 	ret = gic_clockevent_init();
206 	if (!ret && !IS_ERR(clk)) {
207 		if (clk_notifier_register(clk, &gic_clk_nb) < 0)
208 			pr_warn("GIC: Unable to register clock notifier\n");
209 	}
210 
211 	/* And finally start the counter */
212 	gic_start_count();
213 
214 	return 0;
215 }
216 CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
217 		       gic_clocksource_of_init);
218