1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
7  */
8 #include <linux/clk.h>
9 #include <linux/clockchips.h>
10 #include <linux/cpu.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irqchip/mips-gic.h>
14 #include <linux/notifier.h>
15 #include <linux/of_irq.h>
16 #include <linux/percpu.h>
17 #include <linux/smp.h>
18 #include <linux/time.h>
19 
20 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
21 static int gic_timer_irq;
22 static unsigned int gic_frequency;
23 
24 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
25 {
26 	u64 cnt;
27 	int res;
28 
29 	cnt = gic_read_count();
30 	cnt += (u64)delta;
31 	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
32 	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
33 	return res;
34 }
35 
36 static void gic_set_clock_mode(enum clock_event_mode mode,
37 				struct clock_event_device *evt)
38 {
39 	/* Nothing to do ...  */
40 }
41 
42 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
43 {
44 	struct clock_event_device *cd = dev_id;
45 
46 	gic_write_compare(gic_read_compare());
47 	cd->event_handler(cd);
48 	return IRQ_HANDLED;
49 }
50 
51 struct irqaction gic_compare_irqaction = {
52 	.handler = gic_compare_interrupt,
53 	.percpu_dev_id = &gic_clockevent_device,
54 	.flags = IRQF_PERCPU | IRQF_TIMER,
55 	.name = "timer",
56 };
57 
58 static void gic_clockevent_cpu_init(struct clock_event_device *cd)
59 {
60 	unsigned int cpu = smp_processor_id();
61 
62 	cd->name		= "MIPS GIC";
63 	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
64 				  CLOCK_EVT_FEAT_C3STOP;
65 
66 	cd->rating		= 350;
67 	cd->irq			= gic_timer_irq;
68 	cd->cpumask		= cpumask_of(cpu);
69 	cd->set_next_event	= gic_next_event;
70 	cd->set_mode		= gic_set_clock_mode;
71 
72 	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
73 
74 	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
75 }
76 
77 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
78 {
79 	disable_percpu_irq(gic_timer_irq);
80 }
81 
82 static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
83 				void *data)
84 {
85 	switch (action & ~CPU_TASKS_FROZEN) {
86 	case CPU_STARTING:
87 		gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
88 		break;
89 	case CPU_DYING:
90 		gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
91 		break;
92 	}
93 
94 	return NOTIFY_OK;
95 }
96 
97 static struct notifier_block gic_cpu_nb = {
98 	.notifier_call = gic_cpu_notifier,
99 };
100 
101 static int gic_clockevent_init(void)
102 {
103 	if (!cpu_has_counter || !gic_frequency)
104 		return -ENXIO;
105 
106 	setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
107 
108 	register_cpu_notifier(&gic_cpu_nb);
109 
110 	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
111 
112 	return 0;
113 }
114 
115 static cycle_t gic_hpt_read(struct clocksource *cs)
116 {
117 	return gic_read_count();
118 }
119 
120 static struct clocksource gic_clocksource = {
121 	.name	= "GIC",
122 	.read	= gic_hpt_read,
123 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
124 };
125 
126 static void __init __gic_clocksource_init(void)
127 {
128 	/* Set clocksource mask. */
129 	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
130 
131 	/* Calculate a somewhat reasonable rating value. */
132 	gic_clocksource.rating = 200 + gic_frequency / 10000000;
133 
134 	clocksource_register_hz(&gic_clocksource, gic_frequency);
135 
136 	gic_clockevent_init();
137 
138 	/* And finally start the counter */
139 	gic_start_count();
140 }
141 
142 void __init gic_clocksource_init(unsigned int frequency)
143 {
144 	gic_frequency = frequency;
145 	gic_timer_irq = MIPS_GIC_IRQ_BASE +
146 		GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
147 
148 	__gic_clocksource_init();
149 }
150 
151 static void __init gic_clocksource_of_init(struct device_node *node)
152 {
153 	struct clk *clk;
154 
155 	if (WARN_ON(!gic_present || !node->parent ||
156 		    !of_device_is_compatible(node->parent, "mti,gic")))
157 		return;
158 
159 	clk = of_clk_get(node, 0);
160 	if (!IS_ERR(clk)) {
161 		gic_frequency = clk_get_rate(clk);
162 		clk_put(clk);
163 	} else if (of_property_read_u32(node, "clock-frequency",
164 					&gic_frequency)) {
165 		pr_err("GIC frequency not specified.\n");
166 		return;
167 	}
168 	gic_timer_irq = irq_of_parse_and_map(node, 0);
169 	if (!gic_timer_irq) {
170 		pr_err("GIC timer IRQ not specified.\n");
171 		return;
172 	}
173 
174 	__gic_clocksource_init();
175 }
176 CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
177 		       gic_clocksource_of_init);
178