1 // SPDX-License-Identifier: GPL-2.0-only 2 /* linux/arch/arm/mach-exynos4/mct.c 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Exynos4 MCT(Multi-Core Timer) support 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/err.h> 13 #include <linux/clk.h> 14 #include <linux/clockchips.h> 15 #include <linux/cpu.h> 16 #include <linux/delay.h> 17 #include <linux/percpu.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/clocksource.h> 22 #include <linux/sched_clock.h> 23 24 #define EXYNOS4_MCTREG(x) (x) 25 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) 26 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) 27 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) 28 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) 29 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) 30 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) 31 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) 32 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) 33 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) 34 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) 35 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) 36 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) 37 #define EXYNOS4_MCT_L_MASK (0xffffff00) 38 39 #define MCT_L_TCNTB_OFFSET (0x00) 40 #define MCT_L_ICNTB_OFFSET (0x08) 41 #define MCT_L_TCON_OFFSET (0x20) 42 #define MCT_L_INT_CSTAT_OFFSET (0x30) 43 #define MCT_L_INT_ENB_OFFSET (0x34) 44 #define MCT_L_WSTAT_OFFSET (0x40) 45 #define MCT_G_TCON_START (1 << 8) 46 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) 47 #define MCT_G_TCON_COMP0_ENABLE (1 << 0) 48 #define MCT_L_TCON_INTERVAL_MODE (1 << 2) 49 #define MCT_L_TCON_INT_START (1 << 1) 50 #define MCT_L_TCON_TIMER_START (1 << 0) 51 52 #define TICK_BASE_CNT 1 53 54 #ifdef CONFIG_ARM 55 /* Use values higher than ARM arch timer. See 6282edb72bed. */ 56 #define MCT_CLKSOURCE_RATING 450 57 #define MCT_CLKEVENTS_RATING 500 58 #else 59 #define MCT_CLKSOURCE_RATING 350 60 #define MCT_CLKEVENTS_RATING 350 61 #endif 62 63 /* There are four Global timers starting with 0 offset */ 64 #define MCT_G0_IRQ 0 65 /* Local timers count starts after global timer count */ 66 #define MCT_L0_IRQ 4 67 /* Max number of IRQ as per DT binding document */ 68 #define MCT_NR_IRQS 20 69 70 enum { 71 MCT_INT_SPI, 72 MCT_INT_PPI 73 }; 74 75 static void __iomem *reg_base; 76 static unsigned long clk_rate; 77 static unsigned int mct_int_type; 78 static int mct_irqs[MCT_NR_IRQS]; 79 80 struct mct_clock_event_device { 81 struct clock_event_device evt; 82 unsigned long base; 83 /** 84 * The length of the name must be adjusted if number of 85 * local timer interrupts grow over two digits 86 */ 87 char name[11]; 88 }; 89 90 static void exynos4_mct_write(unsigned int value, unsigned long offset) 91 { 92 unsigned long stat_addr; 93 u32 mask; 94 u32 i; 95 96 writel_relaxed(value, reg_base + offset); 97 98 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { 99 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; 100 switch (offset & ~EXYNOS4_MCT_L_MASK) { 101 case MCT_L_TCON_OFFSET: 102 mask = 1 << 3; /* L_TCON write status */ 103 break; 104 case MCT_L_ICNTB_OFFSET: 105 mask = 1 << 1; /* L_ICNTB write status */ 106 break; 107 case MCT_L_TCNTB_OFFSET: 108 mask = 1 << 0; /* L_TCNTB write status */ 109 break; 110 default: 111 return; 112 } 113 } else { 114 switch (offset) { 115 case EXYNOS4_MCT_G_TCON: 116 stat_addr = EXYNOS4_MCT_G_WSTAT; 117 mask = 1 << 16; /* G_TCON write status */ 118 break; 119 case EXYNOS4_MCT_G_COMP0_L: 120 stat_addr = EXYNOS4_MCT_G_WSTAT; 121 mask = 1 << 0; /* G_COMP0_L write status */ 122 break; 123 case EXYNOS4_MCT_G_COMP0_U: 124 stat_addr = EXYNOS4_MCT_G_WSTAT; 125 mask = 1 << 1; /* G_COMP0_U write status */ 126 break; 127 case EXYNOS4_MCT_G_COMP0_ADD_INCR: 128 stat_addr = EXYNOS4_MCT_G_WSTAT; 129 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ 130 break; 131 case EXYNOS4_MCT_G_CNT_L: 132 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 133 mask = 1 << 0; /* G_CNT_L write status */ 134 break; 135 case EXYNOS4_MCT_G_CNT_U: 136 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 137 mask = 1 << 1; /* G_CNT_U write status */ 138 break; 139 default: 140 return; 141 } 142 } 143 144 /* Wait maximum 1 ms until written values are applied */ 145 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) 146 if (readl_relaxed(reg_base + stat_addr) & mask) { 147 writel_relaxed(mask, reg_base + stat_addr); 148 return; 149 } 150 151 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); 152 } 153 154 /* Clocksource handling */ 155 static void exynos4_mct_frc_start(void) 156 { 157 u32 reg; 158 159 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 160 reg |= MCT_G_TCON_START; 161 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); 162 } 163 164 /** 165 * exynos4_read_count_64 - Read all 64-bits of the global counter 166 * 167 * This will read all 64-bits of the global counter taking care to make sure 168 * that the upper and lower half match. Note that reading the MCT can be quite 169 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half 170 * only) version when possible. 171 * 172 * Returns the number of cycles in the global counter. 173 */ 174 static u64 exynos4_read_count_64(void) 175 { 176 unsigned int lo, hi; 177 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 178 179 do { 180 hi = hi2; 181 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 182 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 183 } while (hi != hi2); 184 185 return ((u64)hi << 32) | lo; 186 } 187 188 /** 189 * exynos4_read_count_32 - Read the lower 32-bits of the global counter 190 * 191 * This will read just the lower 32-bits of the global counter. This is marked 192 * as notrace so it can be used by the scheduler clock. 193 * 194 * Returns the number of cycles in the global counter (lower 32 bits). 195 */ 196 static u32 notrace exynos4_read_count_32(void) 197 { 198 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 199 } 200 201 static u64 exynos4_frc_read(struct clocksource *cs) 202 { 203 return exynos4_read_count_32(); 204 } 205 206 static void exynos4_frc_resume(struct clocksource *cs) 207 { 208 exynos4_mct_frc_start(); 209 } 210 211 static struct clocksource mct_frc = { 212 .name = "mct-frc", 213 .rating = MCT_CLKSOURCE_RATING, 214 .read = exynos4_frc_read, 215 .mask = CLOCKSOURCE_MASK(32), 216 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 217 .resume = exynos4_frc_resume, 218 }; 219 220 static u64 notrace exynos4_read_sched_clock(void) 221 { 222 return exynos4_read_count_32(); 223 } 224 225 #if defined(CONFIG_ARM) 226 static struct delay_timer exynos4_delay_timer; 227 228 static cycles_t exynos4_read_current_timer(void) 229 { 230 BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32), 231 "cycles_t needs to move to 32-bit for ARM64 usage"); 232 return exynos4_read_count_32(); 233 } 234 #endif 235 236 static int __init exynos4_clocksource_init(bool frc_shared) 237 { 238 /* 239 * When the frc is shared, the main processer should have already 240 * turned it on and we shouldn't be writing to TCON. 241 */ 242 if (frc_shared) 243 mct_frc.resume = NULL; 244 else 245 exynos4_mct_frc_start(); 246 247 #if defined(CONFIG_ARM) 248 exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; 249 exynos4_delay_timer.freq = clk_rate; 250 register_current_timer_delay(&exynos4_delay_timer); 251 #endif 252 253 if (clocksource_register_hz(&mct_frc, clk_rate)) 254 panic("%s: can't register clocksource\n", mct_frc.name); 255 256 sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); 257 258 return 0; 259 } 260 261 static void exynos4_mct_comp0_stop(void) 262 { 263 unsigned int tcon; 264 265 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 266 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); 267 268 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); 269 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); 270 } 271 272 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) 273 { 274 unsigned int tcon; 275 u64 comp_cycle; 276 277 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 278 279 if (periodic) { 280 tcon |= MCT_G_TCON_COMP0_AUTO_INC; 281 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); 282 } 283 284 comp_cycle = exynos4_read_count_64() + cycles; 285 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); 286 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); 287 288 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); 289 290 tcon |= MCT_G_TCON_COMP0_ENABLE; 291 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); 292 } 293 294 static int exynos4_comp_set_next_event(unsigned long cycles, 295 struct clock_event_device *evt) 296 { 297 exynos4_mct_comp0_start(false, cycles); 298 299 return 0; 300 } 301 302 static int mct_set_state_shutdown(struct clock_event_device *evt) 303 { 304 exynos4_mct_comp0_stop(); 305 return 0; 306 } 307 308 static int mct_set_state_periodic(struct clock_event_device *evt) 309 { 310 unsigned long cycles_per_jiffy; 311 312 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) 313 >> evt->shift); 314 exynos4_mct_comp0_stop(); 315 exynos4_mct_comp0_start(true, cycles_per_jiffy); 316 return 0; 317 } 318 319 static struct clock_event_device mct_comp_device = { 320 .name = "mct-comp", 321 .features = CLOCK_EVT_FEAT_PERIODIC | 322 CLOCK_EVT_FEAT_ONESHOT, 323 .rating = 250, 324 .set_next_event = exynos4_comp_set_next_event, 325 .set_state_periodic = mct_set_state_periodic, 326 .set_state_shutdown = mct_set_state_shutdown, 327 .set_state_oneshot = mct_set_state_shutdown, 328 .set_state_oneshot_stopped = mct_set_state_shutdown, 329 .tick_resume = mct_set_state_shutdown, 330 }; 331 332 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) 333 { 334 struct clock_event_device *evt = dev_id; 335 336 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); 337 338 evt->event_handler(evt); 339 340 return IRQ_HANDLED; 341 } 342 343 static int exynos4_clockevent_init(void) 344 { 345 mct_comp_device.cpumask = cpumask_of(0); 346 clockevents_config_and_register(&mct_comp_device, clk_rate, 347 0xf, 0xffffffff); 348 if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr, 349 IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq", 350 &mct_comp_device)) 351 pr_err("%s: request_irq() failed\n", "mct_comp_irq"); 352 353 return 0; 354 } 355 356 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); 357 358 /* Clock event handling */ 359 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) 360 { 361 unsigned long tmp; 362 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; 363 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; 364 365 tmp = readl_relaxed(reg_base + offset); 366 if (tmp & mask) { 367 tmp &= ~mask; 368 exynos4_mct_write(tmp, offset); 369 } 370 } 371 372 static void exynos4_mct_tick_start(unsigned long cycles, 373 struct mct_clock_event_device *mevt) 374 { 375 unsigned long tmp; 376 377 exynos4_mct_tick_stop(mevt); 378 379 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ 380 381 /* update interrupt count buffer */ 382 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); 383 384 /* enable MCT tick interrupt */ 385 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); 386 387 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); 388 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | 389 MCT_L_TCON_INTERVAL_MODE; 390 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); 391 } 392 393 static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) 394 { 395 /* Clear the MCT tick interrupt */ 396 if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) 397 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 398 } 399 400 static int exynos4_tick_set_next_event(unsigned long cycles, 401 struct clock_event_device *evt) 402 { 403 struct mct_clock_event_device *mevt; 404 405 mevt = container_of(evt, struct mct_clock_event_device, evt); 406 exynos4_mct_tick_start(cycles, mevt); 407 return 0; 408 } 409 410 static int set_state_shutdown(struct clock_event_device *evt) 411 { 412 struct mct_clock_event_device *mevt; 413 414 mevt = container_of(evt, struct mct_clock_event_device, evt); 415 exynos4_mct_tick_stop(mevt); 416 exynos4_mct_tick_clear(mevt); 417 return 0; 418 } 419 420 static int set_state_periodic(struct clock_event_device *evt) 421 { 422 struct mct_clock_event_device *mevt; 423 unsigned long cycles_per_jiffy; 424 425 mevt = container_of(evt, struct mct_clock_event_device, evt); 426 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) 427 >> evt->shift); 428 exynos4_mct_tick_stop(mevt); 429 exynos4_mct_tick_start(cycles_per_jiffy, mevt); 430 return 0; 431 } 432 433 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) 434 { 435 struct mct_clock_event_device *mevt = dev_id; 436 struct clock_event_device *evt = &mevt->evt; 437 438 /* 439 * This is for supporting oneshot mode. 440 * Mct would generate interrupt periodically 441 * without explicit stopping. 442 */ 443 if (!clockevent_state_periodic(&mevt->evt)) 444 exynos4_mct_tick_stop(mevt); 445 446 exynos4_mct_tick_clear(mevt); 447 448 evt->event_handler(evt); 449 450 return IRQ_HANDLED; 451 } 452 453 static int exynos4_mct_starting_cpu(unsigned int cpu) 454 { 455 struct mct_clock_event_device *mevt = 456 per_cpu_ptr(&percpu_mct_tick, cpu); 457 struct clock_event_device *evt = &mevt->evt; 458 459 mevt->base = EXYNOS4_MCT_L_BASE(cpu); 460 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); 461 462 evt->name = mevt->name; 463 evt->cpumask = cpumask_of(cpu); 464 evt->set_next_event = exynos4_tick_set_next_event; 465 evt->set_state_periodic = set_state_periodic; 466 evt->set_state_shutdown = set_state_shutdown; 467 evt->set_state_oneshot = set_state_shutdown; 468 evt->set_state_oneshot_stopped = set_state_shutdown; 469 evt->tick_resume = set_state_shutdown; 470 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | 471 CLOCK_EVT_FEAT_PERCPU; 472 evt->rating = MCT_CLKEVENTS_RATING; 473 474 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 475 476 if (mct_int_type == MCT_INT_SPI) { 477 478 if (evt->irq == -1) 479 return -EIO; 480 481 irq_force_affinity(evt->irq, cpumask_of(cpu)); 482 enable_irq(evt->irq); 483 } else { 484 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); 485 } 486 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), 487 0xf, 0x7fffffff); 488 489 return 0; 490 } 491 492 static int exynos4_mct_dying_cpu(unsigned int cpu) 493 { 494 struct mct_clock_event_device *mevt = 495 per_cpu_ptr(&percpu_mct_tick, cpu); 496 struct clock_event_device *evt = &mevt->evt; 497 498 evt->set_state_shutdown(evt); 499 if (mct_int_type == MCT_INT_SPI) { 500 if (evt->irq != -1) 501 disable_irq_nosync(evt->irq); 502 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 503 } else { 504 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); 505 } 506 return 0; 507 } 508 509 static int __init exynos4_timer_resources(struct device_node *np) 510 { 511 struct clk *mct_clk, *tick_clk; 512 513 reg_base = of_iomap(np, 0); 514 if (!reg_base) 515 panic("%s: unable to ioremap mct address space\n", __func__); 516 517 tick_clk = of_clk_get_by_name(np, "fin_pll"); 518 if (IS_ERR(tick_clk)) 519 panic("%s: unable to determine tick clock rate\n", __func__); 520 clk_rate = clk_get_rate(tick_clk); 521 522 mct_clk = of_clk_get_by_name(np, "mct"); 523 if (IS_ERR(mct_clk)) 524 panic("%s: unable to retrieve mct clock instance\n", __func__); 525 clk_prepare_enable(mct_clk); 526 527 return 0; 528 } 529 530 static int __init exynos4_timer_interrupts(struct device_node *np, 531 unsigned int int_type) 532 { 533 int nr_irqs, i, err, cpu; 534 535 mct_int_type = int_type; 536 537 /* This driver uses only one global timer interrupt */ 538 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); 539 540 /* 541 * Find out the number of local irqs specified. The local 542 * timer irqs are specified after the four global timer 543 * irqs are specified. 544 */ 545 nr_irqs = of_irq_count(np); 546 if (nr_irqs > ARRAY_SIZE(mct_irqs)) { 547 pr_err("exynos-mct: too many (%d) interrupts configured in DT\n", 548 nr_irqs); 549 nr_irqs = ARRAY_SIZE(mct_irqs); 550 } 551 for (i = MCT_L0_IRQ; i < nr_irqs; i++) 552 mct_irqs[i] = irq_of_parse_and_map(np, i); 553 554 if (mct_int_type == MCT_INT_PPI) { 555 556 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], 557 exynos4_mct_tick_isr, "MCT", 558 &percpu_mct_tick); 559 WARN(err, "MCT: can't request IRQ %d (%d)\n", 560 mct_irqs[MCT_L0_IRQ], err); 561 } else { 562 for_each_possible_cpu(cpu) { 563 int mct_irq; 564 struct mct_clock_event_device *pcpu_mevt = 565 per_cpu_ptr(&percpu_mct_tick, cpu); 566 567 pcpu_mevt->evt.irq = -1; 568 if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs)) 569 break; 570 mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; 571 572 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); 573 if (request_irq(mct_irq, 574 exynos4_mct_tick_isr, 575 IRQF_TIMER | IRQF_NOBALANCING, 576 pcpu_mevt->name, pcpu_mevt)) { 577 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", 578 cpu); 579 580 continue; 581 } 582 pcpu_mevt->evt.irq = mct_irq; 583 } 584 } 585 586 /* Install hotplug callbacks which configure the timer on this CPU */ 587 err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, 588 "clockevents/exynos4/mct_timer:starting", 589 exynos4_mct_starting_cpu, 590 exynos4_mct_dying_cpu); 591 if (err) 592 goto out_irq; 593 594 return 0; 595 596 out_irq: 597 if (mct_int_type == MCT_INT_PPI) { 598 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); 599 } else { 600 for_each_possible_cpu(cpu) { 601 struct mct_clock_event_device *pcpu_mevt = 602 per_cpu_ptr(&percpu_mct_tick, cpu); 603 604 if (pcpu_mevt->evt.irq != -1) { 605 free_irq(pcpu_mevt->evt.irq, pcpu_mevt); 606 pcpu_mevt->evt.irq = -1; 607 } 608 } 609 } 610 return err; 611 } 612 613 static int __init mct_init_dt(struct device_node *np, unsigned int int_type) 614 { 615 bool frc_shared = of_property_read_bool(np, "samsung,frc-shared"); 616 int ret; 617 618 ret = exynos4_timer_resources(np); 619 if (ret) 620 return ret; 621 622 ret = exynos4_timer_interrupts(np, int_type); 623 if (ret) 624 return ret; 625 626 ret = exynos4_clocksource_init(frc_shared); 627 if (ret) 628 return ret; 629 630 /* 631 * When the FRC is shared with a main processor, this secondary 632 * processor cannot use the global comparator. 633 */ 634 if (frc_shared) 635 return ret; 636 637 return exynos4_clockevent_init(); 638 } 639 640 641 static int __init mct_init_spi(struct device_node *np) 642 { 643 return mct_init_dt(np, MCT_INT_SPI); 644 } 645 646 static int __init mct_init_ppi(struct device_node *np) 647 { 648 return mct_init_dt(np, MCT_INT_PPI); 649 } 650 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); 651 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); 652