1 /* linux/arch/arm/mach-exynos4/mct.c 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * EXYNOS4 MCT(Multi-Core Timer) support 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/clockchips.h> 19 #include <linux/cpu.h> 20 #include <linux/platform_device.h> 21 #include <linux/delay.h> 22 #include <linux/percpu.h> 23 #include <linux/of.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_address.h> 26 #include <linux/clocksource.h> 27 #include <linux/sched_clock.h> 28 29 #define EXYNOS4_MCTREG(x) (x) 30 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) 31 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) 32 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) 33 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) 34 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) 35 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) 36 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) 37 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) 38 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) 39 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) 40 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) 41 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) 42 #define EXYNOS4_MCT_L_MASK (0xffffff00) 43 44 #define MCT_L_TCNTB_OFFSET (0x00) 45 #define MCT_L_ICNTB_OFFSET (0x08) 46 #define MCT_L_TCON_OFFSET (0x20) 47 #define MCT_L_INT_CSTAT_OFFSET (0x30) 48 #define MCT_L_INT_ENB_OFFSET (0x34) 49 #define MCT_L_WSTAT_OFFSET (0x40) 50 #define MCT_G_TCON_START (1 << 8) 51 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) 52 #define MCT_G_TCON_COMP0_ENABLE (1 << 0) 53 #define MCT_L_TCON_INTERVAL_MODE (1 << 2) 54 #define MCT_L_TCON_INT_START (1 << 1) 55 #define MCT_L_TCON_TIMER_START (1 << 0) 56 57 #define TICK_BASE_CNT 1 58 59 enum { 60 MCT_INT_SPI, 61 MCT_INT_PPI 62 }; 63 64 enum { 65 MCT_G0_IRQ, 66 MCT_G1_IRQ, 67 MCT_G2_IRQ, 68 MCT_G3_IRQ, 69 MCT_L0_IRQ, 70 MCT_L1_IRQ, 71 MCT_L2_IRQ, 72 MCT_L3_IRQ, 73 MCT_L4_IRQ, 74 MCT_L5_IRQ, 75 MCT_L6_IRQ, 76 MCT_L7_IRQ, 77 MCT_NR_IRQS, 78 }; 79 80 static void __iomem *reg_base; 81 static unsigned long clk_rate; 82 static unsigned int mct_int_type; 83 static int mct_irqs[MCT_NR_IRQS]; 84 85 struct mct_clock_event_device { 86 struct clock_event_device evt; 87 unsigned long base; 88 char name[10]; 89 }; 90 91 static void exynos4_mct_write(unsigned int value, unsigned long offset) 92 { 93 unsigned long stat_addr; 94 u32 mask; 95 u32 i; 96 97 writel_relaxed(value, reg_base + offset); 98 99 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { 100 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; 101 switch (offset & ~EXYNOS4_MCT_L_MASK) { 102 case MCT_L_TCON_OFFSET: 103 mask = 1 << 3; /* L_TCON write status */ 104 break; 105 case MCT_L_ICNTB_OFFSET: 106 mask = 1 << 1; /* L_ICNTB write status */ 107 break; 108 case MCT_L_TCNTB_OFFSET: 109 mask = 1 << 0; /* L_TCNTB write status */ 110 break; 111 default: 112 return; 113 } 114 } else { 115 switch (offset) { 116 case EXYNOS4_MCT_G_TCON: 117 stat_addr = EXYNOS4_MCT_G_WSTAT; 118 mask = 1 << 16; /* G_TCON write status */ 119 break; 120 case EXYNOS4_MCT_G_COMP0_L: 121 stat_addr = EXYNOS4_MCT_G_WSTAT; 122 mask = 1 << 0; /* G_COMP0_L write status */ 123 break; 124 case EXYNOS4_MCT_G_COMP0_U: 125 stat_addr = EXYNOS4_MCT_G_WSTAT; 126 mask = 1 << 1; /* G_COMP0_U write status */ 127 break; 128 case EXYNOS4_MCT_G_COMP0_ADD_INCR: 129 stat_addr = EXYNOS4_MCT_G_WSTAT; 130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ 131 break; 132 case EXYNOS4_MCT_G_CNT_L: 133 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 134 mask = 1 << 0; /* G_CNT_L write status */ 135 break; 136 case EXYNOS4_MCT_G_CNT_U: 137 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 138 mask = 1 << 1; /* G_CNT_U write status */ 139 break; 140 default: 141 return; 142 } 143 } 144 145 /* Wait maximum 1 ms until written values are applied */ 146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) 147 if (readl_relaxed(reg_base + stat_addr) & mask) { 148 writel_relaxed(mask, reg_base + stat_addr); 149 return; 150 } 151 152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); 153 } 154 155 /* Clocksource handling */ 156 static void exynos4_mct_frc_start(void) 157 { 158 u32 reg; 159 160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 161 reg |= MCT_G_TCON_START; 162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); 163 } 164 165 /** 166 * exynos4_read_count_64 - Read all 64-bits of the global counter 167 * 168 * This will read all 64-bits of the global counter taking care to make sure 169 * that the upper and lower half match. Note that reading the MCT can be quite 170 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half 171 * only) version when possible. 172 * 173 * Returns the number of cycles in the global counter. 174 */ 175 static u64 exynos4_read_count_64(void) 176 { 177 unsigned int lo, hi; 178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 179 180 do { 181 hi = hi2; 182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 184 } while (hi != hi2); 185 186 return ((u64)hi << 32) | lo; 187 } 188 189 /** 190 * exynos4_read_count_32 - Read the lower 32-bits of the global counter 191 * 192 * This will read just the lower 32-bits of the global counter. This is marked 193 * as notrace so it can be used by the scheduler clock. 194 * 195 * Returns the number of cycles in the global counter (lower 32 bits). 196 */ 197 static u32 notrace exynos4_read_count_32(void) 198 { 199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 200 } 201 202 static u64 exynos4_frc_read(struct clocksource *cs) 203 { 204 return exynos4_read_count_32(); 205 } 206 207 static void exynos4_frc_resume(struct clocksource *cs) 208 { 209 exynos4_mct_frc_start(); 210 } 211 212 static struct clocksource mct_frc = { 213 .name = "mct-frc", 214 .rating = 400, 215 .read = exynos4_frc_read, 216 .mask = CLOCKSOURCE_MASK(32), 217 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 218 .resume = exynos4_frc_resume, 219 }; 220 221 static u64 notrace exynos4_read_sched_clock(void) 222 { 223 return exynos4_read_count_32(); 224 } 225 226 #if defined(CONFIG_ARM) 227 static struct delay_timer exynos4_delay_timer; 228 229 static cycles_t exynos4_read_current_timer(void) 230 { 231 BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32), 232 "cycles_t needs to move to 32-bit for ARM64 usage"); 233 return exynos4_read_count_32(); 234 } 235 #endif 236 237 static int __init exynos4_clocksource_init(void) 238 { 239 exynos4_mct_frc_start(); 240 241 #if defined(CONFIG_ARM) 242 exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; 243 exynos4_delay_timer.freq = clk_rate; 244 register_current_timer_delay(&exynos4_delay_timer); 245 #endif 246 247 if (clocksource_register_hz(&mct_frc, clk_rate)) 248 panic("%s: can't register clocksource\n", mct_frc.name); 249 250 sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); 251 252 return 0; 253 } 254 255 static void exynos4_mct_comp0_stop(void) 256 { 257 unsigned int tcon; 258 259 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 260 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); 261 262 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); 263 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); 264 } 265 266 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) 267 { 268 unsigned int tcon; 269 u64 comp_cycle; 270 271 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 272 273 if (periodic) { 274 tcon |= MCT_G_TCON_COMP0_AUTO_INC; 275 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); 276 } 277 278 comp_cycle = exynos4_read_count_64() + cycles; 279 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); 280 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); 281 282 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); 283 284 tcon |= MCT_G_TCON_COMP0_ENABLE; 285 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); 286 } 287 288 static int exynos4_comp_set_next_event(unsigned long cycles, 289 struct clock_event_device *evt) 290 { 291 exynos4_mct_comp0_start(false, cycles); 292 293 return 0; 294 } 295 296 static int mct_set_state_shutdown(struct clock_event_device *evt) 297 { 298 exynos4_mct_comp0_stop(); 299 return 0; 300 } 301 302 static int mct_set_state_periodic(struct clock_event_device *evt) 303 { 304 unsigned long cycles_per_jiffy; 305 306 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) 307 >> evt->shift); 308 exynos4_mct_comp0_stop(); 309 exynos4_mct_comp0_start(true, cycles_per_jiffy); 310 return 0; 311 } 312 313 static struct clock_event_device mct_comp_device = { 314 .name = "mct-comp", 315 .features = CLOCK_EVT_FEAT_PERIODIC | 316 CLOCK_EVT_FEAT_ONESHOT, 317 .rating = 250, 318 .set_next_event = exynos4_comp_set_next_event, 319 .set_state_periodic = mct_set_state_periodic, 320 .set_state_shutdown = mct_set_state_shutdown, 321 .set_state_oneshot = mct_set_state_shutdown, 322 .set_state_oneshot_stopped = mct_set_state_shutdown, 323 .tick_resume = mct_set_state_shutdown, 324 }; 325 326 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) 327 { 328 struct clock_event_device *evt = dev_id; 329 330 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); 331 332 evt->event_handler(evt); 333 334 return IRQ_HANDLED; 335 } 336 337 static struct irqaction mct_comp_event_irq = { 338 .name = "mct_comp_irq", 339 .flags = IRQF_TIMER | IRQF_IRQPOLL, 340 .handler = exynos4_mct_comp_isr, 341 .dev_id = &mct_comp_device, 342 }; 343 344 static int exynos4_clockevent_init(void) 345 { 346 mct_comp_device.cpumask = cpumask_of(0); 347 clockevents_config_and_register(&mct_comp_device, clk_rate, 348 0xf, 0xffffffff); 349 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); 350 351 return 0; 352 } 353 354 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); 355 356 /* Clock event handling */ 357 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) 358 { 359 unsigned long tmp; 360 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; 361 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; 362 363 tmp = readl_relaxed(reg_base + offset); 364 if (tmp & mask) { 365 tmp &= ~mask; 366 exynos4_mct_write(tmp, offset); 367 } 368 } 369 370 static void exynos4_mct_tick_start(unsigned long cycles, 371 struct mct_clock_event_device *mevt) 372 { 373 unsigned long tmp; 374 375 exynos4_mct_tick_stop(mevt); 376 377 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ 378 379 /* update interrupt count buffer */ 380 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); 381 382 /* enable MCT tick interrupt */ 383 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); 384 385 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); 386 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | 387 MCT_L_TCON_INTERVAL_MODE; 388 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); 389 } 390 391 static int exynos4_tick_set_next_event(unsigned long cycles, 392 struct clock_event_device *evt) 393 { 394 struct mct_clock_event_device *mevt; 395 396 mevt = container_of(evt, struct mct_clock_event_device, evt); 397 exynos4_mct_tick_start(cycles, mevt); 398 return 0; 399 } 400 401 static int set_state_shutdown(struct clock_event_device *evt) 402 { 403 struct mct_clock_event_device *mevt; 404 405 mevt = container_of(evt, struct mct_clock_event_device, evt); 406 exynos4_mct_tick_stop(mevt); 407 return 0; 408 } 409 410 static int set_state_periodic(struct clock_event_device *evt) 411 { 412 struct mct_clock_event_device *mevt; 413 unsigned long cycles_per_jiffy; 414 415 mevt = container_of(evt, struct mct_clock_event_device, evt); 416 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) 417 >> evt->shift); 418 exynos4_mct_tick_stop(mevt); 419 exynos4_mct_tick_start(cycles_per_jiffy, mevt); 420 return 0; 421 } 422 423 static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) 424 { 425 /* 426 * This is for supporting oneshot mode. 427 * Mct would generate interrupt periodically 428 * without explicit stopping. 429 */ 430 if (!clockevent_state_periodic(&mevt->evt)) 431 exynos4_mct_tick_stop(mevt); 432 433 /* Clear the MCT tick interrupt */ 434 if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) 435 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 436 } 437 438 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) 439 { 440 struct mct_clock_event_device *mevt = dev_id; 441 struct clock_event_device *evt = &mevt->evt; 442 443 exynos4_mct_tick_clear(mevt); 444 445 evt->event_handler(evt); 446 447 return IRQ_HANDLED; 448 } 449 450 static int exynos4_mct_starting_cpu(unsigned int cpu) 451 { 452 struct mct_clock_event_device *mevt = 453 per_cpu_ptr(&percpu_mct_tick, cpu); 454 struct clock_event_device *evt = &mevt->evt; 455 456 mevt->base = EXYNOS4_MCT_L_BASE(cpu); 457 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); 458 459 evt->name = mevt->name; 460 evt->cpumask = cpumask_of(cpu); 461 evt->set_next_event = exynos4_tick_set_next_event; 462 evt->set_state_periodic = set_state_periodic; 463 evt->set_state_shutdown = set_state_shutdown; 464 evt->set_state_oneshot = set_state_shutdown; 465 evt->set_state_oneshot_stopped = set_state_shutdown; 466 evt->tick_resume = set_state_shutdown; 467 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 468 evt->rating = 450; 469 470 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 471 472 if (mct_int_type == MCT_INT_SPI) { 473 474 if (evt->irq == -1) 475 return -EIO; 476 477 irq_force_affinity(evt->irq, cpumask_of(cpu)); 478 enable_irq(evt->irq); 479 } else { 480 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); 481 } 482 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), 483 0xf, 0x7fffffff); 484 485 return 0; 486 } 487 488 static int exynos4_mct_dying_cpu(unsigned int cpu) 489 { 490 struct mct_clock_event_device *mevt = 491 per_cpu_ptr(&percpu_mct_tick, cpu); 492 struct clock_event_device *evt = &mevt->evt; 493 494 evt->set_state_shutdown(evt); 495 if (mct_int_type == MCT_INT_SPI) { 496 if (evt->irq != -1) 497 disable_irq_nosync(evt->irq); 498 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 499 } else { 500 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); 501 } 502 return 0; 503 } 504 505 static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base) 506 { 507 int err, cpu; 508 struct clk *mct_clk, *tick_clk; 509 510 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : 511 clk_get(NULL, "fin_pll"); 512 if (IS_ERR(tick_clk)) 513 panic("%s: unable to determine tick clock rate\n", __func__); 514 clk_rate = clk_get_rate(tick_clk); 515 516 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); 517 if (IS_ERR(mct_clk)) 518 panic("%s: unable to retrieve mct clock instance\n", __func__); 519 clk_prepare_enable(mct_clk); 520 521 reg_base = base; 522 if (!reg_base) 523 panic("%s: unable to ioremap mct address space\n", __func__); 524 525 if (mct_int_type == MCT_INT_PPI) { 526 527 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], 528 exynos4_mct_tick_isr, "MCT", 529 &percpu_mct_tick); 530 WARN(err, "MCT: can't request IRQ %d (%d)\n", 531 mct_irqs[MCT_L0_IRQ], err); 532 } else { 533 for_each_possible_cpu(cpu) { 534 int mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; 535 struct mct_clock_event_device *pcpu_mevt = 536 per_cpu_ptr(&percpu_mct_tick, cpu); 537 538 pcpu_mevt->evt.irq = -1; 539 540 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); 541 if (request_irq(mct_irq, 542 exynos4_mct_tick_isr, 543 IRQF_TIMER | IRQF_NOBALANCING, 544 pcpu_mevt->name, pcpu_mevt)) { 545 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", 546 cpu); 547 548 continue; 549 } 550 pcpu_mevt->evt.irq = mct_irq; 551 } 552 } 553 554 /* Install hotplug callbacks which configure the timer on this CPU */ 555 err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, 556 "clockevents/exynos4/mct_timer:starting", 557 exynos4_mct_starting_cpu, 558 exynos4_mct_dying_cpu); 559 if (err) 560 goto out_irq; 561 562 return 0; 563 564 out_irq: 565 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); 566 return err; 567 } 568 569 static int __init mct_init_dt(struct device_node *np, unsigned int int_type) 570 { 571 u32 nr_irqs, i; 572 int ret; 573 574 mct_int_type = int_type; 575 576 /* This driver uses only one global timer interrupt */ 577 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); 578 579 /* 580 * Find out the number of local irqs specified. The local 581 * timer irqs are specified after the four global timer 582 * irqs are specified. 583 */ 584 #ifdef CONFIG_OF 585 nr_irqs = of_irq_count(np); 586 #else 587 nr_irqs = 0; 588 #endif 589 for (i = MCT_L0_IRQ; i < nr_irqs; i++) 590 mct_irqs[i] = irq_of_parse_and_map(np, i); 591 592 ret = exynos4_timer_resources(np, of_iomap(np, 0)); 593 if (ret) 594 return ret; 595 596 ret = exynos4_clocksource_init(); 597 if (ret) 598 return ret; 599 600 return exynos4_clockevent_init(); 601 } 602 603 604 static int __init mct_init_spi(struct device_node *np) 605 { 606 return mct_init_dt(np, MCT_INT_SPI); 607 } 608 609 static int __init mct_init_ppi(struct device_node *np) 610 { 611 return mct_init_dt(np, MCT_INT_PPI); 612 } 613 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); 614 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); 615