1 /* linux/arch/arm/mach-exynos4/mct.c 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * EXYNOS4 MCT(Multi-Core Timer) support 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/clockchips.h> 19 #include <linux/platform_device.h> 20 #include <linux/delay.h> 21 #include <linux/percpu.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_address.h> 25 #include <linux/clocksource.h> 26 27 #include <asm/localtimer.h> 28 #include <asm/mach/time.h> 29 30 #define EXYNOS4_MCTREG(x) (x) 31 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) 32 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) 33 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) 34 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) 35 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) 36 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) 37 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) 38 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) 39 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) 40 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) 41 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) 42 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) 43 #define EXYNOS4_MCT_L_MASK (0xffffff00) 44 45 #define MCT_L_TCNTB_OFFSET (0x00) 46 #define MCT_L_ICNTB_OFFSET (0x08) 47 #define MCT_L_TCON_OFFSET (0x20) 48 #define MCT_L_INT_CSTAT_OFFSET (0x30) 49 #define MCT_L_INT_ENB_OFFSET (0x34) 50 #define MCT_L_WSTAT_OFFSET (0x40) 51 #define MCT_G_TCON_START (1 << 8) 52 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) 53 #define MCT_G_TCON_COMP0_ENABLE (1 << 0) 54 #define MCT_L_TCON_INTERVAL_MODE (1 << 2) 55 #define MCT_L_TCON_INT_START (1 << 1) 56 #define MCT_L_TCON_TIMER_START (1 << 0) 57 58 #define TICK_BASE_CNT 1 59 60 enum { 61 MCT_INT_SPI, 62 MCT_INT_PPI 63 }; 64 65 enum { 66 MCT_G0_IRQ, 67 MCT_G1_IRQ, 68 MCT_G2_IRQ, 69 MCT_G3_IRQ, 70 MCT_L0_IRQ, 71 MCT_L1_IRQ, 72 MCT_L2_IRQ, 73 MCT_L3_IRQ, 74 MCT_NR_IRQS, 75 }; 76 77 static void __iomem *reg_base; 78 static unsigned long clk_rate; 79 static unsigned int mct_int_type; 80 static int mct_irqs[MCT_NR_IRQS]; 81 82 struct mct_clock_event_device { 83 struct clock_event_device *evt; 84 unsigned long base; 85 char name[10]; 86 }; 87 88 static void exynos4_mct_write(unsigned int value, unsigned long offset) 89 { 90 unsigned long stat_addr; 91 u32 mask; 92 u32 i; 93 94 __raw_writel(value, reg_base + offset); 95 96 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { 97 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; 98 switch (offset & EXYNOS4_MCT_L_MASK) { 99 case MCT_L_TCON_OFFSET: 100 mask = 1 << 3; /* L_TCON write status */ 101 break; 102 case MCT_L_ICNTB_OFFSET: 103 mask = 1 << 1; /* L_ICNTB write status */ 104 break; 105 case MCT_L_TCNTB_OFFSET: 106 mask = 1 << 0; /* L_TCNTB write status */ 107 break; 108 default: 109 return; 110 } 111 } else { 112 switch (offset) { 113 case EXYNOS4_MCT_G_TCON: 114 stat_addr = EXYNOS4_MCT_G_WSTAT; 115 mask = 1 << 16; /* G_TCON write status */ 116 break; 117 case EXYNOS4_MCT_G_COMP0_L: 118 stat_addr = EXYNOS4_MCT_G_WSTAT; 119 mask = 1 << 0; /* G_COMP0_L write status */ 120 break; 121 case EXYNOS4_MCT_G_COMP0_U: 122 stat_addr = EXYNOS4_MCT_G_WSTAT; 123 mask = 1 << 1; /* G_COMP0_U write status */ 124 break; 125 case EXYNOS4_MCT_G_COMP0_ADD_INCR: 126 stat_addr = EXYNOS4_MCT_G_WSTAT; 127 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ 128 break; 129 case EXYNOS4_MCT_G_CNT_L: 130 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 131 mask = 1 << 0; /* G_CNT_L write status */ 132 break; 133 case EXYNOS4_MCT_G_CNT_U: 134 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 135 mask = 1 << 1; /* G_CNT_U write status */ 136 break; 137 default: 138 return; 139 } 140 } 141 142 /* Wait maximum 1 ms until written values are applied */ 143 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) 144 if (__raw_readl(reg_base + stat_addr) & mask) { 145 __raw_writel(mask, reg_base + stat_addr); 146 return; 147 } 148 149 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); 150 } 151 152 /* Clocksource handling */ 153 static void exynos4_mct_frc_start(u32 hi, u32 lo) 154 { 155 u32 reg; 156 157 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); 158 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); 159 160 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); 161 reg |= MCT_G_TCON_START; 162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); 163 } 164 165 static cycle_t exynos4_frc_read(struct clocksource *cs) 166 { 167 unsigned int lo, hi; 168 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); 169 170 do { 171 hi = hi2; 172 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); 173 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); 174 } while (hi != hi2); 175 176 return ((cycle_t)hi << 32) | lo; 177 } 178 179 static void exynos4_frc_resume(struct clocksource *cs) 180 { 181 exynos4_mct_frc_start(0, 0); 182 } 183 184 struct clocksource mct_frc = { 185 .name = "mct-frc", 186 .rating = 400, 187 .read = exynos4_frc_read, 188 .mask = CLOCKSOURCE_MASK(64), 189 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 190 .resume = exynos4_frc_resume, 191 }; 192 193 static void __init exynos4_clocksource_init(void) 194 { 195 exynos4_mct_frc_start(0, 0); 196 197 if (clocksource_register_hz(&mct_frc, clk_rate)) 198 panic("%s: can't register clocksource\n", mct_frc.name); 199 } 200 201 static void exynos4_mct_comp0_stop(void) 202 { 203 unsigned int tcon; 204 205 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); 206 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); 207 208 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); 209 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); 210 } 211 212 static void exynos4_mct_comp0_start(enum clock_event_mode mode, 213 unsigned long cycles) 214 { 215 unsigned int tcon; 216 cycle_t comp_cycle; 217 218 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); 219 220 if (mode == CLOCK_EVT_MODE_PERIODIC) { 221 tcon |= MCT_G_TCON_COMP0_AUTO_INC; 222 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); 223 } 224 225 comp_cycle = exynos4_frc_read(&mct_frc) + cycles; 226 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); 227 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); 228 229 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); 230 231 tcon |= MCT_G_TCON_COMP0_ENABLE; 232 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); 233 } 234 235 static int exynos4_comp_set_next_event(unsigned long cycles, 236 struct clock_event_device *evt) 237 { 238 exynos4_mct_comp0_start(evt->mode, cycles); 239 240 return 0; 241 } 242 243 static void exynos4_comp_set_mode(enum clock_event_mode mode, 244 struct clock_event_device *evt) 245 { 246 unsigned long cycles_per_jiffy; 247 exynos4_mct_comp0_stop(); 248 249 switch (mode) { 250 case CLOCK_EVT_MODE_PERIODIC: 251 cycles_per_jiffy = 252 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); 253 exynos4_mct_comp0_start(mode, cycles_per_jiffy); 254 break; 255 256 case CLOCK_EVT_MODE_ONESHOT: 257 case CLOCK_EVT_MODE_UNUSED: 258 case CLOCK_EVT_MODE_SHUTDOWN: 259 case CLOCK_EVT_MODE_RESUME: 260 break; 261 } 262 } 263 264 static struct clock_event_device mct_comp_device = { 265 .name = "mct-comp", 266 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 267 .rating = 250, 268 .set_next_event = exynos4_comp_set_next_event, 269 .set_mode = exynos4_comp_set_mode, 270 }; 271 272 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) 273 { 274 struct clock_event_device *evt = dev_id; 275 276 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); 277 278 evt->event_handler(evt); 279 280 return IRQ_HANDLED; 281 } 282 283 static struct irqaction mct_comp_event_irq = { 284 .name = "mct_comp_irq", 285 .flags = IRQF_TIMER | IRQF_IRQPOLL, 286 .handler = exynos4_mct_comp_isr, 287 .dev_id = &mct_comp_device, 288 }; 289 290 static void exynos4_clockevent_init(void) 291 { 292 mct_comp_device.cpumask = cpumask_of(0); 293 clockevents_config_and_register(&mct_comp_device, clk_rate, 294 0xf, 0xffffffff); 295 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); 296 } 297 298 #ifdef CONFIG_LOCAL_TIMERS 299 300 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); 301 302 /* Clock event handling */ 303 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) 304 { 305 unsigned long tmp; 306 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; 307 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; 308 309 tmp = __raw_readl(reg_base + offset); 310 if (tmp & mask) { 311 tmp &= ~mask; 312 exynos4_mct_write(tmp, offset); 313 } 314 } 315 316 static void exynos4_mct_tick_start(unsigned long cycles, 317 struct mct_clock_event_device *mevt) 318 { 319 unsigned long tmp; 320 321 exynos4_mct_tick_stop(mevt); 322 323 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ 324 325 /* update interrupt count buffer */ 326 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); 327 328 /* enable MCT tick interrupt */ 329 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); 330 331 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET); 332 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | 333 MCT_L_TCON_INTERVAL_MODE; 334 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); 335 } 336 337 static int exynos4_tick_set_next_event(unsigned long cycles, 338 struct clock_event_device *evt) 339 { 340 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); 341 342 exynos4_mct_tick_start(cycles, mevt); 343 344 return 0; 345 } 346 347 static inline void exynos4_tick_set_mode(enum clock_event_mode mode, 348 struct clock_event_device *evt) 349 { 350 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); 351 unsigned long cycles_per_jiffy; 352 353 exynos4_mct_tick_stop(mevt); 354 355 switch (mode) { 356 case CLOCK_EVT_MODE_PERIODIC: 357 cycles_per_jiffy = 358 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); 359 exynos4_mct_tick_start(cycles_per_jiffy, mevt); 360 break; 361 362 case CLOCK_EVT_MODE_ONESHOT: 363 case CLOCK_EVT_MODE_UNUSED: 364 case CLOCK_EVT_MODE_SHUTDOWN: 365 case CLOCK_EVT_MODE_RESUME: 366 break; 367 } 368 } 369 370 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) 371 { 372 struct clock_event_device *evt = mevt->evt; 373 374 /* 375 * This is for supporting oneshot mode. 376 * Mct would generate interrupt periodically 377 * without explicit stopping. 378 */ 379 if (evt->mode != CLOCK_EVT_MODE_PERIODIC) 380 exynos4_mct_tick_stop(mevt); 381 382 /* Clear the MCT tick interrupt */ 383 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { 384 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 385 return 1; 386 } else { 387 return 0; 388 } 389 } 390 391 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) 392 { 393 struct mct_clock_event_device *mevt = dev_id; 394 struct clock_event_device *evt = mevt->evt; 395 396 exynos4_mct_tick_clear(mevt); 397 398 evt->event_handler(evt); 399 400 return IRQ_HANDLED; 401 } 402 403 static struct irqaction mct_tick0_event_irq = { 404 .name = "mct_tick0_irq", 405 .flags = IRQF_TIMER | IRQF_NOBALANCING, 406 .handler = exynos4_mct_tick_isr, 407 }; 408 409 static struct irqaction mct_tick1_event_irq = { 410 .name = "mct_tick1_irq", 411 .flags = IRQF_TIMER | IRQF_NOBALANCING, 412 .handler = exynos4_mct_tick_isr, 413 }; 414 415 static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) 416 { 417 struct mct_clock_event_device *mevt; 418 unsigned int cpu = smp_processor_id(); 419 420 mevt = this_cpu_ptr(&percpu_mct_tick); 421 mevt->evt = evt; 422 423 mevt->base = EXYNOS4_MCT_L_BASE(cpu); 424 sprintf(mevt->name, "mct_tick%d", cpu); 425 426 evt->name = mevt->name; 427 evt->cpumask = cpumask_of(cpu); 428 evt->set_next_event = exynos4_tick_set_next_event; 429 evt->set_mode = exynos4_tick_set_mode; 430 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 431 evt->rating = 450; 432 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), 433 0xf, 0x7fffffff); 434 435 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 436 437 if (mct_int_type == MCT_INT_SPI) { 438 if (cpu == 0) { 439 mct_tick0_event_irq.dev_id = mevt; 440 evt->irq = mct_irqs[MCT_L0_IRQ]; 441 setup_irq(evt->irq, &mct_tick0_event_irq); 442 } else { 443 mct_tick1_event_irq.dev_id = mevt; 444 evt->irq = mct_irqs[MCT_L1_IRQ]; 445 setup_irq(evt->irq, &mct_tick1_event_irq); 446 irq_set_affinity(evt->irq, cpumask_of(1)); 447 } 448 } else { 449 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); 450 } 451 452 return 0; 453 } 454 455 static void exynos4_local_timer_stop(struct clock_event_device *evt) 456 { 457 unsigned int cpu = smp_processor_id(); 458 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 459 if (mct_int_type == MCT_INT_SPI) 460 if (cpu == 0) 461 remove_irq(evt->irq, &mct_tick0_event_irq); 462 else 463 remove_irq(evt->irq, &mct_tick1_event_irq); 464 else 465 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); 466 } 467 468 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { 469 .setup = exynos4_local_timer_setup, 470 .stop = exynos4_local_timer_stop, 471 }; 472 #endif /* CONFIG_LOCAL_TIMERS */ 473 474 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base) 475 { 476 struct clk *mct_clk, *tick_clk; 477 478 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : 479 clk_get(NULL, "fin_pll"); 480 if (IS_ERR(tick_clk)) 481 panic("%s: unable to determine tick clock rate\n", __func__); 482 clk_rate = clk_get_rate(tick_clk); 483 484 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); 485 if (IS_ERR(mct_clk)) 486 panic("%s: unable to retrieve mct clock instance\n", __func__); 487 clk_prepare_enable(mct_clk); 488 489 reg_base = base; 490 if (!reg_base) 491 panic("%s: unable to ioremap mct address space\n", __func__); 492 493 #ifdef CONFIG_LOCAL_TIMERS 494 if (mct_int_type == MCT_INT_PPI) { 495 int err; 496 497 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], 498 exynos4_mct_tick_isr, "MCT", 499 &percpu_mct_tick); 500 WARN(err, "MCT: can't request IRQ %d (%d)\n", 501 mct_irqs[MCT_L0_IRQ], err); 502 } 503 504 local_timer_register(&exynos4_mct_tick_ops); 505 #endif /* CONFIG_LOCAL_TIMERS */ 506 } 507 508 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1) 509 { 510 mct_irqs[MCT_G0_IRQ] = irq_g0; 511 mct_irqs[MCT_L0_IRQ] = irq_l0; 512 mct_irqs[MCT_L1_IRQ] = irq_l1; 513 mct_int_type = MCT_INT_SPI; 514 515 exynos4_timer_resources(NULL, base); 516 exynos4_clocksource_init(); 517 exynos4_clockevent_init(); 518 } 519 520 static void __init mct_init_dt(struct device_node *np, unsigned int int_type) 521 { 522 u32 nr_irqs, i; 523 524 mct_int_type = int_type; 525 526 /* This driver uses only one global timer interrupt */ 527 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); 528 529 /* 530 * Find out the number of local irqs specified. The local 531 * timer irqs are specified after the four global timer 532 * irqs are specified. 533 */ 534 #ifdef CONFIG_OF 535 nr_irqs = of_irq_count(np); 536 #else 537 nr_irqs = 0; 538 #endif 539 for (i = MCT_L0_IRQ; i < nr_irqs; i++) 540 mct_irqs[i] = irq_of_parse_and_map(np, i); 541 542 exynos4_timer_resources(np, of_iomap(np, 0)); 543 exynos4_clocksource_init(); 544 exynos4_clockevent_init(); 545 } 546 547 548 static void __init mct_init_spi(struct device_node *np) 549 { 550 return mct_init_dt(np, MCT_INT_SPI); 551 } 552 553 static void __init mct_init_ppi(struct device_node *np) 554 { 555 return mct_init_dt(np, MCT_INT_PPI); 556 } 557 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); 558 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); 559