106c3df49SJamie Iles /* 206c3df49SJamie Iles * (C) Copyright 2009 Intel Corporation 306c3df49SJamie Iles * Author: Jacob Pan (jacob.jun.pan@intel.com) 406c3df49SJamie Iles * 506c3df49SJamie Iles * Shared with ARM platforms, Jamie Iles, Picochip 2011 606c3df49SJamie Iles * 706c3df49SJamie Iles * This program is free software; you can redistribute it and/or modify 806c3df49SJamie Iles * it under the terms of the GNU General Public License version 2 as 906c3df49SJamie Iles * published by the Free Software Foundation. 1006c3df49SJamie Iles * 1106c3df49SJamie Iles * Support for the Synopsys DesignWare APB Timers. 1206c3df49SJamie Iles */ 1306c3df49SJamie Iles #include <linux/dw_apb_timer.h> 1406c3df49SJamie Iles #include <linux/delay.h> 1506c3df49SJamie Iles #include <linux/kernel.h> 1606c3df49SJamie Iles #include <linux/interrupt.h> 1706c3df49SJamie Iles #include <linux/irq.h> 1806c3df49SJamie Iles #include <linux/io.h> 1906c3df49SJamie Iles #include <linux/slab.h> 2006c3df49SJamie Iles 2106c3df49SJamie Iles #define APBT_MIN_PERIOD 4 2206c3df49SJamie Iles #define APBT_MIN_DELTA_USEC 200 2306c3df49SJamie Iles 24d3d8fee4SJohn Stultz #define APBTMR_N_LOAD_COUNT 0x00 25d3d8fee4SJohn Stultz #define APBTMR_N_CURRENT_VALUE 0x04 26d3d8fee4SJohn Stultz #define APBTMR_N_CONTROL 0x08 27d3d8fee4SJohn Stultz #define APBTMR_N_EOI 0x0c 28d3d8fee4SJohn Stultz #define APBTMR_N_INT_STATUS 0x10 29d3d8fee4SJohn Stultz 3006c3df49SJamie Iles #define APBTMRS_INT_STATUS 0xa0 3106c3df49SJamie Iles #define APBTMRS_EOI 0xa4 3206c3df49SJamie Iles #define APBTMRS_RAW_INT_STATUS 0xa8 3306c3df49SJamie Iles #define APBTMRS_COMP_VERSION 0xac 3406c3df49SJamie Iles 3506c3df49SJamie Iles #define APBTMR_CONTROL_ENABLE (1 << 0) 3606c3df49SJamie Iles /* 1: periodic, 0:free running. */ 3706c3df49SJamie Iles #define APBTMR_CONTROL_MODE_PERIODIC (1 << 1) 3806c3df49SJamie Iles #define APBTMR_CONTROL_INT (1 << 2) 3906c3df49SJamie Iles 4006c3df49SJamie Iles static inline struct dw_apb_clock_event_device * 4106c3df49SJamie Iles ced_to_dw_apb_ced(struct clock_event_device *evt) 4206c3df49SJamie Iles { 4306c3df49SJamie Iles return container_of(evt, struct dw_apb_clock_event_device, ced); 4406c3df49SJamie Iles } 4506c3df49SJamie Iles 4606c3df49SJamie Iles static inline struct dw_apb_clocksource * 4706c3df49SJamie Iles clocksource_to_dw_apb_clocksource(struct clocksource *cs) 4806c3df49SJamie Iles { 4906c3df49SJamie Iles return container_of(cs, struct dw_apb_clocksource, cs); 5006c3df49SJamie Iles } 5106c3df49SJamie Iles 529f4165dcSJisheng Zhang static u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs) 5306c3df49SJamie Iles { 5406c3df49SJamie Iles return readl(timer->base + offs); 5506c3df49SJamie Iles } 5606c3df49SJamie Iles 579f4165dcSJisheng Zhang static void apbt_writel(struct dw_apb_timer *timer, u32 val, 5806c3df49SJamie Iles unsigned long offs) 5906c3df49SJamie Iles { 6006c3df49SJamie Iles writel(val, timer->base + offs); 6106c3df49SJamie Iles } 6206c3df49SJamie Iles 6306c3df49SJamie Iles static void apbt_disable_int(struct dw_apb_timer *timer) 6406c3df49SJamie Iles { 659f4165dcSJisheng Zhang u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL); 6606c3df49SJamie Iles 6706c3df49SJamie Iles ctrl |= APBTMR_CONTROL_INT; 6806c3df49SJamie Iles apbt_writel(timer, ctrl, APBTMR_N_CONTROL); 6906c3df49SJamie Iles } 7006c3df49SJamie Iles 7106c3df49SJamie Iles /** 7206c3df49SJamie Iles * dw_apb_clockevent_pause() - stop the clock_event_device from running 7306c3df49SJamie Iles * 7406c3df49SJamie Iles * @dw_ced: The APB clock to stop generating events. 7506c3df49SJamie Iles */ 7606c3df49SJamie Iles void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced) 7706c3df49SJamie Iles { 7806c3df49SJamie Iles disable_irq(dw_ced->timer.irq); 7906c3df49SJamie Iles apbt_disable_int(&dw_ced->timer); 8006c3df49SJamie Iles } 8106c3df49SJamie Iles 8206c3df49SJamie Iles static void apbt_eoi(struct dw_apb_timer *timer) 8306c3df49SJamie Iles { 8406c3df49SJamie Iles apbt_readl(timer, APBTMR_N_EOI); 8506c3df49SJamie Iles } 8606c3df49SJamie Iles 8706c3df49SJamie Iles static irqreturn_t dw_apb_clockevent_irq(int irq, void *data) 8806c3df49SJamie Iles { 8906c3df49SJamie Iles struct clock_event_device *evt = data; 9006c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 9106c3df49SJamie Iles 9206c3df49SJamie Iles if (!evt->event_handler) { 9306c3df49SJamie Iles pr_info("Spurious APBT timer interrupt %d", irq); 9406c3df49SJamie Iles return IRQ_NONE; 9506c3df49SJamie Iles } 9606c3df49SJamie Iles 9706c3df49SJamie Iles if (dw_ced->eoi) 9806c3df49SJamie Iles dw_ced->eoi(&dw_ced->timer); 9906c3df49SJamie Iles 10006c3df49SJamie Iles evt->event_handler(evt); 10106c3df49SJamie Iles return IRQ_HANDLED; 10206c3df49SJamie Iles } 10306c3df49SJamie Iles 10406c3df49SJamie Iles static void apbt_enable_int(struct dw_apb_timer *timer) 10506c3df49SJamie Iles { 1069f4165dcSJisheng Zhang u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL); 10706c3df49SJamie Iles /* clear pending intr */ 10806c3df49SJamie Iles apbt_readl(timer, APBTMR_N_EOI); 10906c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_INT; 11006c3df49SJamie Iles apbt_writel(timer, ctrl, APBTMR_N_CONTROL); 11106c3df49SJamie Iles } 11206c3df49SJamie Iles 113226be92bSViresh Kumar static int apbt_shutdown(struct clock_event_device *evt) 11406c3df49SJamie Iles { 11506c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 1169f4165dcSJisheng Zhang u32 ctrl; 11706c3df49SJamie Iles 118226be92bSViresh Kumar pr_debug("%s CPU %d state=shutdown\n", __func__, 119226be92bSViresh Kumar cpumask_first(evt->cpumask)); 12006c3df49SJamie Iles 12106c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 12206c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 12306c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 124226be92bSViresh Kumar return 0; 125226be92bSViresh Kumar } 12606c3df49SJamie Iles 127226be92bSViresh Kumar static int apbt_set_oneshot(struct clock_event_device *evt) 128226be92bSViresh Kumar { 129226be92bSViresh Kumar struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 1309f4165dcSJisheng Zhang u32 ctrl; 131226be92bSViresh Kumar 132226be92bSViresh Kumar pr_debug("%s CPU %d state=oneshot\n", __func__, 133226be92bSViresh Kumar cpumask_first(evt->cpumask)); 134226be92bSViresh Kumar 13506c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 13606c3df49SJamie Iles /* 13706c3df49SJamie Iles * set free running mode, this mode will let timer reload max 13806c3df49SJamie Iles * timeout which will give time (3min on 25MHz clock) to rearm 13906c3df49SJamie Iles * the next event, therefore emulate the one-shot mode. 14006c3df49SJamie Iles */ 14106c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 14206c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; 14306c3df49SJamie Iles 14406c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 14506c3df49SJamie Iles /* write again to set free running mode */ 14606c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 14706c3df49SJamie Iles 14806c3df49SJamie Iles /* 14906c3df49SJamie Iles * DW APB p. 46, load counter with all 1s before starting free 15006c3df49SJamie Iles * running mode. 15106c3df49SJamie Iles */ 15206c3df49SJamie Iles apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT); 15306c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_INT; 15406c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE; 15506c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 156226be92bSViresh Kumar return 0; 157226be92bSViresh Kumar } 15806c3df49SJamie Iles 159226be92bSViresh Kumar static int apbt_set_periodic(struct clock_event_device *evt) 160226be92bSViresh Kumar { 161226be92bSViresh Kumar struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 162226be92bSViresh Kumar unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ); 1639f4165dcSJisheng Zhang u32 ctrl; 164226be92bSViresh Kumar 165226be92bSViresh Kumar pr_debug("%s CPU %d state=periodic\n", __func__, 166226be92bSViresh Kumar cpumask_first(evt->cpumask)); 167226be92bSViresh Kumar 16806c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 169226be92bSViresh Kumar ctrl |= APBTMR_CONTROL_MODE_PERIODIC; 170226be92bSViresh Kumar apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 171226be92bSViresh Kumar /* 172226be92bSViresh Kumar * DW APB p. 46, have to disable timer before load counter, 173226be92bSViresh Kumar * may cause sync problem. 174226be92bSViresh Kumar */ 17506c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 17606c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 177226be92bSViresh Kumar udelay(1); 178226be92bSViresh Kumar pr_debug("Setting clock period %lu for HZ %d\n", period, HZ); 179226be92bSViresh Kumar apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT); 180226be92bSViresh Kumar ctrl |= APBTMR_CONTROL_ENABLE; 181226be92bSViresh Kumar apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 182226be92bSViresh Kumar return 0; 18306c3df49SJamie Iles } 184226be92bSViresh Kumar 185226be92bSViresh Kumar static int apbt_resume(struct clock_event_device *evt) 186226be92bSViresh Kumar { 187226be92bSViresh Kumar struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 188226be92bSViresh Kumar 189226be92bSViresh Kumar pr_debug("%s CPU %d state=resume\n", __func__, 190226be92bSViresh Kumar cpumask_first(evt->cpumask)); 191226be92bSViresh Kumar 192226be92bSViresh Kumar apbt_enable_int(&dw_ced->timer); 193226be92bSViresh Kumar return 0; 19406c3df49SJamie Iles } 19506c3df49SJamie Iles 19606c3df49SJamie Iles static int apbt_next_event(unsigned long delta, 19706c3df49SJamie Iles struct clock_event_device *evt) 19806c3df49SJamie Iles { 1999f4165dcSJisheng Zhang u32 ctrl; 20006c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 20106c3df49SJamie Iles 20206c3df49SJamie Iles /* Disable timer */ 20306c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 20406c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 20506c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 20606c3df49SJamie Iles /* write new count */ 20706c3df49SJamie Iles apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT); 20806c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE; 20906c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 21006c3df49SJamie Iles 21106c3df49SJamie Iles return 0; 21206c3df49SJamie Iles } 21306c3df49SJamie Iles 21406c3df49SJamie Iles /** 21506c3df49SJamie Iles * dw_apb_clockevent_init() - use an APB timer as a clock_event_device 21606c3df49SJamie Iles * 21706c3df49SJamie Iles * @cpu: The CPU the events will be targeted at. 21806c3df49SJamie Iles * @name: The name used for the timer and the IRQ for it. 21906c3df49SJamie Iles * @rating: The rating to give the timer. 22006c3df49SJamie Iles * @base: I/O base for the timer registers. 22106c3df49SJamie Iles * @irq: The interrupt number to use for the timer. 22206c3df49SJamie Iles * @freq: The frequency that the timer counts at. 22306c3df49SJamie Iles * 22406c3df49SJamie Iles * This creates a clock_event_device for using with the generic clock layer 22506c3df49SJamie Iles * but does not start and register it. This should be done with 22606c3df49SJamie Iles * dw_apb_clockevent_register() as the next step. If this is the first time 22706c3df49SJamie Iles * it has been called for a timer then the IRQ will be requested, if not it 22806c3df49SJamie Iles * just be enabled to allow CPU hotplug to avoid repeatedly requesting and 22906c3df49SJamie Iles * releasing the IRQ. 23006c3df49SJamie Iles */ 23106c3df49SJamie Iles struct dw_apb_clock_event_device * 23206c3df49SJamie Iles dw_apb_clockevent_init(int cpu, const char *name, unsigned rating, 23306c3df49SJamie Iles void __iomem *base, int irq, unsigned long freq) 23406c3df49SJamie Iles { 23506c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = 23606c3df49SJamie Iles kzalloc(sizeof(*dw_ced), GFP_KERNEL); 23706c3df49SJamie Iles int err; 23806c3df49SJamie Iles 23906c3df49SJamie Iles if (!dw_ced) 24006c3df49SJamie Iles return NULL; 24106c3df49SJamie Iles 24206c3df49SJamie Iles dw_ced->timer.base = base; 24306c3df49SJamie Iles dw_ced->timer.irq = irq; 24406c3df49SJamie Iles dw_ced->timer.freq = freq; 24506c3df49SJamie Iles 24606c3df49SJamie Iles clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD); 24706c3df49SJamie Iles dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff, 24806c3df49SJamie Iles &dw_ced->ced); 24906c3df49SJamie Iles dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced); 25006c3df49SJamie Iles dw_ced->ced.cpumask = cpumask_of(cpu); 2518b5f0010SJisheng Zhang dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | 2528b5f0010SJisheng Zhang CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; 253226be92bSViresh Kumar dw_ced->ced.set_state_shutdown = apbt_shutdown; 254226be92bSViresh Kumar dw_ced->ced.set_state_periodic = apbt_set_periodic; 255226be92bSViresh Kumar dw_ced->ced.set_state_oneshot = apbt_set_oneshot; 256226be92bSViresh Kumar dw_ced->ced.tick_resume = apbt_resume; 25706c3df49SJamie Iles dw_ced->ced.set_next_event = apbt_next_event; 25806c3df49SJamie Iles dw_ced->ced.irq = dw_ced->timer.irq; 25906c3df49SJamie Iles dw_ced->ced.rating = rating; 26006c3df49SJamie Iles dw_ced->ced.name = name; 26106c3df49SJamie Iles 26206c3df49SJamie Iles dw_ced->irqaction.name = dw_ced->ced.name; 26306c3df49SJamie Iles dw_ced->irqaction.handler = dw_apb_clockevent_irq; 26406c3df49SJamie Iles dw_ced->irqaction.dev_id = &dw_ced->ced; 26506c3df49SJamie Iles dw_ced->irqaction.irq = irq; 26606c3df49SJamie Iles dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | 26738c30a84SMichael Opdenacker IRQF_NOBALANCING; 26806c3df49SJamie Iles 26906c3df49SJamie Iles dw_ced->eoi = apbt_eoi; 27006c3df49SJamie Iles err = setup_irq(irq, &dw_ced->irqaction); 27106c3df49SJamie Iles if (err) { 27206c3df49SJamie Iles pr_err("failed to request timer irq\n"); 27306c3df49SJamie Iles kfree(dw_ced); 27406c3df49SJamie Iles dw_ced = NULL; 27506c3df49SJamie Iles } 27606c3df49SJamie Iles 27706c3df49SJamie Iles return dw_ced; 27806c3df49SJamie Iles } 27906c3df49SJamie Iles 28006c3df49SJamie Iles /** 28106c3df49SJamie Iles * dw_apb_clockevent_resume() - resume a clock that has been paused. 28206c3df49SJamie Iles * 28306c3df49SJamie Iles * @dw_ced: The APB clock to resume. 28406c3df49SJamie Iles */ 28506c3df49SJamie Iles void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced) 28606c3df49SJamie Iles { 28706c3df49SJamie Iles enable_irq(dw_ced->timer.irq); 28806c3df49SJamie Iles } 28906c3df49SJamie Iles 29006c3df49SJamie Iles /** 29106c3df49SJamie Iles * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ. 29206c3df49SJamie Iles * 29306c3df49SJamie Iles * @dw_ced: The APB clock to stop generating the events. 29406c3df49SJamie Iles */ 29506c3df49SJamie Iles void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced) 29606c3df49SJamie Iles { 29706c3df49SJamie Iles free_irq(dw_ced->timer.irq, &dw_ced->ced); 29806c3df49SJamie Iles } 29906c3df49SJamie Iles 30006c3df49SJamie Iles /** 30106c3df49SJamie Iles * dw_apb_clockevent_register() - register the clock with the generic layer 30206c3df49SJamie Iles * 30306c3df49SJamie Iles * @dw_ced: The APB clock to register as a clock_event_device. 30406c3df49SJamie Iles */ 30506c3df49SJamie Iles void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced) 30606c3df49SJamie Iles { 30706c3df49SJamie Iles apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL); 30806c3df49SJamie Iles clockevents_register_device(&dw_ced->ced); 30906c3df49SJamie Iles apbt_enable_int(&dw_ced->timer); 31006c3df49SJamie Iles } 31106c3df49SJamie Iles 31206c3df49SJamie Iles /** 31306c3df49SJamie Iles * dw_apb_clocksource_start() - start the clocksource counting. 31406c3df49SJamie Iles * 31506c3df49SJamie Iles * @dw_cs: The clocksource to start. 31606c3df49SJamie Iles * 31706c3df49SJamie Iles * This is used to start the clocksource before registration and can be used 31806c3df49SJamie Iles * to enable calibration of timers. 31906c3df49SJamie Iles */ 32006c3df49SJamie Iles void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs) 32106c3df49SJamie Iles { 32206c3df49SJamie Iles /* 32306c3df49SJamie Iles * start count down from 0xffff_ffff. this is done by toggling the 32406c3df49SJamie Iles * enable bit then load initial load count to ~0. 32506c3df49SJamie Iles */ 3269f4165dcSJisheng Zhang u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL); 32706c3df49SJamie Iles 32806c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 32906c3df49SJamie Iles apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL); 33006c3df49SJamie Iles apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT); 33106c3df49SJamie Iles /* enable, mask interrupt */ 33206c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; 33306c3df49SJamie Iles ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); 33406c3df49SJamie Iles apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL); 33506c3df49SJamie Iles /* read it once to get cached counter value initialized */ 33606c3df49SJamie Iles dw_apb_clocksource_read(dw_cs); 33706c3df49SJamie Iles } 33806c3df49SJamie Iles 33906c3df49SJamie Iles static cycle_t __apbt_read_clocksource(struct clocksource *cs) 34006c3df49SJamie Iles { 3419f4165dcSJisheng Zhang u32 current_count; 34206c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = 34306c3df49SJamie Iles clocksource_to_dw_apb_clocksource(cs); 34406c3df49SJamie Iles 34506c3df49SJamie Iles current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE); 34606c3df49SJamie Iles 34706c3df49SJamie Iles return (cycle_t)~current_count; 34806c3df49SJamie Iles } 34906c3df49SJamie Iles 35006c3df49SJamie Iles static void apbt_restart_clocksource(struct clocksource *cs) 35106c3df49SJamie Iles { 35206c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = 35306c3df49SJamie Iles clocksource_to_dw_apb_clocksource(cs); 35406c3df49SJamie Iles 35506c3df49SJamie Iles dw_apb_clocksource_start(dw_cs); 35606c3df49SJamie Iles } 35706c3df49SJamie Iles 35806c3df49SJamie Iles /** 35906c3df49SJamie Iles * dw_apb_clocksource_init() - use an APB timer as a clocksource. 36006c3df49SJamie Iles * 36106c3df49SJamie Iles * @rating: The rating to give the clocksource. 36206c3df49SJamie Iles * @name: The name for the clocksource. 36306c3df49SJamie Iles * @base: The I/O base for the timer registers. 36406c3df49SJamie Iles * @freq: The frequency that the timer counts at. 36506c3df49SJamie Iles * 36606c3df49SJamie Iles * This creates a clocksource using an APB timer but does not yet register it 36706c3df49SJamie Iles * with the clocksource system. This should be done with 36806c3df49SJamie Iles * dw_apb_clocksource_register() as the next step. 36906c3df49SJamie Iles */ 37006c3df49SJamie Iles struct dw_apb_clocksource * 371a1330228SJamie Iles dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base, 37206c3df49SJamie Iles unsigned long freq) 37306c3df49SJamie Iles { 37406c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL); 37506c3df49SJamie Iles 37606c3df49SJamie Iles if (!dw_cs) 37706c3df49SJamie Iles return NULL; 37806c3df49SJamie Iles 37906c3df49SJamie Iles dw_cs->timer.base = base; 38006c3df49SJamie Iles dw_cs->timer.freq = freq; 38106c3df49SJamie Iles dw_cs->cs.name = name; 38206c3df49SJamie Iles dw_cs->cs.rating = rating; 38306c3df49SJamie Iles dw_cs->cs.read = __apbt_read_clocksource; 38406c3df49SJamie Iles dw_cs->cs.mask = CLOCKSOURCE_MASK(32); 38506c3df49SJamie Iles dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; 38606c3df49SJamie Iles dw_cs->cs.resume = apbt_restart_clocksource; 38706c3df49SJamie Iles 38806c3df49SJamie Iles return dw_cs; 38906c3df49SJamie Iles } 39006c3df49SJamie Iles 39106c3df49SJamie Iles /** 39206c3df49SJamie Iles * dw_apb_clocksource_register() - register the APB clocksource. 39306c3df49SJamie Iles * 39406c3df49SJamie Iles * @dw_cs: The clocksource to register. 39506c3df49SJamie Iles */ 39606c3df49SJamie Iles void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs) 39706c3df49SJamie Iles { 39806c3df49SJamie Iles clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq); 39906c3df49SJamie Iles } 40006c3df49SJamie Iles 40106c3df49SJamie Iles /** 40206c3df49SJamie Iles * dw_apb_clocksource_read() - read the current value of a clocksource. 40306c3df49SJamie Iles * 40406c3df49SJamie Iles * @dw_cs: The clocksource to read. 40506c3df49SJamie Iles */ 40606c3df49SJamie Iles cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs) 40706c3df49SJamie Iles { 40806c3df49SJamie Iles return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE); 40906c3df49SJamie Iles } 410