1 /* 2 * drivers/clocksource/arm_global_timer.c 3 * 4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 5 * Author: Stuart Menefy <stuart.menefy@st.com> 6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/clocksource.h> 16 #include <linux/clockchips.h> 17 #include <linux/cpu.h> 18 #include <linux/clk.h> 19 #include <linux/err.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/sched_clock.h> 25 26 #include <asm/cputype.h> 27 28 #define GT_COUNTER0 0x00 29 #define GT_COUNTER1 0x04 30 31 #define GT_CONTROL 0x08 32 #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ 33 #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ 34 #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ 35 #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ 36 37 #define GT_INT_STATUS 0x0c 38 #define GT_INT_STATUS_EVENT_FLAG BIT(0) 39 40 #define GT_COMP0 0x10 41 #define GT_COMP1 0x14 42 #define GT_AUTO_INC 0x18 43 44 /* 45 * We are expecting to be clocked by the ARM peripheral clock. 46 * 47 * Note: it is assumed we are using a prescaler value of zero, so this is 48 * the units for all operations. 49 */ 50 static void __iomem *gt_base; 51 static unsigned long gt_clk_rate; 52 static int gt_ppi; 53 static struct clock_event_device __percpu *gt_evt; 54 55 /* 56 * To get the value from the Global Timer Counter register proceed as follows: 57 * 1. Read the upper 32-bit timer counter register 58 * 2. Read the lower 32-bit timer counter register 59 * 3. Read the upper 32-bit timer counter register again. If the value is 60 * different to the 32-bit upper value read previously, go back to step 2. 61 * Otherwise the 64-bit timer counter value is correct. 62 */ 63 static u64 gt_counter_read(void) 64 { 65 u64 counter; 66 u32 lower; 67 u32 upper, old_upper; 68 69 upper = readl_relaxed(gt_base + GT_COUNTER1); 70 do { 71 old_upper = upper; 72 lower = readl_relaxed(gt_base + GT_COUNTER0); 73 upper = readl_relaxed(gt_base + GT_COUNTER1); 74 } while (upper != old_upper); 75 76 counter = upper; 77 counter <<= 32; 78 counter |= lower; 79 return counter; 80 } 81 82 /** 83 * To ensure that updates to comparator value register do not set the 84 * Interrupt Status Register proceed as follows: 85 * 1. Clear the Comp Enable bit in the Timer Control Register. 86 * 2. Write the lower 32-bit Comparator Value Register. 87 * 3. Write the upper 32-bit Comparator Value Register. 88 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. 89 */ 90 static void gt_compare_set(unsigned long delta, int periodic) 91 { 92 u64 counter = gt_counter_read(); 93 unsigned long ctrl; 94 95 counter += delta; 96 ctrl = GT_CONTROL_TIMER_ENABLE; 97 writel(ctrl, gt_base + GT_CONTROL); 98 writel(lower_32_bits(counter), gt_base + GT_COMP0); 99 writel(upper_32_bits(counter), gt_base + GT_COMP1); 100 101 if (periodic) { 102 writel(delta, gt_base + GT_AUTO_INC); 103 ctrl |= GT_CONTROL_AUTO_INC; 104 } 105 106 ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE; 107 writel(ctrl, gt_base + GT_CONTROL); 108 } 109 110 static void gt_clockevent_set_mode(enum clock_event_mode mode, 111 struct clock_event_device *clk) 112 { 113 unsigned long ctrl; 114 115 switch (mode) { 116 case CLOCK_EVT_MODE_PERIODIC: 117 gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1); 118 break; 119 case CLOCK_EVT_MODE_ONESHOT: 120 case CLOCK_EVT_MODE_UNUSED: 121 case CLOCK_EVT_MODE_SHUTDOWN: 122 ctrl = readl(gt_base + GT_CONTROL); 123 ctrl &= ~(GT_CONTROL_COMP_ENABLE | 124 GT_CONTROL_IRQ_ENABLE | GT_CONTROL_AUTO_INC); 125 writel(ctrl, gt_base + GT_CONTROL); 126 break; 127 default: 128 break; 129 } 130 } 131 132 static int gt_clockevent_set_next_event(unsigned long evt, 133 struct clock_event_device *unused) 134 { 135 gt_compare_set(evt, 0); 136 return 0; 137 } 138 139 static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id) 140 { 141 struct clock_event_device *evt = dev_id; 142 143 if (!(readl_relaxed(gt_base + GT_INT_STATUS) & 144 GT_INT_STATUS_EVENT_FLAG)) 145 return IRQ_NONE; 146 147 /** 148 * ERRATA 740657( Global Timer can send 2 interrupts for 149 * the same event in single-shot mode) 150 * Workaround: 151 * Either disable single-shot mode. 152 * Or 153 * Modify the Interrupt Handler to avoid the 154 * offending sequence. This is achieved by clearing 155 * the Global Timer flag _after_ having incremented 156 * the Comparator register value to a higher value. 157 */ 158 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) 159 gt_compare_set(ULONG_MAX, 0); 160 161 writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS); 162 evt->event_handler(evt); 163 164 return IRQ_HANDLED; 165 } 166 167 static int gt_clockevents_init(struct clock_event_device *clk) 168 { 169 int cpu = smp_processor_id(); 170 171 clk->name = "arm_global_timer"; 172 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | 173 CLOCK_EVT_FEAT_PERCPU; 174 clk->set_mode = gt_clockevent_set_mode; 175 clk->set_next_event = gt_clockevent_set_next_event; 176 clk->cpumask = cpumask_of(cpu); 177 clk->rating = 300; 178 clk->irq = gt_ppi; 179 clockevents_config_and_register(clk, gt_clk_rate, 180 1, 0xffffffff); 181 enable_percpu_irq(clk->irq, IRQ_TYPE_NONE); 182 return 0; 183 } 184 185 static void gt_clockevents_stop(struct clock_event_device *clk) 186 { 187 gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk); 188 disable_percpu_irq(clk->irq); 189 } 190 191 static cycle_t gt_clocksource_read(struct clocksource *cs) 192 { 193 return gt_counter_read(); 194 } 195 196 static struct clocksource gt_clocksource = { 197 .name = "arm_global_timer", 198 .rating = 300, 199 .read = gt_clocksource_read, 200 .mask = CLOCKSOURCE_MASK(64), 201 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 202 }; 203 204 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK 205 static u64 notrace gt_sched_clock_read(void) 206 { 207 return gt_counter_read(); 208 } 209 #endif 210 211 static void __init gt_clocksource_init(void) 212 { 213 writel(0, gt_base + GT_CONTROL); 214 writel(0, gt_base + GT_COUNTER0); 215 writel(0, gt_base + GT_COUNTER1); 216 /* enables timer on all the cores */ 217 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); 218 219 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK 220 sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate); 221 #endif 222 clocksource_register_hz(>_clocksource, gt_clk_rate); 223 } 224 225 static int gt_cpu_notify(struct notifier_block *self, unsigned long action, 226 void *hcpu) 227 { 228 switch (action & ~CPU_TASKS_FROZEN) { 229 case CPU_STARTING: 230 gt_clockevents_init(this_cpu_ptr(gt_evt)); 231 break; 232 case CPU_DYING: 233 gt_clockevents_stop(this_cpu_ptr(gt_evt)); 234 break; 235 } 236 237 return NOTIFY_OK; 238 } 239 static struct notifier_block gt_cpu_nb = { 240 .notifier_call = gt_cpu_notify, 241 }; 242 243 static void __init global_timer_of_register(struct device_node *np) 244 { 245 struct clk *gt_clk; 246 int err = 0; 247 248 /* 249 * In r2p0 the comparators for each processor with the global timer 250 * fire when the timer value is greater than or equal to. In previous 251 * revisions the comparators fired when the timer value was equal to. 252 */ 253 if ((read_cpuid_id() & 0xf0000f) < 0x200000) { 254 pr_warn("global-timer: non support for this cpu version.\n"); 255 return; 256 } 257 258 gt_ppi = irq_of_parse_and_map(np, 0); 259 if (!gt_ppi) { 260 pr_warn("global-timer: unable to parse irq\n"); 261 return; 262 } 263 264 gt_base = of_iomap(np, 0); 265 if (!gt_base) { 266 pr_warn("global-timer: invalid base address\n"); 267 return; 268 } 269 270 gt_clk = of_clk_get(np, 0); 271 if (!IS_ERR(gt_clk)) { 272 err = clk_prepare_enable(gt_clk); 273 if (err) 274 goto out_unmap; 275 } else { 276 pr_warn("global-timer: clk not found\n"); 277 err = -EINVAL; 278 goto out_unmap; 279 } 280 281 gt_clk_rate = clk_get_rate(gt_clk); 282 gt_evt = alloc_percpu(struct clock_event_device); 283 if (!gt_evt) { 284 pr_warn("global-timer: can't allocate memory\n"); 285 err = -ENOMEM; 286 goto out_clk; 287 } 288 289 err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt, 290 "gt", gt_evt); 291 if (err) { 292 pr_warn("global-timer: can't register interrupt %d (%d)\n", 293 gt_ppi, err); 294 goto out_free; 295 } 296 297 err = register_cpu_notifier(>_cpu_nb); 298 if (err) { 299 pr_warn("global-timer: unable to register cpu notifier.\n"); 300 goto out_irq; 301 } 302 303 /* Immediately configure the timer on the boot CPU */ 304 gt_clocksource_init(); 305 gt_clockevents_init(this_cpu_ptr(gt_evt)); 306 307 return; 308 309 out_irq: 310 free_percpu_irq(gt_ppi, gt_evt); 311 out_free: 312 free_percpu(gt_evt); 313 out_clk: 314 clk_disable_unprepare(gt_clk); 315 out_unmap: 316 iounmap(gt_base); 317 WARN(err, "ARM Global timer register failed (%d)\n", err); 318 } 319 320 /* Only tested on r2p2 and r3p0 */ 321 CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer", 322 global_timer_of_register); 323