1 /*
2  * drivers/clocksource/arm_global_timer.c
3  *
4  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5  * Author: Stuart Menefy <stuart.menefy@st.com>
6  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/clocksource.h>
16 #include <linux/clockchips.h>
17 #include <linux/cpu.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/sched_clock.h>
25 
26 #include <asm/cputype.h>
27 
28 #define GT_COUNTER0	0x00
29 #define GT_COUNTER1	0x04
30 
31 #define GT_CONTROL	0x08
32 #define GT_CONTROL_TIMER_ENABLE		BIT(0)  /* this bit is NOT banked */
33 #define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
34 #define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
35 #define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
36 
37 #define GT_INT_STATUS	0x0c
38 #define GT_INT_STATUS_EVENT_FLAG	BIT(0)
39 
40 #define GT_COMP0	0x10
41 #define GT_COMP1	0x14
42 #define GT_AUTO_INC	0x18
43 
44 /*
45  * We are expecting to be clocked by the ARM peripheral clock.
46  *
47  * Note: it is assumed we are using a prescaler value of zero, so this is
48  * the units for all operations.
49  */
50 static void __iomem *gt_base;
51 static unsigned long gt_clk_rate;
52 static int gt_ppi;
53 static struct clock_event_device __percpu *gt_evt;
54 
55 /*
56  * To get the value from the Global Timer Counter register proceed as follows:
57  * 1. Read the upper 32-bit timer counter register
58  * 2. Read the lower 32-bit timer counter register
59  * 3. Read the upper 32-bit timer counter register again. If the value is
60  *  different to the 32-bit upper value read previously, go back to step 2.
61  *  Otherwise the 64-bit timer counter value is correct.
62  */
63 static u64 gt_counter_read(void)
64 {
65 	u64 counter;
66 	u32 lower;
67 	u32 upper, old_upper;
68 
69 	upper = readl_relaxed(gt_base + GT_COUNTER1);
70 	do {
71 		old_upper = upper;
72 		lower = readl_relaxed(gt_base + GT_COUNTER0);
73 		upper = readl_relaxed(gt_base + GT_COUNTER1);
74 	} while (upper != old_upper);
75 
76 	counter = upper;
77 	counter <<= 32;
78 	counter |= lower;
79 	return counter;
80 }
81 
82 /**
83  * To ensure that updates to comparator value register do not set the
84  * Interrupt Status Register proceed as follows:
85  * 1. Clear the Comp Enable bit in the Timer Control Register.
86  * 2. Write the lower 32-bit Comparator Value Register.
87  * 3. Write the upper 32-bit Comparator Value Register.
88  * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
89  */
90 static void gt_compare_set(unsigned long delta, int periodic)
91 {
92 	u64 counter = gt_counter_read();
93 	unsigned long ctrl;
94 
95 	counter += delta;
96 	ctrl = GT_CONTROL_TIMER_ENABLE;
97 	writel(ctrl, gt_base + GT_CONTROL);
98 	writel(lower_32_bits(counter), gt_base + GT_COMP0);
99 	writel(upper_32_bits(counter), gt_base + GT_COMP1);
100 
101 	if (periodic) {
102 		writel(delta, gt_base + GT_AUTO_INC);
103 		ctrl |= GT_CONTROL_AUTO_INC;
104 	}
105 
106 	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
107 	writel(ctrl, gt_base + GT_CONTROL);
108 }
109 
110 static int gt_clockevent_shutdown(struct clock_event_device *evt)
111 {
112 	unsigned long ctrl;
113 
114 	ctrl = readl(gt_base + GT_CONTROL);
115 	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
116 		  GT_CONTROL_AUTO_INC);
117 	writel(ctrl, gt_base + GT_CONTROL);
118 	return 0;
119 }
120 
121 static int gt_clockevent_set_periodic(struct clock_event_device *evt)
122 {
123 	gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
124 	return 0;
125 }
126 
127 static int gt_clockevent_set_next_event(unsigned long evt,
128 					struct clock_event_device *unused)
129 {
130 	gt_compare_set(evt, 0);
131 	return 0;
132 }
133 
134 static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
135 {
136 	struct clock_event_device *evt = dev_id;
137 
138 	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
139 				GT_INT_STATUS_EVENT_FLAG))
140 		return IRQ_NONE;
141 
142 	/**
143 	 * ERRATA 740657( Global Timer can send 2 interrupts for
144 	 * the same event in single-shot mode)
145 	 * Workaround:
146 	 *	Either disable single-shot mode.
147 	 *	Or
148 	 *	Modify the Interrupt Handler to avoid the
149 	 *	offending sequence. This is achieved by clearing
150 	 *	the Global Timer flag _after_ having incremented
151 	 *	the Comparator register	value to a higher value.
152 	 */
153 	if (clockevent_state_oneshot(evt))
154 		gt_compare_set(ULONG_MAX, 0);
155 
156 	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
157 	evt->event_handler(evt);
158 
159 	return IRQ_HANDLED;
160 }
161 
162 static int gt_clockevents_init(struct clock_event_device *clk)
163 {
164 	int cpu = smp_processor_id();
165 
166 	clk->name = "arm_global_timer";
167 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
168 		CLOCK_EVT_FEAT_PERCPU;
169 	clk->set_state_shutdown = gt_clockevent_shutdown;
170 	clk->set_state_periodic = gt_clockevent_set_periodic;
171 	clk->set_state_oneshot = gt_clockevent_shutdown;
172 	clk->set_next_event = gt_clockevent_set_next_event;
173 	clk->cpumask = cpumask_of(cpu);
174 	clk->rating = 300;
175 	clk->irq = gt_ppi;
176 	clockevents_config_and_register(clk, gt_clk_rate,
177 					1, 0xffffffff);
178 	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
179 	return 0;
180 }
181 
182 static void gt_clockevents_stop(struct clock_event_device *clk)
183 {
184 	gt_clockevent_shutdown(clk);
185 	disable_percpu_irq(clk->irq);
186 }
187 
188 static cycle_t gt_clocksource_read(struct clocksource *cs)
189 {
190 	return gt_counter_read();
191 }
192 
193 static struct clocksource gt_clocksource = {
194 	.name	= "arm_global_timer",
195 	.rating	= 300,
196 	.read	= gt_clocksource_read,
197 	.mask	= CLOCKSOURCE_MASK(64),
198 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
199 };
200 
201 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
202 static u64 notrace gt_sched_clock_read(void)
203 {
204 	return gt_counter_read();
205 }
206 #endif
207 
208 static void __init gt_clocksource_init(void)
209 {
210 	writel(0, gt_base + GT_CONTROL);
211 	writel(0, gt_base + GT_COUNTER0);
212 	writel(0, gt_base + GT_COUNTER1);
213 	/* enables timer on all the cores */
214 	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
215 
216 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
217 	sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
218 #endif
219 	clocksource_register_hz(&gt_clocksource, gt_clk_rate);
220 }
221 
222 static int gt_cpu_notify(struct notifier_block *self, unsigned long action,
223 			 void *hcpu)
224 {
225 	switch (action & ~CPU_TASKS_FROZEN) {
226 	case CPU_STARTING:
227 		gt_clockevents_init(this_cpu_ptr(gt_evt));
228 		break;
229 	case CPU_DYING:
230 		gt_clockevents_stop(this_cpu_ptr(gt_evt));
231 		break;
232 	}
233 
234 	return NOTIFY_OK;
235 }
236 static struct notifier_block gt_cpu_nb = {
237 	.notifier_call = gt_cpu_notify,
238 };
239 
240 static void __init global_timer_of_register(struct device_node *np)
241 {
242 	struct clk *gt_clk;
243 	int err = 0;
244 
245 	/*
246 	 * In A9 r2p0 the comparators for each processor with the global timer
247 	 * fire when the timer value is greater than or equal to. In previous
248 	 * revisions the comparators fired when the timer value was equal to.
249 	 */
250 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
251 	    && (read_cpuid_id() & 0xf0000f) < 0x200000) {
252 		pr_warn("global-timer: non support for this cpu version.\n");
253 		return;
254 	}
255 
256 	gt_ppi = irq_of_parse_and_map(np, 0);
257 	if (!gt_ppi) {
258 		pr_warn("global-timer: unable to parse irq\n");
259 		return;
260 	}
261 
262 	gt_base = of_iomap(np, 0);
263 	if (!gt_base) {
264 		pr_warn("global-timer: invalid base address\n");
265 		return;
266 	}
267 
268 	gt_clk = of_clk_get(np, 0);
269 	if (!IS_ERR(gt_clk)) {
270 		err = clk_prepare_enable(gt_clk);
271 		if (err)
272 			goto out_unmap;
273 	} else {
274 		pr_warn("global-timer: clk not found\n");
275 		err = -EINVAL;
276 		goto out_unmap;
277 	}
278 
279 	gt_clk_rate = clk_get_rate(gt_clk);
280 	gt_evt = alloc_percpu(struct clock_event_device);
281 	if (!gt_evt) {
282 		pr_warn("global-timer: can't allocate memory\n");
283 		err = -ENOMEM;
284 		goto out_clk;
285 	}
286 
287 	err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
288 				 "gt", gt_evt);
289 	if (err) {
290 		pr_warn("global-timer: can't register interrupt %d (%d)\n",
291 			gt_ppi, err);
292 		goto out_free;
293 	}
294 
295 	err = register_cpu_notifier(&gt_cpu_nb);
296 	if (err) {
297 		pr_warn("global-timer: unable to register cpu notifier.\n");
298 		goto out_irq;
299 	}
300 
301 	/* Immediately configure the timer on the boot CPU */
302 	gt_clocksource_init();
303 	gt_clockevents_init(this_cpu_ptr(gt_evt));
304 
305 	return;
306 
307 out_irq:
308 	free_percpu_irq(gt_ppi, gt_evt);
309 out_free:
310 	free_percpu(gt_evt);
311 out_clk:
312 	clk_disable_unprepare(gt_clk);
313 out_unmap:
314 	iounmap(gt_base);
315 	WARN(err, "ARM Global timer register failed (%d)\n", err);
316 }
317 
318 /* Only tested on r2p2 and r3p0  */
319 CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
320 			global_timer_of_register);
321