1 /* 2 * drivers/clocksource/arm_global_timer.c 3 * 4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 5 * Author: Stuart Menefy <stuart.menefy@st.com> 6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/clocksource.h> 16 #include <linux/clockchips.h> 17 #include <linux/cpu.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_address.h> 25 #include <linux/sched_clock.h> 26 27 #include <asm/cputype.h> 28 29 #define GT_COUNTER0 0x00 30 #define GT_COUNTER1 0x04 31 32 #define GT_CONTROL 0x08 33 #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ 34 #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ 35 #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ 36 #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ 37 38 #define GT_INT_STATUS 0x0c 39 #define GT_INT_STATUS_EVENT_FLAG BIT(0) 40 41 #define GT_COMP0 0x10 42 #define GT_COMP1 0x14 43 #define GT_AUTO_INC 0x18 44 45 /* 46 * We are expecting to be clocked by the ARM peripheral clock. 47 * 48 * Note: it is assumed we are using a prescaler value of zero, so this is 49 * the units for all operations. 50 */ 51 static void __iomem *gt_base; 52 static unsigned long gt_clk_rate; 53 static int gt_ppi; 54 static struct clock_event_device __percpu *gt_evt; 55 56 /* 57 * To get the value from the Global Timer Counter register proceed as follows: 58 * 1. Read the upper 32-bit timer counter register 59 * 2. Read the lower 32-bit timer counter register 60 * 3. Read the upper 32-bit timer counter register again. If the value is 61 * different to the 32-bit upper value read previously, go back to step 2. 62 * Otherwise the 64-bit timer counter value is correct. 63 */ 64 static u64 notrace _gt_counter_read(void) 65 { 66 u64 counter; 67 u32 lower; 68 u32 upper, old_upper; 69 70 upper = readl_relaxed(gt_base + GT_COUNTER1); 71 do { 72 old_upper = upper; 73 lower = readl_relaxed(gt_base + GT_COUNTER0); 74 upper = readl_relaxed(gt_base + GT_COUNTER1); 75 } while (upper != old_upper); 76 77 counter = upper; 78 counter <<= 32; 79 counter |= lower; 80 return counter; 81 } 82 83 static u64 gt_counter_read(void) 84 { 85 return _gt_counter_read(); 86 } 87 88 /** 89 * To ensure that updates to comparator value register do not set the 90 * Interrupt Status Register proceed as follows: 91 * 1. Clear the Comp Enable bit in the Timer Control Register. 92 * 2. Write the lower 32-bit Comparator Value Register. 93 * 3. Write the upper 32-bit Comparator Value Register. 94 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. 95 */ 96 static void gt_compare_set(unsigned long delta, int periodic) 97 { 98 u64 counter = gt_counter_read(); 99 unsigned long ctrl; 100 101 counter += delta; 102 ctrl = GT_CONTROL_TIMER_ENABLE; 103 writel_relaxed(ctrl, gt_base + GT_CONTROL); 104 writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0); 105 writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1); 106 107 if (periodic) { 108 writel_relaxed(delta, gt_base + GT_AUTO_INC); 109 ctrl |= GT_CONTROL_AUTO_INC; 110 } 111 112 ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE; 113 writel_relaxed(ctrl, gt_base + GT_CONTROL); 114 } 115 116 static int gt_clockevent_shutdown(struct clock_event_device *evt) 117 { 118 unsigned long ctrl; 119 120 ctrl = readl(gt_base + GT_CONTROL); 121 ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE | 122 GT_CONTROL_AUTO_INC); 123 writel(ctrl, gt_base + GT_CONTROL); 124 return 0; 125 } 126 127 static int gt_clockevent_set_periodic(struct clock_event_device *evt) 128 { 129 gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1); 130 return 0; 131 } 132 133 static int gt_clockevent_set_next_event(unsigned long evt, 134 struct clock_event_device *unused) 135 { 136 gt_compare_set(evt, 0); 137 return 0; 138 } 139 140 static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id) 141 { 142 struct clock_event_device *evt = dev_id; 143 144 if (!(readl_relaxed(gt_base + GT_INT_STATUS) & 145 GT_INT_STATUS_EVENT_FLAG)) 146 return IRQ_NONE; 147 148 /** 149 * ERRATA 740657( Global Timer can send 2 interrupts for 150 * the same event in single-shot mode) 151 * Workaround: 152 * Either disable single-shot mode. 153 * Or 154 * Modify the Interrupt Handler to avoid the 155 * offending sequence. This is achieved by clearing 156 * the Global Timer flag _after_ having incremented 157 * the Comparator register value to a higher value. 158 */ 159 if (clockevent_state_oneshot(evt)) 160 gt_compare_set(ULONG_MAX, 0); 161 162 writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS); 163 evt->event_handler(evt); 164 165 return IRQ_HANDLED; 166 } 167 168 static int gt_clockevents_init(struct clock_event_device *clk) 169 { 170 int cpu = smp_processor_id(); 171 172 clk->name = "arm_global_timer"; 173 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | 174 CLOCK_EVT_FEAT_PERCPU; 175 clk->set_state_shutdown = gt_clockevent_shutdown; 176 clk->set_state_periodic = gt_clockevent_set_periodic; 177 clk->set_state_oneshot = gt_clockevent_shutdown; 178 clk->set_state_oneshot_stopped = gt_clockevent_shutdown; 179 clk->set_next_event = gt_clockevent_set_next_event; 180 clk->cpumask = cpumask_of(cpu); 181 clk->rating = 300; 182 clk->irq = gt_ppi; 183 clockevents_config_and_register(clk, gt_clk_rate, 184 1, 0xffffffff); 185 enable_percpu_irq(clk->irq, IRQ_TYPE_NONE); 186 return 0; 187 } 188 189 static void gt_clockevents_stop(struct clock_event_device *clk) 190 { 191 gt_clockevent_shutdown(clk); 192 disable_percpu_irq(clk->irq); 193 } 194 195 static cycle_t gt_clocksource_read(struct clocksource *cs) 196 { 197 return gt_counter_read(); 198 } 199 200 static void gt_resume(struct clocksource *cs) 201 { 202 unsigned long ctrl; 203 204 ctrl = readl(gt_base + GT_CONTROL); 205 if (!(ctrl & GT_CONTROL_TIMER_ENABLE)) 206 /* re-enable timer on resume */ 207 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); 208 } 209 210 static struct clocksource gt_clocksource = { 211 .name = "arm_global_timer", 212 .rating = 300, 213 .read = gt_clocksource_read, 214 .mask = CLOCKSOURCE_MASK(64), 215 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 216 .resume = gt_resume, 217 }; 218 219 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK 220 static u64 notrace gt_sched_clock_read(void) 221 { 222 return _gt_counter_read(); 223 } 224 #endif 225 226 static unsigned long gt_read_long(void) 227 { 228 return readl_relaxed(gt_base + GT_COUNTER0); 229 } 230 231 static struct delay_timer gt_delay_timer = { 232 .read_current_timer = gt_read_long, 233 }; 234 235 static void __init gt_delay_timer_init(void) 236 { 237 gt_delay_timer.freq = gt_clk_rate; 238 register_current_timer_delay(>_delay_timer); 239 } 240 241 static void __init gt_clocksource_init(void) 242 { 243 writel(0, gt_base + GT_CONTROL); 244 writel(0, gt_base + GT_COUNTER0); 245 writel(0, gt_base + GT_COUNTER1); 246 /* enables timer on all the cores */ 247 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); 248 249 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK 250 sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate); 251 #endif 252 clocksource_register_hz(>_clocksource, gt_clk_rate); 253 } 254 255 static int gt_cpu_notify(struct notifier_block *self, unsigned long action, 256 void *hcpu) 257 { 258 switch (action & ~CPU_TASKS_FROZEN) { 259 case CPU_STARTING: 260 gt_clockevents_init(this_cpu_ptr(gt_evt)); 261 break; 262 case CPU_DYING: 263 gt_clockevents_stop(this_cpu_ptr(gt_evt)); 264 break; 265 } 266 267 return NOTIFY_OK; 268 } 269 static struct notifier_block gt_cpu_nb = { 270 .notifier_call = gt_cpu_notify, 271 }; 272 273 static void __init global_timer_of_register(struct device_node *np) 274 { 275 struct clk *gt_clk; 276 int err = 0; 277 278 /* 279 * In A9 r2p0 the comparators for each processor with the global timer 280 * fire when the timer value is greater than or equal to. In previous 281 * revisions the comparators fired when the timer value was equal to. 282 */ 283 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9 284 && (read_cpuid_id() & 0xf0000f) < 0x200000) { 285 pr_warn("global-timer: non support for this cpu version.\n"); 286 return; 287 } 288 289 gt_ppi = irq_of_parse_and_map(np, 0); 290 if (!gt_ppi) { 291 pr_warn("global-timer: unable to parse irq\n"); 292 return; 293 } 294 295 gt_base = of_iomap(np, 0); 296 if (!gt_base) { 297 pr_warn("global-timer: invalid base address\n"); 298 return; 299 } 300 301 gt_clk = of_clk_get(np, 0); 302 if (!IS_ERR(gt_clk)) { 303 err = clk_prepare_enable(gt_clk); 304 if (err) 305 goto out_unmap; 306 } else { 307 pr_warn("global-timer: clk not found\n"); 308 err = -EINVAL; 309 goto out_unmap; 310 } 311 312 gt_clk_rate = clk_get_rate(gt_clk); 313 gt_evt = alloc_percpu(struct clock_event_device); 314 if (!gt_evt) { 315 pr_warn("global-timer: can't allocate memory\n"); 316 err = -ENOMEM; 317 goto out_clk; 318 } 319 320 err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt, 321 "gt", gt_evt); 322 if (err) { 323 pr_warn("global-timer: can't register interrupt %d (%d)\n", 324 gt_ppi, err); 325 goto out_free; 326 } 327 328 err = register_cpu_notifier(>_cpu_nb); 329 if (err) { 330 pr_warn("global-timer: unable to register cpu notifier.\n"); 331 goto out_irq; 332 } 333 334 /* Immediately configure the timer on the boot CPU */ 335 gt_clocksource_init(); 336 gt_clockevents_init(this_cpu_ptr(gt_evt)); 337 gt_delay_timer_init(); 338 339 return; 340 341 out_irq: 342 free_percpu_irq(gt_ppi, gt_evt); 343 out_free: 344 free_percpu(gt_evt); 345 out_clk: 346 clk_disable_unprepare(gt_clk); 347 out_unmap: 348 iounmap(gt_base); 349 WARN(err, "ARM Global timer register failed (%d)\n", err); 350 } 351 352 /* Only tested on r2p2 and r3p0 */ 353 CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer", 354 global_timer_of_register); 355