1 /*
2  * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9 
10 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
11  * programmed to go from @count to @limit and optionally interrupt.
12  * We've designated TIMER0 for clockevents and TIMER1 for clocksource
13  *
14  * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
15  * which are suitable for UP and SMP based clocksources respectively
16  */
17 
18 #include <linux/interrupt.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/clocksource.h>
22 #include <linux/clockchips.h>
23 #include <linux/cpu.h>
24 #include <linux/of.h>
25 #include <linux/of_irq.h>
26 
27 #include <soc/arc/timers.h>
28 #include <soc/arc/mcip.h>
29 
30 
31 static unsigned long arc_timer_freq;
32 
33 static int noinline arc_get_timer_clk(struct device_node *node)
34 {
35 	struct clk *clk;
36 	int ret;
37 
38 	clk = of_clk_get(node, 0);
39 	if (IS_ERR(clk)) {
40 		pr_err("timer missing clk\n");
41 		return PTR_ERR(clk);
42 	}
43 
44 	ret = clk_prepare_enable(clk);
45 	if (ret) {
46 		pr_err("Couldn't enable parent clk\n");
47 		return ret;
48 	}
49 
50 	arc_timer_freq = clk_get_rate(clk);
51 
52 	return 0;
53 }
54 
55 /********** Clock Source Device *********/
56 
57 #ifdef CONFIG_ARC_TIMERS_64BIT
58 
59 static u64 arc_read_gfrc(struct clocksource *cs)
60 {
61 	unsigned long flags;
62 	u32 l, h;
63 
64 	local_irq_save(flags);
65 
66 	__mcip_cmd(CMD_GFRC_READ_LO, 0);
67 	l = read_aux_reg(ARC_REG_MCIP_READBACK);
68 
69 	__mcip_cmd(CMD_GFRC_READ_HI, 0);
70 	h = read_aux_reg(ARC_REG_MCIP_READBACK);
71 
72 	local_irq_restore(flags);
73 
74 	return (((u64)h) << 32) | l;
75 }
76 
77 static struct clocksource arc_counter_gfrc = {
78 	.name   = "ARConnect GFRC",
79 	.rating = 400,
80 	.read   = arc_read_gfrc,
81 	.mask   = CLOCKSOURCE_MASK(64),
82 	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
83 };
84 
85 static int __init arc_cs_setup_gfrc(struct device_node *node)
86 {
87 	struct mcip_bcr mp;
88 	int ret;
89 
90 	READ_BCR(ARC_REG_MCIP_BCR, mp);
91 	if (!mp.gfrc) {
92 		pr_warn("Global-64-bit-Ctr clocksource not detected\n");
93 		return -ENXIO;
94 	}
95 
96 	ret = arc_get_timer_clk(node);
97 	if (ret)
98 		return ret;
99 
100 	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
101 }
102 TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
103 
104 #define AUX_RTC_CTRL	0x103
105 #define AUX_RTC_LOW	0x104
106 #define AUX_RTC_HIGH	0x105
107 
108 static u64 arc_read_rtc(struct clocksource *cs)
109 {
110 	unsigned long status;
111 	u32 l, h;
112 
113 	/*
114 	 * hardware has an internal state machine which tracks readout of
115 	 * low/high and updates the CTRL.status if
116 	 *  - interrupt/exception taken between the two reads
117 	 *  - high increments after low has been read
118 	 */
119 	do {
120 		l = read_aux_reg(AUX_RTC_LOW);
121 		h = read_aux_reg(AUX_RTC_HIGH);
122 		status = read_aux_reg(AUX_RTC_CTRL);
123 	} while (!(status & _BITUL(31)));
124 
125 	return (((u64)h) << 32) | l;
126 }
127 
128 static struct clocksource arc_counter_rtc = {
129 	.name   = "ARCv2 RTC",
130 	.rating = 350,
131 	.read   = arc_read_rtc,
132 	.mask   = CLOCKSOURCE_MASK(64),
133 	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
134 };
135 
136 static int __init arc_cs_setup_rtc(struct device_node *node)
137 {
138 	struct bcr_timer timer;
139 	int ret;
140 
141 	READ_BCR(ARC_REG_TIMERS_BCR, timer);
142 	if (!timer.rtc) {
143 		pr_warn("Local-64-bit-Ctr clocksource not detected\n");
144 		return -ENXIO;
145 	}
146 
147 	/* Local to CPU hence not usable in SMP */
148 	if (IS_ENABLED(CONFIG_SMP)) {
149 		pr_warn("Local-64-bit-Ctr not usable in SMP\n");
150 		return -EINVAL;
151 	}
152 
153 	ret = arc_get_timer_clk(node);
154 	if (ret)
155 		return ret;
156 
157 	write_aux_reg(AUX_RTC_CTRL, 1);
158 
159 	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
160 }
161 TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
162 
163 #endif
164 
165 /*
166  * 32bit TIMER1 to keep counting monotonically and wraparound
167  */
168 
169 static u64 arc_read_timer1(struct clocksource *cs)
170 {
171 	return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
172 }
173 
174 static struct clocksource arc_counter_timer1 = {
175 	.name   = "ARC Timer1",
176 	.rating = 300,
177 	.read   = arc_read_timer1,
178 	.mask   = CLOCKSOURCE_MASK(32),
179 	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
180 };
181 
182 static int __init arc_cs_setup_timer1(struct device_node *node)
183 {
184 	int ret;
185 
186 	/* Local to CPU hence not usable in SMP */
187 	if (IS_ENABLED(CONFIG_SMP))
188 		return -EINVAL;
189 
190 	ret = arc_get_timer_clk(node);
191 	if (ret)
192 		return ret;
193 
194 	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
195 	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
196 	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
197 
198 	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
199 }
200 
201 /********** Clock Event Device *********/
202 
203 static int arc_timer_irq;
204 
205 /*
206  * Arm the timer to interrupt after @cycles
207  * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
208  */
209 static void arc_timer_event_setup(unsigned int cycles)
210 {
211 	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
212 	write_aux_reg(ARC_REG_TIMER0_CNT, 0);	/* start from 0 */
213 
214 	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
215 }
216 
217 
218 static int arc_clkevent_set_next_event(unsigned long delta,
219 				       struct clock_event_device *dev)
220 {
221 	arc_timer_event_setup(delta);
222 	return 0;
223 }
224 
225 static int arc_clkevent_set_periodic(struct clock_event_device *dev)
226 {
227 	/*
228 	 * At X Hz, 1 sec = 1000ms -> X cycles;
229 	 *		      10ms -> X / 100 cycles
230 	 */
231 	arc_timer_event_setup(arc_timer_freq / HZ);
232 	return 0;
233 }
234 
235 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
236 	.name			= "ARC Timer0",
237 	.features		= CLOCK_EVT_FEAT_ONESHOT |
238 				  CLOCK_EVT_FEAT_PERIODIC,
239 	.rating			= 300,
240 	.set_next_event		= arc_clkevent_set_next_event,
241 	.set_state_periodic	= arc_clkevent_set_periodic,
242 };
243 
244 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
245 {
246 	/*
247 	 * Note that generic IRQ core could have passed @evt for @dev_id if
248 	 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
249 	 */
250 	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
251 	int irq_reenable = clockevent_state_periodic(evt);
252 
253 	/*
254 	 * Any write to CTRL reg ACks the interrupt, we rewrite the
255 	 * Count when [N]ot [H]alted bit.
256 	 * And re-arm it if perioid by [I]nterrupt [E]nable bit
257 	 */
258 	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
259 
260 	evt->event_handler(evt);
261 
262 	return IRQ_HANDLED;
263 }
264 
265 
266 static int arc_timer_starting_cpu(unsigned int cpu)
267 {
268 	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
269 
270 	evt->cpumask = cpumask_of(smp_processor_id());
271 
272 	clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
273 	enable_percpu_irq(arc_timer_irq, 0);
274 	return 0;
275 }
276 
277 static int arc_timer_dying_cpu(unsigned int cpu)
278 {
279 	disable_percpu_irq(arc_timer_irq);
280 	return 0;
281 }
282 
283 /*
284  * clockevent setup for boot CPU
285  */
286 static int __init arc_clockevent_setup(struct device_node *node)
287 {
288 	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
289 	int ret;
290 
291 	arc_timer_irq = irq_of_parse_and_map(node, 0);
292 	if (arc_timer_irq <= 0) {
293 		pr_err("clockevent: missing irq\n");
294 		return -EINVAL;
295 	}
296 
297 	ret = arc_get_timer_clk(node);
298 	if (ret) {
299 		pr_err("clockevent: missing clk\n");
300 		return ret;
301 	}
302 
303 	/* Needs apriori irq_set_percpu_devid() done in intc map function */
304 	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
305 				 "Timer0 (per-cpu-tick)", evt);
306 	if (ret) {
307 		pr_err("clockevent: unable to request irq\n");
308 		return ret;
309 	}
310 
311 	ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
312 				"clockevents/arc/timer:starting",
313 				arc_timer_starting_cpu,
314 				arc_timer_dying_cpu);
315 	if (ret) {
316 		pr_err("Failed to setup hotplug state\n");
317 		return ret;
318 	}
319 	return 0;
320 }
321 
322 static int __init arc_of_timer_init(struct device_node *np)
323 {
324 	static int init_count = 0;
325 	int ret;
326 
327 	if (!init_count) {
328 		init_count = 1;
329 		ret = arc_clockevent_setup(np);
330 	} else {
331 		ret = arc_cs_setup_timer1(np);
332 	}
333 
334 	return ret;
335 }
336 TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
337