1ae278a93SStephen Warrenconfig CLKSRC_OF 2ae278a93SStephen Warren bool 3ae278a93SStephen Warren 489c0b8e2SRussell Kingconfig CLKSRC_I8253 589c0b8e2SRussell King bool 6442c8176SRussell King 7e6220bdcSThomas Gleixnerconfig CLKEVT_I8253 8e6220bdcSThomas Gleixner bool 9e6220bdcSThomas Gleixner 1015f304b6SRalf Baechleconfig I8253_LOCK 1115f304b6SRalf Baechle bool 1215f304b6SRalf Baechle 1315f304b6SRalf Baechleconfig CLKBLD_I8253 14e6220bdcSThomas Gleixner def_bool y if CLKSRC_I8253 || CLKEVT_I8253 || I8253_LOCK 1515f304b6SRalf Baechle 16442c8176SRussell Kingconfig CLKSRC_MMIO 17442c8176SRussell King bool 1806c3df49SJamie Iles 1906c3df49SJamie Ilesconfig DW_APB_TIMER 2006c3df49SJamie Iles bool 21489bcceaSMattias Wallin 22cfda5901SDinh Nguyenconfig DW_APB_TIMER_OF 23cfda5901SDinh Nguyen bool 24cfda5901SDinh Nguyen 256fe9cbd1SGregory CLEMENTconfig ARMADA_370_XP_TIMER 266fe9cbd1SGregory CLEMENT bool 276fe9cbd1SGregory CLEMENT 28b2ac5d75SMaxime Ripardconfig SUNXI_TIMER 29b2ac5d75SMaxime Ripard bool 30b2ac5d75SMaxime Ripard 31ff7ec345STony Priskconfig VT8500_TIMER 32ff7ec345STony Prisk bool 33ff7ec345STony Prisk 344f0f234fSMichal Simekconfig CADENCE_TTC_TIMER 354f0f234fSMichal Simek bool 364f0f234fSMichal Simek 37694e33a7SLinus Walleijconfig CLKSRC_NOMADIK_MTU 38694e33a7SLinus Walleij bool 39694e33a7SLinus Walleij depends on (ARCH_NOMADIK || ARCH_U8500) 40694e33a7SLinus Walleij select CLKSRC_MMIO 41694e33a7SLinus Walleij help 42694e33a7SLinus Walleij Support for Multi Timer Unit. MTU provides access 43694e33a7SLinus Walleij to multiple interrupt generating programmable 44694e33a7SLinus Walleij 32-bit free running decrementing counters. 45694e33a7SLinus Walleij 46694e33a7SLinus Walleijconfig CLKSRC_NOMADIK_MTU_SCHED_CLOCK 47694e33a7SLinus Walleij bool 48694e33a7SLinus Walleij depends on CLKSRC_NOMADIK_MTU 49694e33a7SLinus Walleij help 50694e33a7SLinus Walleij Use the Multi Timer Unit as the sched_clock. 51694e33a7SLinus Walleij 52489bcceaSMattias Wallinconfig CLKSRC_DBX500_PRCMU 53489bcceaSMattias Wallin bool "Clocksource PRCMU Timer" 5429746f48SLinus Walleij depends on UX500_SOC_DB8500 55489bcceaSMattias Wallin default y 56489bcceaSMattias Wallin help 57489bcceaSMattias Wallin Use the always on PRCMU Timer as clocksource 58489bcceaSMattias Wallin 59489bcceaSMattias Wallinconfig CLKSRC_DBX500_PRCMU_SCHED_CLOCK 60489bcceaSMattias Wallin bool "Clocksource PRCMU Timer sched_clock" 61694e33a7SLinus Walleij depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK) 62489bcceaSMattias Wallin default y 63489bcceaSMattias Wallin help 64489bcceaSMattias Wallin Use the always on PRCMU Timer as sched_clock 65985c0679SMarc Zyngier 668a4da6e3SMark Rutlandconfig ARM_ARCH_TIMER 678a4da6e3SMark Rutland bool 68a2c5d4edSJames Hogan 69a2c5d4edSJames Hoganconfig CLKSRC_METAG_GENERIC 70a2c5d4edSJames Hogan def_bool y if METAG 71a2c5d4edSJames Hogan help 72a2c5d4edSJames Hogan This option enables support for the Meta per-thread timers. 736938d75aSThomas Abraham 746938d75aSThomas Abrahamconfig CLKSRC_EXYNOS_MCT 756938d75aSThomas Abraham def_bool y if ARCH_EXYNOS 766938d75aSThomas Abraham help 776938d75aSThomas Abraham Support for Multi Core Timer controller on Exynos SoCs. 78241a9871SArnd Bergmann 79f1189989STomasz Figaconfig CLKSRC_SAMSUNG_PWM 8077d84434STomasz Figa bool 81f1189989STomasz Figa select CLKSRC_MMIO 82f1189989STomasz Figa help 83f1189989STomasz Figa This is a new clocksource driver for the PWM timer found in 84f1189989STomasz Figa Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver 85f1189989STomasz Figa for all devicetree enabled platforms. This driver will be 86f1189989STomasz Figa needed only on systems that do not have the Exynos MCT available. 87