1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC PLL driver 4 * 5 * Copyright (C) 2016-2018 Xilinx 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/slab.h> 11 #include "clk-zynqmp.h" 12 13 /** 14 * struct zynqmp_pll - PLL clock 15 * @hw: Handle between common and hardware-specific interfaces 16 * @clk_id: PLL clock ID 17 */ 18 struct zynqmp_pll { 19 struct clk_hw hw; 20 u32 clk_id; 21 }; 22 23 #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw) 24 25 #define PLL_FBDIV_MIN 25 26 #define PLL_FBDIV_MAX 125 27 28 #define PS_PLL_VCO_MIN 1500000000 29 #define PS_PLL_VCO_MAX 3000000000UL 30 31 enum pll_mode { 32 PLL_MODE_INT, 33 PLL_MODE_FRAC, 34 }; 35 36 #define FRAC_OFFSET 0x8 37 #define PLLFCFG_FRAC_EN BIT(31) 38 #define FRAC_DIV BIT(16) /* 2^16 */ 39 40 /** 41 * zynqmp_pll_get_mode() - Get mode of PLL 42 * @hw: Handle between common and hardware-specific interfaces 43 * 44 * Return: Mode of PLL 45 */ 46 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) 47 { 48 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 49 u32 clk_id = clk->clk_id; 50 const char *clk_name = clk_hw_get_name(hw); 51 u32 ret_payload[PAYLOAD_ARG_CNT]; 52 int ret; 53 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 54 55 ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0, 56 ret_payload); 57 if (ret) 58 pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n", 59 __func__, clk_name, ret); 60 61 return ret_payload[1]; 62 } 63 64 /** 65 * zynqmp_pll_set_mode() - Set the PLL mode 66 * @hw: Handle between common and hardware-specific interfaces 67 * @on: Flag to determine the mode 68 */ 69 static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) 70 { 71 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 72 u32 clk_id = clk->clk_id; 73 const char *clk_name = clk_hw_get_name(hw); 74 int ret; 75 u32 mode; 76 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 77 78 if (on) 79 mode = PLL_MODE_FRAC; 80 else 81 mode = PLL_MODE_INT; 82 83 ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL); 84 if (ret) 85 pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", 86 __func__, clk_name, ret); 87 } 88 89 /** 90 * zynqmp_pll_round_rate() - Round a clock frequency 91 * @hw: Handle between common and hardware-specific interfaces 92 * @rate: Desired clock frequency 93 * @prate: Clock frequency of parent clock 94 * 95 * Return: Frequency closest to @rate the hardware can generate 96 */ 97 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, 98 unsigned long *prate) 99 { 100 u32 fbdiv; 101 long rate_div, f; 102 103 /* Enable the fractional mode if needed */ 104 rate_div = (rate * FRAC_DIV) / *prate; 105 f = rate_div % FRAC_DIV; 106 zynqmp_pll_set_mode(hw, !!f); 107 108 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { 109 if (rate > PS_PLL_VCO_MAX) { 110 fbdiv = rate / PS_PLL_VCO_MAX; 111 rate = rate / (fbdiv + 1); 112 } 113 if (rate < PS_PLL_VCO_MIN) { 114 fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); 115 rate = rate * fbdiv; 116 } 117 return rate; 118 } 119 120 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); 121 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); 122 return *prate * fbdiv; 123 } 124 125 /** 126 * zynqmp_pll_recalc_rate() - Recalculate clock frequency 127 * @hw: Handle between common and hardware-specific interfaces 128 * @parent_rate: Clock frequency of parent clock 129 * 130 * Return: Current clock frequency 131 */ 132 static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, 133 unsigned long parent_rate) 134 { 135 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 136 u32 clk_id = clk->clk_id; 137 const char *clk_name = clk_hw_get_name(hw); 138 u32 fbdiv, data; 139 unsigned long rate, frac; 140 u32 ret_payload[PAYLOAD_ARG_CNT]; 141 int ret; 142 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 143 144 ret = eemi_ops->clock_getdivider(clk_id, &fbdiv); 145 if (ret) 146 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 147 __func__, clk_name, ret); 148 149 rate = parent_rate * fbdiv; 150 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { 151 eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0, 152 ret_payload); 153 data = ret_payload[1]; 154 frac = (parent_rate * data) / FRAC_DIV; 155 rate = rate + frac; 156 } 157 158 return rate; 159 } 160 161 /** 162 * zynqmp_pll_set_rate() - Set rate of PLL 163 * @hw: Handle between common and hardware-specific interfaces 164 * @rate: Frequency of clock to be set 165 * @parent_rate: Clock frequency of parent clock 166 * 167 * Set PLL divider to set desired rate. 168 * 169 * Returns: rate which is set on success else error code 170 */ 171 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, 172 unsigned long parent_rate) 173 { 174 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 175 u32 clk_id = clk->clk_id; 176 const char *clk_name = clk_hw_get_name(hw); 177 u32 fbdiv; 178 long rate_div, frac, m, f; 179 int ret; 180 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 181 182 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { 183 rate_div = (rate * FRAC_DIV) / parent_rate; 184 m = rate_div / FRAC_DIV; 185 f = rate_div % FRAC_DIV; 186 m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX)); 187 rate = parent_rate * m; 188 frac = (parent_rate * f) / FRAC_DIV; 189 190 ret = eemi_ops->clock_setdivider(clk_id, m); 191 if (ret == -EUSERS) 192 WARN(1, "More than allowed devices are using the %s, which is forbidden\n", 193 clk_name); 194 else if (ret) 195 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 196 __func__, clk_name, ret); 197 eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL); 198 199 return rate + frac; 200 } 201 202 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); 203 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); 204 ret = eemi_ops->clock_setdivider(clk_id, fbdiv); 205 if (ret) 206 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 207 __func__, clk_name, ret); 208 209 return parent_rate * fbdiv; 210 } 211 212 /** 213 * zynqmp_pll_is_enabled() - Check if a clock is enabled 214 * @hw: Handle between common and hardware-specific interfaces 215 * 216 * Return: 1 if the clock is enabled, 0 otherwise 217 */ 218 static int zynqmp_pll_is_enabled(struct clk_hw *hw) 219 { 220 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 221 const char *clk_name = clk_hw_get_name(hw); 222 u32 clk_id = clk->clk_id; 223 unsigned int state; 224 int ret; 225 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 226 227 ret = eemi_ops->clock_getstate(clk_id, &state); 228 if (ret) { 229 pr_warn_once("%s() clock get state failed for %s, ret = %d\n", 230 __func__, clk_name, ret); 231 return -EIO; 232 } 233 234 return state ? 1 : 0; 235 } 236 237 /** 238 * zynqmp_pll_enable() - Enable clock 239 * @hw: Handle between common and hardware-specific interfaces 240 * 241 * Return: 0 on success else error code 242 */ 243 static int zynqmp_pll_enable(struct clk_hw *hw) 244 { 245 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 246 const char *clk_name = clk_hw_get_name(hw); 247 u32 clk_id = clk->clk_id; 248 int ret; 249 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 250 251 if (zynqmp_pll_is_enabled(hw)) 252 return 0; 253 254 ret = eemi_ops->clock_enable(clk_id); 255 if (ret) 256 pr_warn_once("%s() clock enable failed for %s, ret = %d\n", 257 __func__, clk_name, ret); 258 259 return ret; 260 } 261 262 /** 263 * zynqmp_pll_disable() - Disable clock 264 * @hw: Handle between common and hardware-specific interfaces 265 */ 266 static void zynqmp_pll_disable(struct clk_hw *hw) 267 { 268 struct zynqmp_pll *clk = to_zynqmp_pll(hw); 269 const char *clk_name = clk_hw_get_name(hw); 270 u32 clk_id = clk->clk_id; 271 int ret; 272 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 273 274 if (!zynqmp_pll_is_enabled(hw)) 275 return; 276 277 ret = eemi_ops->clock_disable(clk_id); 278 if (ret) 279 pr_warn_once("%s() clock disable failed for %s, ret = %d\n", 280 __func__, clk_name, ret); 281 } 282 283 static const struct clk_ops zynqmp_pll_ops = { 284 .enable = zynqmp_pll_enable, 285 .disable = zynqmp_pll_disable, 286 .is_enabled = zynqmp_pll_is_enabled, 287 .round_rate = zynqmp_pll_round_rate, 288 .recalc_rate = zynqmp_pll_recalc_rate, 289 .set_rate = zynqmp_pll_set_rate, 290 }; 291 292 /** 293 * zynqmp_clk_register_pll() - Register PLL with the clock framework 294 * @name: PLL name 295 * @clk_id: Clock ID 296 * @parents: Name of this clock's parents 297 * @num_parents: Number of parents 298 * @nodes: Clock topology node 299 * 300 * Return: clock hardware to the registered clock 301 */ 302 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, 303 const char * const *parents, 304 u8 num_parents, 305 const struct clock_topology *nodes) 306 { 307 struct zynqmp_pll *pll; 308 struct clk_hw *hw; 309 struct clk_init_data init; 310 int ret; 311 312 init.name = name; 313 init.ops = &zynqmp_pll_ops; 314 init.flags = nodes->flag; 315 init.parent_names = parents; 316 init.num_parents = 1; 317 318 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 319 if (!pll) 320 return ERR_PTR(-ENOMEM); 321 322 pll->hw.init = &init; 323 pll->clk_id = clk_id; 324 325 hw = &pll->hw; 326 ret = clk_hw_register(NULL, hw); 327 if (ret) { 328 kfree(pll); 329 return ERR_PTR(ret); 330 } 331 332 clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX); 333 if (ret < 0) 334 pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret); 335 336 return hw; 337 } 338