1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC Divider support 4 * 5 * Copyright (C) 2016-2018 Xilinx 6 * 7 * Adjustable divider clock implementation 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/slab.h> 13 #include "clk-zynqmp.h" 14 15 /* 16 * DOC: basic adjustable divider clock that cannot gate 17 * 18 * Traits of this clock: 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 22 * parent - fixed parent. No clk_set_parent support 23 */ 24 25 #define to_zynqmp_clk_divider(_hw) \ 26 container_of(_hw, struct zynqmp_clk_divider, hw) 27 28 #define CLK_FRAC BIT(13) /* has a fractional parent */ 29 30 /** 31 * struct zynqmp_clk_divider - adjustable divider clock 32 * @hw: handle between common and hardware-specific interfaces 33 * @flags: Hardware specific flags 34 * @clk_id: Id of clock 35 * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 36 */ 37 struct zynqmp_clk_divider { 38 struct clk_hw hw; 39 u8 flags; 40 u32 clk_id; 41 u32 div_type; 42 }; 43 44 static inline int zynqmp_divider_get_val(unsigned long parent_rate, 45 unsigned long rate) 46 { 47 return DIV_ROUND_CLOSEST(parent_rate, rate); 48 } 49 50 /** 51 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 52 * @hw: handle between common and hardware-specific interfaces 53 * @parent_rate: rate of parent clock 54 * 55 * Return: 0 on success else error+reason 56 */ 57 static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 58 unsigned long parent_rate) 59 { 60 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 61 const char *clk_name = clk_hw_get_name(hw); 62 u32 clk_id = divider->clk_id; 63 u32 div_type = divider->div_type; 64 u32 div, value; 65 int ret; 66 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 67 68 ret = eemi_ops->clock_getdivider(clk_id, &div); 69 70 if (ret) 71 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 72 __func__, clk_name, ret); 73 74 if (div_type == TYPE_DIV1) 75 value = div & 0xFFFF; 76 else 77 value = div >> 16; 78 79 if (!value) { 80 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 81 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 82 clk_name); 83 return parent_rate; 84 } 85 86 return DIV_ROUND_UP_ULL(parent_rate, value); 87 } 88 89 /** 90 * zynqmp_clk_divider_round_rate() - Round rate of divider clock 91 * @hw: handle between common and hardware-specific interfaces 92 * @rate: rate of clock to be set 93 * @prate: rate of parent clock 94 * 95 * Return: 0 on success else error+reason 96 */ 97 static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 98 unsigned long rate, 99 unsigned long *prate) 100 { 101 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 102 const char *clk_name = clk_hw_get_name(hw); 103 u32 clk_id = divider->clk_id; 104 u32 div_type = divider->div_type; 105 u32 bestdiv; 106 int ret; 107 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 108 109 /* if read only, just return current value */ 110 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 111 ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); 112 113 if (ret) 114 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 115 __func__, clk_name, ret); 116 if (div_type == TYPE_DIV1) 117 bestdiv = bestdiv & 0xFFFF; 118 else 119 bestdiv = bestdiv >> 16; 120 121 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 122 } 123 124 bestdiv = zynqmp_divider_get_val(*prate, rate); 125 126 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && 127 (divider->flags & CLK_FRAC)) 128 bestdiv = rate % *prate ? 1 : bestdiv; 129 *prate = rate * bestdiv; 130 131 return rate; 132 } 133 134 /** 135 * zynqmp_clk_divider_set_rate() - Set rate of divider clock 136 * @hw: handle between common and hardware-specific interfaces 137 * @rate: rate of clock to be set 138 * @parent_rate: rate of parent clock 139 * 140 * Return: 0 on success else error+reason 141 */ 142 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 143 unsigned long parent_rate) 144 { 145 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 146 const char *clk_name = clk_hw_get_name(hw); 147 u32 clk_id = divider->clk_id; 148 u32 div_type = divider->div_type; 149 u32 value, div; 150 int ret; 151 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 152 153 value = zynqmp_divider_get_val(parent_rate, rate); 154 if (div_type == TYPE_DIV1) { 155 div = value & 0xFFFF; 156 div |= 0xffff << 16; 157 } else { 158 div = 0xffff; 159 div |= value << 16; 160 } 161 162 ret = eemi_ops->clock_setdivider(clk_id, div); 163 164 if (ret) 165 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 166 __func__, clk_name, ret); 167 168 return ret; 169 } 170 171 static const struct clk_ops zynqmp_clk_divider_ops = { 172 .recalc_rate = zynqmp_clk_divider_recalc_rate, 173 .round_rate = zynqmp_clk_divider_round_rate, 174 .set_rate = zynqmp_clk_divider_set_rate, 175 }; 176 177 /** 178 * zynqmp_clk_register_divider() - Register a divider clock 179 * @name: Name of this clock 180 * @clk_id: Id of clock 181 * @parents: Name of this clock's parents 182 * @num_parents: Number of parents 183 * @nodes: Clock topology node 184 * 185 * Return: clock hardware to registered clock divider 186 */ 187 struct clk_hw *zynqmp_clk_register_divider(const char *name, 188 u32 clk_id, 189 const char * const *parents, 190 u8 num_parents, 191 const struct clock_topology *nodes) 192 { 193 struct zynqmp_clk_divider *div; 194 struct clk_hw *hw; 195 struct clk_init_data init; 196 int ret; 197 198 /* allocate the divider */ 199 div = kzalloc(sizeof(*div), GFP_KERNEL); 200 if (!div) 201 return ERR_PTR(-ENOMEM); 202 203 init.name = name; 204 init.ops = &zynqmp_clk_divider_ops; 205 init.flags = nodes->flag; 206 init.parent_names = parents; 207 init.num_parents = 1; 208 209 /* struct clk_divider assignments */ 210 div->flags = nodes->type_flag; 211 div->hw.init = &init; 212 div->clk_id = clk_id; 213 div->div_type = nodes->type; 214 215 hw = &div->hw; 216 ret = clk_hw_register(NULL, hw); 217 if (ret) { 218 kfree(div); 219 hw = ERR_PTR(ret); 220 } 221 222 return hw; 223 } 224