1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC Divider support 4 * 5 * Copyright (C) 2016-2019 Xilinx 6 * 7 * Adjustable divider clock implementation 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/slab.h> 13 #include "clk-zynqmp.h" 14 15 /* 16 * DOC: basic adjustable divider clock that cannot gate 17 * 18 * Traits of this clock: 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 22 * parent - fixed parent. No clk_set_parent support 23 */ 24 25 #define to_zynqmp_clk_divider(_hw) \ 26 container_of(_hw, struct zynqmp_clk_divider, hw) 27 28 #define CLK_FRAC BIT(13) /* has a fractional parent */ 29 30 /** 31 * struct zynqmp_clk_divider - adjustable divider clock 32 * @hw: handle between common and hardware-specific interfaces 33 * @flags: Hardware specific flags 34 * @is_frac: The divider is a fractional divider 35 * @clk_id: Id of clock 36 * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 37 */ 38 struct zynqmp_clk_divider { 39 struct clk_hw hw; 40 u8 flags; 41 bool is_frac; 42 u32 clk_id; 43 u32 div_type; 44 u16 max_div; 45 }; 46 47 static inline int zynqmp_divider_get_val(unsigned long parent_rate, 48 unsigned long rate, u16 flags) 49 { 50 int up, down; 51 unsigned long up_rate, down_rate; 52 53 if (flags & CLK_DIVIDER_POWER_OF_TWO) { 54 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 55 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); 56 57 up = __roundup_pow_of_two(up); 58 down = __rounddown_pow_of_two(down); 59 60 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); 61 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); 62 63 return (rate - up_rate) <= (down_rate - rate) ? up : down; 64 65 } else { 66 return DIV_ROUND_CLOSEST(parent_rate, rate); 67 } 68 } 69 70 /** 71 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 72 * @hw: handle between common and hardware-specific interfaces 73 * @parent_rate: rate of parent clock 74 * 75 * Return: 0 on success else error+reason 76 */ 77 static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 78 unsigned long parent_rate) 79 { 80 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 81 const char *clk_name = clk_hw_get_name(hw); 82 u32 clk_id = divider->clk_id; 83 u32 div_type = divider->div_type; 84 u32 div, value; 85 int ret; 86 87 ret = zynqmp_pm_clock_getdivider(clk_id, &div); 88 89 if (ret) 90 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 91 __func__, clk_name, ret); 92 93 if (div_type == TYPE_DIV1) 94 value = div & 0xFFFF; 95 else 96 value = div >> 16; 97 98 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 99 value = 1 << value; 100 101 if (!value) { 102 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 103 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 104 clk_name); 105 return parent_rate; 106 } 107 108 return DIV_ROUND_UP_ULL(parent_rate, value); 109 } 110 111 static void zynqmp_get_divider2_val(struct clk_hw *hw, 112 unsigned long rate, 113 unsigned long parent_rate, 114 struct zynqmp_clk_divider *divider, 115 int *bestdiv) 116 { 117 int div1; 118 int div2; 119 long error = LONG_MAX; 120 struct clk_hw *parent_hw = clk_hw_get_parent(hw); 121 struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw); 122 123 if (!pdivider) 124 return; 125 126 *bestdiv = 1; 127 for (div1 = 1; div1 <= pdivider->max_div;) { 128 for (div2 = 1; div2 <= divider->max_div;) { 129 long new_error = ((parent_rate / div1) / div2) - rate; 130 131 if (abs(new_error) < abs(error)) { 132 *bestdiv = div2; 133 error = new_error; 134 } 135 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 136 div2 = div2 << 1; 137 else 138 div2++; 139 } 140 if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) 141 div1 = div1 << 1; 142 else 143 div1++; 144 } 145 } 146 147 /** 148 * zynqmp_clk_divider_round_rate() - Round rate of divider clock 149 * @hw: handle between common and hardware-specific interfaces 150 * @rate: rate of clock to be set 151 * @prate: rate of parent clock 152 * 153 * Return: 0 on success else error+reason 154 */ 155 static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 156 unsigned long rate, 157 unsigned long *prate) 158 { 159 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 160 const char *clk_name = clk_hw_get_name(hw); 161 u32 clk_id = divider->clk_id; 162 u32 div_type = divider->div_type; 163 u32 bestdiv; 164 int ret; 165 166 /* if read only, just return current value */ 167 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 168 ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); 169 170 if (ret) 171 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 172 __func__, clk_name, ret); 173 if (div_type == TYPE_DIV1) 174 bestdiv = bestdiv & 0xFFFF; 175 else 176 bestdiv = bestdiv >> 16; 177 178 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 179 bestdiv = 1 << bestdiv; 180 181 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 182 } 183 184 bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); 185 186 /* 187 * In case of two divisors, compute best divider values and return 188 * divider2 value based on compute value. div1 will be automatically 189 * set to optimum based on required total divider value. 190 */ 191 if (div_type == TYPE_DIV2 && 192 (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { 193 zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv); 194 } 195 196 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) 197 bestdiv = rate % *prate ? 1 : bestdiv; 198 *prate = rate * bestdiv; 199 200 return rate; 201 } 202 203 /** 204 * zynqmp_clk_divider_set_rate() - Set rate of divider clock 205 * @hw: handle between common and hardware-specific interfaces 206 * @rate: rate of clock to be set 207 * @parent_rate: rate of parent clock 208 * 209 * Return: 0 on success else error+reason 210 */ 211 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 212 unsigned long parent_rate) 213 { 214 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 215 const char *clk_name = clk_hw_get_name(hw); 216 u32 clk_id = divider->clk_id; 217 u32 div_type = divider->div_type; 218 u32 value, div; 219 int ret; 220 221 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); 222 if (div_type == TYPE_DIV1) { 223 div = value & 0xFFFF; 224 div |= 0xffff << 16; 225 } else { 226 div = 0xffff; 227 div |= value << 16; 228 } 229 230 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 231 div = __ffs(div); 232 233 ret = zynqmp_pm_clock_setdivider(clk_id, div); 234 235 if (ret) 236 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 237 __func__, clk_name, ret); 238 239 return ret; 240 } 241 242 static const struct clk_ops zynqmp_clk_divider_ops = { 243 .recalc_rate = zynqmp_clk_divider_recalc_rate, 244 .round_rate = zynqmp_clk_divider_round_rate, 245 .set_rate = zynqmp_clk_divider_set_rate, 246 }; 247 248 /** 249 * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. 250 * @clk_id: Id of clock 251 * @type: Divider type 252 * 253 * Return: Maximum divisor of a clock if query data is successful 254 * U16_MAX in case of query data is not success 255 */ 256 u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) 257 { 258 struct zynqmp_pm_query_data qdata = {0}; 259 u32 ret_payload[PAYLOAD_ARG_CNT]; 260 int ret; 261 262 qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; 263 qdata.arg1 = clk_id; 264 qdata.arg2 = type; 265 ret = zynqmp_pm_query_data(qdata, ret_payload); 266 /* 267 * To maintain backward compatibility return maximum possible value 268 * (0xFFFF) if query for max divisor is not successful. 269 */ 270 if (ret) 271 return U16_MAX; 272 273 return ret_payload[1]; 274 } 275 276 /** 277 * zynqmp_clk_register_divider() - Register a divider clock 278 * @name: Name of this clock 279 * @clk_id: Id of clock 280 * @parents: Name of this clock's parents 281 * @num_parents: Number of parents 282 * @nodes: Clock topology node 283 * 284 * Return: clock hardware to registered clock divider 285 */ 286 struct clk_hw *zynqmp_clk_register_divider(const char *name, 287 u32 clk_id, 288 const char * const *parents, 289 u8 num_parents, 290 const struct clock_topology *nodes) 291 { 292 struct zynqmp_clk_divider *div; 293 struct clk_hw *hw; 294 struct clk_init_data init; 295 int ret; 296 297 /* allocate the divider */ 298 div = kzalloc(sizeof(*div), GFP_KERNEL); 299 if (!div) 300 return ERR_PTR(-ENOMEM); 301 302 init.name = name; 303 init.ops = &zynqmp_clk_divider_ops; 304 /* CLK_FRAC is not defined in the common clk framework */ 305 init.flags = nodes->flag & ~CLK_FRAC; 306 init.parent_names = parents; 307 init.num_parents = 1; 308 309 /* struct clk_divider assignments */ 310 div->is_frac = !!(nodes->flag & CLK_FRAC); 311 div->flags = nodes->type_flag; 312 div->hw.init = &init; 313 div->clk_id = clk_id; 314 div->div_type = nodes->type; 315 316 /* 317 * To achieve best possible rate, maximum limit of divider is required 318 * while computation. 319 */ 320 div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); 321 322 hw = &div->hw; 323 ret = clk_hw_register(NULL, hw); 324 if (ret) { 325 kfree(div); 326 hw = ERR_PTR(ret); 327 } 328 329 return hw; 330 } 331