1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC Divider support 4 * 5 * Copyright (C) 2016-2018 Xilinx 6 * 7 * Adjustable divider clock implementation 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/slab.h> 13 #include "clk-zynqmp.h" 14 15 /* 16 * DOC: basic adjustable divider clock that cannot gate 17 * 18 * Traits of this clock: 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 22 * parent - fixed parent. No clk_set_parent support 23 */ 24 25 #define to_zynqmp_clk_divider(_hw) \ 26 container_of(_hw, struct zynqmp_clk_divider, hw) 27 28 #define CLK_FRAC BIT(13) /* has a fractional parent */ 29 30 /** 31 * struct zynqmp_clk_divider - adjustable divider clock 32 * @hw: handle between common and hardware-specific interfaces 33 * @flags: Hardware specific flags 34 * @clk_id: Id of clock 35 * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 36 */ 37 struct zynqmp_clk_divider { 38 struct clk_hw hw; 39 u8 flags; 40 u32 clk_id; 41 u32 div_type; 42 }; 43 44 static inline int zynqmp_divider_get_val(unsigned long parent_rate, 45 unsigned long rate) 46 { 47 return DIV_ROUND_CLOSEST(parent_rate, rate); 48 } 49 50 /** 51 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 52 * @hw: handle between common and hardware-specific interfaces 53 * @parent_rate: rate of parent clock 54 * 55 * Return: 0 on success else error+reason 56 */ 57 static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 58 unsigned long parent_rate) 59 { 60 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 61 const char *clk_name = clk_hw_get_name(hw); 62 u32 clk_id = divider->clk_id; 63 u32 div_type = divider->div_type; 64 u32 div, value; 65 int ret; 66 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 67 68 ret = eemi_ops->clock_getdivider(clk_id, &div); 69 70 if (ret) 71 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 72 __func__, clk_name, ret); 73 74 if (div_type == TYPE_DIV1) 75 value = div & 0xFFFF; 76 else 77 value = div >> 16; 78 79 return DIV_ROUND_UP_ULL(parent_rate, value); 80 } 81 82 /** 83 * zynqmp_clk_divider_round_rate() - Round rate of divider clock 84 * @hw: handle between common and hardware-specific interfaces 85 * @rate: rate of clock to be set 86 * @prate: rate of parent clock 87 * 88 * Return: 0 on success else error+reason 89 */ 90 static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 91 unsigned long rate, 92 unsigned long *prate) 93 { 94 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 95 const char *clk_name = clk_hw_get_name(hw); 96 u32 clk_id = divider->clk_id; 97 u32 div_type = divider->div_type; 98 u32 bestdiv; 99 int ret; 100 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 101 102 /* if read only, just return current value */ 103 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 104 ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); 105 106 if (ret) 107 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 108 __func__, clk_name, ret); 109 if (div_type == TYPE_DIV1) 110 bestdiv = bestdiv & 0xFFFF; 111 else 112 bestdiv = bestdiv >> 16; 113 114 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 115 } 116 117 bestdiv = zynqmp_divider_get_val(*prate, rate); 118 119 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && 120 (divider->flags & CLK_FRAC)) 121 bestdiv = rate % *prate ? 1 : bestdiv; 122 *prate = rate * bestdiv; 123 124 return rate; 125 } 126 127 /** 128 * zynqmp_clk_divider_set_rate() - Set rate of divider clock 129 * @hw: handle between common and hardware-specific interfaces 130 * @rate: rate of clock to be set 131 * @parent_rate: rate of parent clock 132 * 133 * Return: 0 on success else error+reason 134 */ 135 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 136 unsigned long parent_rate) 137 { 138 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 139 const char *clk_name = clk_hw_get_name(hw); 140 u32 clk_id = divider->clk_id; 141 u32 div_type = divider->div_type; 142 u32 value, div; 143 int ret; 144 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 145 146 value = zynqmp_divider_get_val(parent_rate, rate); 147 if (div_type == TYPE_DIV1) { 148 div = value & 0xFFFF; 149 div |= 0xffff << 16; 150 } else { 151 div = 0xffff; 152 div |= value << 16; 153 } 154 155 ret = eemi_ops->clock_setdivider(clk_id, div); 156 157 if (ret) 158 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 159 __func__, clk_name, ret); 160 161 return ret; 162 } 163 164 static const struct clk_ops zynqmp_clk_divider_ops = { 165 .recalc_rate = zynqmp_clk_divider_recalc_rate, 166 .round_rate = zynqmp_clk_divider_round_rate, 167 .set_rate = zynqmp_clk_divider_set_rate, 168 }; 169 170 /** 171 * zynqmp_clk_register_divider() - Register a divider clock 172 * @name: Name of this clock 173 * @clk_id: Id of clock 174 * @parents: Name of this clock's parents 175 * @num_parents: Number of parents 176 * @nodes: Clock topology node 177 * 178 * Return: clock hardware to registered clock divider 179 */ 180 struct clk_hw *zynqmp_clk_register_divider(const char *name, 181 u32 clk_id, 182 const char * const *parents, 183 u8 num_parents, 184 const struct clock_topology *nodes) 185 { 186 struct zynqmp_clk_divider *div; 187 struct clk_hw *hw; 188 struct clk_init_data init; 189 int ret; 190 191 /* allocate the divider */ 192 div = kzalloc(sizeof(*div), GFP_KERNEL); 193 if (!div) 194 return ERR_PTR(-ENOMEM); 195 196 init.name = name; 197 init.ops = &zynqmp_clk_divider_ops; 198 init.flags = nodes->flag; 199 init.parent_names = parents; 200 init.num_parents = 1; 201 202 /* struct clk_divider assignments */ 203 div->flags = nodes->type_flag; 204 div->hw.init = &init; 205 div->clk_id = clk_id; 206 div->div_type = nodes->type; 207 208 hw = &div->hw; 209 ret = clk_hw_register(NULL, hw); 210 if (ret) { 211 kfree(div); 212 hw = ERR_PTR(ret); 213 } 214 215 return hw; 216 } 217 EXPORT_SYMBOL_GPL(zynqmp_clk_register_divider); 218