1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC Divider support 4 * 5 * Copyright (C) 2016-2019 Xilinx 6 * 7 * Adjustable divider clock implementation 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/slab.h> 13 #include "clk-zynqmp.h" 14 15 /* 16 * DOC: basic adjustable divider clock that cannot gate 17 * 18 * Traits of this clock: 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 22 * parent - fixed parent. No clk_set_parent support 23 */ 24 25 #define to_zynqmp_clk_divider(_hw) \ 26 container_of(_hw, struct zynqmp_clk_divider, hw) 27 28 #define CLK_FRAC BIT(13) /* has a fractional parent */ 29 30 /** 31 * struct zynqmp_clk_divider - adjustable divider clock 32 * @hw: handle between common and hardware-specific interfaces 33 * @flags: Hardware specific flags 34 * @is_frac: The divider is a fractional divider 35 * @clk_id: Id of clock 36 * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 37 */ 38 struct zynqmp_clk_divider { 39 struct clk_hw hw; 40 u8 flags; 41 bool is_frac; 42 u32 clk_id; 43 u32 div_type; 44 u16 max_div; 45 }; 46 47 static inline int zynqmp_divider_get_val(unsigned long parent_rate, 48 unsigned long rate, u16 flags) 49 { 50 int up, down; 51 unsigned long up_rate, down_rate; 52 53 if (flags & CLK_DIVIDER_POWER_OF_TWO) { 54 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 55 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); 56 57 up = __roundup_pow_of_two(up); 58 down = __rounddown_pow_of_two(down); 59 60 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); 61 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); 62 63 return (rate - up_rate) <= (down_rate - rate) ? up : down; 64 65 } else { 66 return DIV_ROUND_CLOSEST(parent_rate, rate); 67 } 68 } 69 70 /** 71 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 72 * @hw: handle between common and hardware-specific interfaces 73 * @parent_rate: rate of parent clock 74 * 75 * Return: 0 on success else error+reason 76 */ 77 static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 78 unsigned long parent_rate) 79 { 80 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 81 const char *clk_name = clk_hw_get_name(hw); 82 u32 clk_id = divider->clk_id; 83 u32 div_type = divider->div_type; 84 u32 div, value; 85 int ret; 86 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 87 88 ret = eemi_ops->clock_getdivider(clk_id, &div); 89 90 if (ret) 91 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 92 __func__, clk_name, ret); 93 94 if (div_type == TYPE_DIV1) 95 value = div & 0xFFFF; 96 else 97 value = div >> 16; 98 99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 100 value = 1 << value; 101 102 if (!value) { 103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 104 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 105 clk_name); 106 return parent_rate; 107 } 108 109 return DIV_ROUND_UP_ULL(parent_rate, value); 110 } 111 112 static void zynqmp_get_divider2_val(struct clk_hw *hw, 113 unsigned long rate, 114 unsigned long parent_rate, 115 struct zynqmp_clk_divider *divider, 116 int *bestdiv) 117 { 118 int div1; 119 int div2; 120 long error = LONG_MAX; 121 struct clk_hw *parent_hw = clk_hw_get_parent(hw); 122 struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw); 123 124 if (!pdivider) 125 return; 126 127 *bestdiv = 1; 128 for (div1 = 1; div1 <= pdivider->max_div;) { 129 for (div2 = 1; div2 <= divider->max_div;) { 130 long new_error = ((parent_rate / div1) / div2) - rate; 131 132 if (abs(new_error) < abs(error)) { 133 *bestdiv = div2; 134 error = new_error; 135 } 136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 137 div2 = div2 << 1; 138 else 139 div2++; 140 } 141 if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) 142 div1 = div1 << 1; 143 else 144 div1++; 145 } 146 } 147 148 /** 149 * zynqmp_clk_divider_round_rate() - Round rate of divider clock 150 * @hw: handle between common and hardware-specific interfaces 151 * @rate: rate of clock to be set 152 * @prate: rate of parent clock 153 * 154 * Return: 0 on success else error+reason 155 */ 156 static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 157 unsigned long rate, 158 unsigned long *prate) 159 { 160 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 161 const char *clk_name = clk_hw_get_name(hw); 162 u32 clk_id = divider->clk_id; 163 u32 div_type = divider->div_type; 164 u32 bestdiv; 165 int ret; 166 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 167 168 /* if read only, just return current value */ 169 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 170 ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); 171 172 if (ret) 173 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 174 __func__, clk_name, ret); 175 if (div_type == TYPE_DIV1) 176 bestdiv = bestdiv & 0xFFFF; 177 else 178 bestdiv = bestdiv >> 16; 179 180 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 181 bestdiv = 1 << bestdiv; 182 183 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 184 } 185 186 bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); 187 188 /* 189 * In case of two divisors, compute best divider values and return 190 * divider2 value based on compute value. div1 will be automatically 191 * set to optimum based on required total divider value. 192 */ 193 if (div_type == TYPE_DIV2 && 194 (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { 195 zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv); 196 } 197 198 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) 199 bestdiv = rate % *prate ? 1 : bestdiv; 200 *prate = rate * bestdiv; 201 202 return rate; 203 } 204 205 /** 206 * zynqmp_clk_divider_set_rate() - Set rate of divider clock 207 * @hw: handle between common and hardware-specific interfaces 208 * @rate: rate of clock to be set 209 * @parent_rate: rate of parent clock 210 * 211 * Return: 0 on success else error+reason 212 */ 213 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 214 unsigned long parent_rate) 215 { 216 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 217 const char *clk_name = clk_hw_get_name(hw); 218 u32 clk_id = divider->clk_id; 219 u32 div_type = divider->div_type; 220 u32 value, div; 221 int ret; 222 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 223 224 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); 225 if (div_type == TYPE_DIV1) { 226 div = value & 0xFFFF; 227 div |= 0xffff << 16; 228 } else { 229 div = 0xffff; 230 div |= value << 16; 231 } 232 233 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 234 div = __ffs(div); 235 236 ret = eemi_ops->clock_setdivider(clk_id, div); 237 238 if (ret) 239 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 240 __func__, clk_name, ret); 241 242 return ret; 243 } 244 245 static const struct clk_ops zynqmp_clk_divider_ops = { 246 .recalc_rate = zynqmp_clk_divider_recalc_rate, 247 .round_rate = zynqmp_clk_divider_round_rate, 248 .set_rate = zynqmp_clk_divider_set_rate, 249 }; 250 251 /** 252 * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. 253 * @clk_id: Id of clock 254 * @type: Divider type 255 * 256 * Return: Maximum divisor of a clock if query data is successful 257 * U16_MAX in case of query data is not success 258 */ 259 u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) 260 { 261 struct zynqmp_pm_query_data qdata = {0}; 262 u32 ret_payload[PAYLOAD_ARG_CNT]; 263 int ret; 264 265 qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; 266 qdata.arg1 = clk_id; 267 qdata.arg2 = type; 268 ret = zynqmp_pm_query_data(qdata, ret_payload); 269 /* 270 * To maintain backward compatibility return maximum possible value 271 * (0xFFFF) if query for max divisor is not successful. 272 */ 273 if (ret) 274 return U16_MAX; 275 276 return ret_payload[1]; 277 } 278 279 /** 280 * zynqmp_clk_register_divider() - Register a divider clock 281 * @name: Name of this clock 282 * @clk_id: Id of clock 283 * @parents: Name of this clock's parents 284 * @num_parents: Number of parents 285 * @nodes: Clock topology node 286 * 287 * Return: clock hardware to registered clock divider 288 */ 289 struct clk_hw *zynqmp_clk_register_divider(const char *name, 290 u32 clk_id, 291 const char * const *parents, 292 u8 num_parents, 293 const struct clock_topology *nodes) 294 { 295 struct zynqmp_clk_divider *div; 296 struct clk_hw *hw; 297 struct clk_init_data init; 298 int ret; 299 300 /* allocate the divider */ 301 div = kzalloc(sizeof(*div), GFP_KERNEL); 302 if (!div) 303 return ERR_PTR(-ENOMEM); 304 305 init.name = name; 306 init.ops = &zynqmp_clk_divider_ops; 307 /* CLK_FRAC is not defined in the common clk framework */ 308 init.flags = nodes->flag & ~CLK_FRAC; 309 init.parent_names = parents; 310 init.num_parents = 1; 311 312 /* struct clk_divider assignments */ 313 div->is_frac = !!(nodes->flag & CLK_FRAC); 314 div->flags = nodes->type_flag; 315 div->hw.init = &init; 316 div->clk_id = clk_id; 317 div->div_type = nodes->type; 318 319 /* 320 * To achieve best possible rate, maximum limit of divider is required 321 * while computation. 322 */ 323 div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); 324 325 hw = &div->hw; 326 ret = clk_hw_register(NULL, hw); 327 if (ret) { 328 kfree(div); 329 hw = ERR_PTR(ret); 330 } 331 332 return hw; 333 } 334