1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC clock controller 4 * 5 * Copyright (C) 2016-2018 Xilinx 6 * 7 * Based on drivers/clk/zynq/clkc.c 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/slab.h> 16 #include <linux/string.h> 17 18 #include "clk-zynqmp.h" 19 20 #define MAX_PARENT 100 21 #define MAX_NODES 6 22 #define MAX_NAME_LEN 50 23 24 #define CLK_TYPE_SHIFT 2 25 26 #define PM_API_PAYLOAD_LEN 3 27 28 #define NA_PARENT 0xFFFFFFFF 29 #define DUMMY_PARENT 0xFFFFFFFE 30 31 #define CLK_TYPE_FIELD_LEN 4 32 #define CLK_TOPOLOGY_NODE_OFFSET 16 33 #define NODES_PER_RESP 3 34 35 #define CLK_TYPE_FIELD_MASK 0xF 36 #define CLK_FLAG_FIELD_MASK GENMASK(21, 8) 37 #define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24) 38 39 #define CLK_PARENTS_ID_LEN 16 40 #define CLK_PARENTS_ID_MASK 0xFFFF 41 42 /* Flags for parents */ 43 #define PARENT_CLK_SELF 0 44 #define PARENT_CLK_NODE1 1 45 #define PARENT_CLK_NODE2 2 46 #define PARENT_CLK_NODE3 3 47 #define PARENT_CLK_NODE4 4 48 #define PARENT_CLK_EXTERNAL 5 49 50 #define END_OF_CLK_NAME "END_OF_CLK" 51 #define END_OF_TOPOLOGY_NODE 1 52 #define END_OF_PARENTS 1 53 #define RESERVED_CLK_NAME "" 54 55 #define CLK_VALID_MASK 0x1 56 #define NODE_CLASS_SHIFT 26U 57 #define NODE_SUBCLASS_SHIFT 20U 58 #define NODE_TYPE_SHIFT 14U 59 #define NODE_INDEX_SHIFT 0U 60 61 enum clk_type { 62 CLK_TYPE_OUTPUT, 63 CLK_TYPE_EXTERNAL, 64 }; 65 66 /** 67 * struct clock_parent - Clock parent 68 * @name: Parent name 69 * @id: Parent clock ID 70 * @flag: Parent flags 71 */ 72 struct clock_parent { 73 char name[MAX_NAME_LEN]; 74 int id; 75 u32 flag; 76 }; 77 78 /** 79 * struct zynqmp_clock - Clock 80 * @clk_name: Clock name 81 * @valid: Validity flag of clock 82 * @type: Clock type (Output/External) 83 * @node: Clock topology nodes 84 * @num_nodes: Number of nodes present in topology 85 * @parent: Parent of clock 86 * @num_parents: Number of parents of clock 87 * @clk_id: Clock id 88 */ 89 struct zynqmp_clock { 90 char clk_name[MAX_NAME_LEN]; 91 u32 valid; 92 enum clk_type type; 93 struct clock_topology node[MAX_NODES]; 94 u32 num_nodes; 95 struct clock_parent parent[MAX_PARENT]; 96 u32 num_parents; 97 u32 clk_id; 98 }; 99 100 static const char clk_type_postfix[][10] = { 101 [TYPE_INVALID] = "", 102 [TYPE_MUX] = "_mux", 103 [TYPE_GATE] = "", 104 [TYPE_DIV1] = "_div1", 105 [TYPE_DIV2] = "_div2", 106 [TYPE_FIXEDFACTOR] = "_ff", 107 [TYPE_PLL] = "" 108 }; 109 110 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id, 111 const char * const *parents, 112 u8 num_parents, 113 const struct clock_topology *nodes) 114 = { 115 [TYPE_INVALID] = NULL, 116 [TYPE_MUX] = zynqmp_clk_register_mux, 117 [TYPE_PLL] = zynqmp_clk_register_pll, 118 [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor, 119 [TYPE_DIV1] = zynqmp_clk_register_divider, 120 [TYPE_DIV2] = zynqmp_clk_register_divider, 121 [TYPE_GATE] = zynqmp_clk_register_gate 122 }; 123 124 static struct zynqmp_clock *clock; 125 static struct clk_hw_onecell_data *zynqmp_data; 126 static unsigned int clock_max_idx; 127 static const struct zynqmp_eemi_ops *eemi_ops; 128 129 /** 130 * zynqmp_is_valid_clock() - Check whether clock is valid or not 131 * @clk_id: Clock index 132 * 133 * Return: 1 if clock is valid, 0 if clock is invalid else error code 134 */ 135 static inline int zynqmp_is_valid_clock(u32 clk_id) 136 { 137 if (clk_id >= clock_max_idx) 138 return -ENODEV; 139 140 return clock[clk_id].valid; 141 } 142 143 /** 144 * zynqmp_get_clock_name() - Get name of clock from Clock index 145 * @clk_id: Clock index 146 * @clk_name: Name of clock 147 * 148 * Return: 0 on success else error code 149 */ 150 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) 151 { 152 int ret; 153 154 ret = zynqmp_is_valid_clock(clk_id); 155 if (ret == 1) { 156 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); 157 return 0; 158 } 159 160 return ret == 0 ? -EINVAL : ret; 161 } 162 163 /** 164 * zynqmp_get_clock_type() - Get type of clock 165 * @clk_id: Clock index 166 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL 167 * 168 * Return: 0 on success else error code 169 */ 170 static int zynqmp_get_clock_type(u32 clk_id, u32 *type) 171 { 172 int ret; 173 174 ret = zynqmp_is_valid_clock(clk_id); 175 if (ret == 1) { 176 *type = clock[clk_id].type; 177 return 0; 178 } 179 180 return ret == 0 ? -EINVAL : ret; 181 } 182 183 /** 184 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system 185 * @nclocks: Number of clocks in system/board. 186 * 187 * Call firmware API to get number of clocks. 188 * 189 * Return: 0 on success else error code. 190 */ 191 static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks) 192 { 193 struct zynqmp_pm_query_data qdata = {0}; 194 u32 ret_payload[PAYLOAD_ARG_CNT]; 195 int ret; 196 197 qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS; 198 199 ret = eemi_ops->query_data(qdata, ret_payload); 200 *nclocks = ret_payload[1]; 201 202 return ret; 203 } 204 205 /** 206 * zynqmp_pm_clock_get_name() - Get the name of clock for given id 207 * @clock_id: ID of the clock to be queried 208 * @name: Name of given clock 209 * 210 * This function is used to get name of clock specified by given 211 * clock ID. 212 * 213 * Return: Returns 0, in case of error name would be 0 214 */ 215 static int zynqmp_pm_clock_get_name(u32 clock_id, char *name) 216 { 217 struct zynqmp_pm_query_data qdata = {0}; 218 u32 ret_payload[PAYLOAD_ARG_CNT]; 219 220 qdata.qid = PM_QID_CLOCK_GET_NAME; 221 qdata.arg1 = clock_id; 222 223 eemi_ops->query_data(qdata, ret_payload); 224 memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN); 225 226 return 0; 227 } 228 229 /** 230 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id 231 * @clock_id: ID of the clock to be queried 232 * @index: Node index of clock topology 233 * @topology: Buffer to store nodes in topology and flags 234 * 235 * This function is used to get topology information for the clock 236 * specified by given clock ID. 237 * 238 * This API will return 3 node of topology with a single response. To get 239 * other nodes, master should call same API in loop with new 240 * index till error is returned. E.g First call should have 241 * index 0 which will return nodes 0,1 and 2. Next call, index 242 * should be 3 which will return nodes 3,4 and 5 and so on. 243 * 244 * Return: 0 on success else error+reason 245 */ 246 static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology) 247 { 248 struct zynqmp_pm_query_data qdata = {0}; 249 u32 ret_payload[PAYLOAD_ARG_CNT]; 250 int ret; 251 252 qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY; 253 qdata.arg1 = clock_id; 254 qdata.arg2 = index; 255 256 ret = eemi_ops->query_data(qdata, ret_payload); 257 memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4); 258 259 return ret; 260 } 261 262 /** 263 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the 264 * clock framework 265 * @name: Name of this clock 266 * @clk_id: Clock ID 267 * @parents: Name of this clock's parents 268 * @num_parents: Number of parents 269 * @nodes: Clock topology node 270 * 271 * Return: clock hardware to the registered clock 272 */ 273 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, 274 const char * const *parents, 275 u8 num_parents, 276 const struct clock_topology *nodes) 277 { 278 u32 mult, div; 279 struct clk_hw *hw; 280 struct zynqmp_pm_query_data qdata = {0}; 281 u32 ret_payload[PAYLOAD_ARG_CNT]; 282 int ret; 283 284 qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; 285 qdata.arg1 = clk_id; 286 287 ret = eemi_ops->query_data(qdata, ret_payload); 288 if (ret) 289 return ERR_PTR(ret); 290 291 mult = ret_payload[1]; 292 div = ret_payload[2]; 293 294 hw = clk_hw_register_fixed_factor(NULL, name, 295 parents[0], 296 nodes->flag, mult, 297 div); 298 299 return hw; 300 } 301 302 /** 303 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id 304 * @clock_id: Clock ID 305 * @index: Parent index 306 * @parents: 3 parents of the given clock 307 * 308 * This function is used to get 3 parents for the clock specified by 309 * given clock ID. 310 * 311 * This API will return 3 parents with a single response. To get 312 * other parents, master should call same API in loop with new 313 * parent index till error is returned. E.g First call should have 314 * index 0 which will return parents 0,1 and 2. Next call, index 315 * should be 3 which will return parent 3,4 and 5 and so on. 316 * 317 * Return: 0 on success else error+reason 318 */ 319 static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents) 320 { 321 struct zynqmp_pm_query_data qdata = {0}; 322 u32 ret_payload[PAYLOAD_ARG_CNT]; 323 int ret; 324 325 qdata.qid = PM_QID_CLOCK_GET_PARENTS; 326 qdata.arg1 = clock_id; 327 qdata.arg2 = index; 328 329 ret = eemi_ops->query_data(qdata, ret_payload); 330 memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4); 331 332 return ret; 333 } 334 335 /** 336 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id 337 * @clock_id: Clock ID 338 * @attr: Clock attributes 339 * 340 * This function is used to get clock's attributes(e.g. valid, clock type, etc). 341 * 342 * Return: 0 on success else error+reason 343 */ 344 static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr) 345 { 346 struct zynqmp_pm_query_data qdata = {0}; 347 u32 ret_payload[PAYLOAD_ARG_CNT]; 348 int ret; 349 350 qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES; 351 qdata.arg1 = clock_id; 352 353 ret = eemi_ops->query_data(qdata, ret_payload); 354 memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4); 355 356 return ret; 357 } 358 359 /** 360 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware 361 * response data 362 * @topology: Clock topology 363 * @data: Clock topology data received from firmware 364 * @nnodes: Number of nodes 365 * 366 * Return: 0 on success else error+reason 367 */ 368 static int __zynqmp_clock_get_topology(struct clock_topology *topology, 369 u32 *data, u32 *nnodes) 370 { 371 int i; 372 373 for (i = 0; i < PM_API_PAYLOAD_LEN; i++) { 374 if (!(data[i] & CLK_TYPE_FIELD_MASK)) 375 return END_OF_TOPOLOGY_NODE; 376 topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK; 377 topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK, 378 data[i]); 379 topology[*nnodes].type_flag = 380 FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]); 381 (*nnodes)++; 382 } 383 384 return 0; 385 } 386 387 /** 388 * zynqmp_clock_get_topology() - Get topology of clock from firmware using 389 * PM_API 390 * @clk_id: Clock index 391 * @topology: Clock topology 392 * @num_nodes: Number of nodes 393 * 394 * Return: 0 on success else error+reason 395 */ 396 static int zynqmp_clock_get_topology(u32 clk_id, 397 struct clock_topology *topology, 398 u32 *num_nodes) 399 { 400 int j, ret; 401 u32 pm_resp[PM_API_PAYLOAD_LEN] = {0}; 402 403 *num_nodes = 0; 404 for (j = 0; j <= MAX_NODES; j += 3) { 405 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j, 406 pm_resp); 407 if (ret) 408 return ret; 409 ret = __zynqmp_clock_get_topology(topology, pm_resp, num_nodes); 410 if (ret == END_OF_TOPOLOGY_NODE) 411 return 0; 412 } 413 414 return 0; 415 } 416 417 /** 418 * __zynqmp_clock_get_topology() - Get parents info of clock from firmware 419 * response data 420 * @parents: Clock parents 421 * @data: Clock parents data received from firmware 422 * @nparent: Number of parent 423 * 424 * Return: 0 on success else error+reason 425 */ 426 static int __zynqmp_clock_get_parents(struct clock_parent *parents, u32 *data, 427 u32 *nparent) 428 { 429 int i; 430 struct clock_parent *parent; 431 432 for (i = 0; i < PM_API_PAYLOAD_LEN; i++) { 433 if (data[i] == NA_PARENT) 434 return END_OF_PARENTS; 435 436 parent = &parents[i]; 437 parent->id = data[i] & CLK_PARENTS_ID_MASK; 438 if (data[i] == DUMMY_PARENT) { 439 strcpy(parent->name, "dummy_name"); 440 parent->flag = 0; 441 } else { 442 parent->flag = data[i] >> CLK_PARENTS_ID_LEN; 443 if (zynqmp_get_clock_name(parent->id, parent->name)) 444 continue; 445 } 446 *nparent += 1; 447 } 448 449 return 0; 450 } 451 452 /** 453 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API 454 * @clk_id: Clock index 455 * @parents: Clock parents 456 * @num_parents: Total number of parents 457 * 458 * Return: 0 on success else error+reason 459 */ 460 static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, 461 u32 *num_parents) 462 { 463 int j = 0, ret; 464 u32 pm_resp[PM_API_PAYLOAD_LEN] = {0}; 465 466 *num_parents = 0; 467 do { 468 /* Get parents from firmware */ 469 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j, 470 pm_resp); 471 if (ret) 472 return ret; 473 474 ret = __zynqmp_clock_get_parents(&parents[j], pm_resp, 475 num_parents); 476 if (ret == END_OF_PARENTS) 477 return 0; 478 j += PM_API_PAYLOAD_LEN; 479 } while (*num_parents <= MAX_PARENT); 480 481 return 0; 482 } 483 484 /** 485 * zynqmp_get_parent_list() - Create list of parents name 486 * @np: Device node 487 * @clk_id: Clock index 488 * @parent_list: List of parent's name 489 * @num_parents: Total number of parents 490 * 491 * Return: 0 on success else error+reason 492 */ 493 static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id, 494 const char **parent_list, u32 *num_parents) 495 { 496 int i = 0, ret; 497 u32 total_parents = clock[clk_id].num_parents; 498 struct clock_topology *clk_nodes; 499 struct clock_parent *parents; 500 501 clk_nodes = clock[clk_id].node; 502 parents = clock[clk_id].parent; 503 504 for (i = 0; i < total_parents; i++) { 505 if (!parents[i].flag) { 506 parent_list[i] = parents[i].name; 507 } else if (parents[i].flag == PARENT_CLK_EXTERNAL) { 508 ret = of_property_match_string(np, "clock-names", 509 parents[i].name); 510 if (ret < 0) 511 strcpy(parents[i].name, "dummy_name"); 512 parent_list[i] = parents[i].name; 513 } else { 514 strcat(parents[i].name, 515 clk_type_postfix[clk_nodes[parents[i].flag - 1]. 516 type]); 517 parent_list[i] = parents[i].name; 518 } 519 } 520 521 *num_parents = total_parents; 522 return 0; 523 } 524 525 /** 526 * zynqmp_register_clk_topology() - Register clock topology 527 * @clk_id: Clock index 528 * @clk_name: Clock Name 529 * @num_parents: Total number of parents 530 * @parent_names: List of parents name 531 * 532 * Return: Returns either clock hardware or error+reason 533 */ 534 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, 535 int num_parents, 536 const char **parent_names) 537 { 538 int j; 539 u32 num_nodes, clk_dev_id; 540 char *clk_out = NULL; 541 struct clock_topology *nodes; 542 struct clk_hw *hw = NULL; 543 544 nodes = clock[clk_id].node; 545 num_nodes = clock[clk_id].num_nodes; 546 clk_dev_id = clock[clk_id].clk_id; 547 548 for (j = 0; j < num_nodes; j++) { 549 /* 550 * Clock name received from firmware is output clock name. 551 * Intermediate clock names are postfixed with type of clock. 552 */ 553 if (j != (num_nodes - 1)) { 554 clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name, 555 clk_type_postfix[nodes[j].type]); 556 } else { 557 clk_out = kasprintf(GFP_KERNEL, "%s", clk_name); 558 } 559 560 if (!clk_topology[nodes[j].type]) 561 continue; 562 563 hw = (*clk_topology[nodes[j].type])(clk_out, clk_dev_id, 564 parent_names, 565 num_parents, 566 &nodes[j]); 567 if (IS_ERR(hw)) 568 pr_warn_once("%s() 0x%x: %s register fail with %ld\n", 569 __func__, clk_dev_id, clk_name, 570 PTR_ERR(hw)); 571 572 parent_names[0] = clk_out; 573 } 574 kfree(clk_out); 575 return hw; 576 } 577 578 /** 579 * zynqmp_register_clocks() - Register clocks 580 * @np: Device node 581 * 582 * Return: 0 on success else error code 583 */ 584 static int zynqmp_register_clocks(struct device_node *np) 585 { 586 int ret; 587 u32 i, total_parents = 0, type = 0; 588 const char *parent_names[MAX_PARENT]; 589 590 for (i = 0; i < clock_max_idx; i++) { 591 char clk_name[MAX_NAME_LEN]; 592 593 /* get clock name, continue to next clock if name not found */ 594 if (zynqmp_get_clock_name(i, clk_name)) 595 continue; 596 597 /* Check if clock is valid and output clock. 598 * Do not register invalid or external clock. 599 */ 600 ret = zynqmp_get_clock_type(i, &type); 601 if (ret || type != CLK_TYPE_OUTPUT) 602 continue; 603 604 /* Get parents of clock*/ 605 if (zynqmp_get_parent_list(np, i, parent_names, 606 &total_parents)) { 607 WARN_ONCE(1, "No parents found for %s\n", 608 clock[i].clk_name); 609 continue; 610 } 611 612 zynqmp_data->hws[i] = 613 zynqmp_register_clk_topology(i, clk_name, 614 total_parents, 615 parent_names); 616 } 617 618 for (i = 0; i < clock_max_idx; i++) { 619 if (IS_ERR(zynqmp_data->hws[i])) { 620 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", 621 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i])); 622 WARN_ON(1); 623 } 624 } 625 return 0; 626 } 627 628 /** 629 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API 630 */ 631 static void zynqmp_get_clock_info(void) 632 { 633 int i, ret; 634 u32 attr, type = 0, nodetype, subclass, class; 635 636 for (i = 0; i < clock_max_idx; i++) { 637 ret = zynqmp_pm_clock_get_attributes(i, &attr); 638 if (ret) 639 continue; 640 641 clock[i].valid = attr & CLK_VALID_MASK; 642 clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ? 643 CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT; 644 nodetype = (attr >> NODE_TYPE_SHIFT) & 0x3F; 645 subclass = (attr >> NODE_SUBCLASS_SHIFT) & 0x3F; 646 class = (attr >> NODE_CLASS_SHIFT) & 0x3F; 647 648 clock[i].clk_id = (class << NODE_CLASS_SHIFT) | 649 (subclass << NODE_SUBCLASS_SHIFT) | 650 (nodetype << NODE_TYPE_SHIFT) | 651 (i << NODE_INDEX_SHIFT); 652 653 zynqmp_pm_clock_get_name(clock[i].clk_id, clock[i].clk_name); 654 } 655 656 /* Get topology of all clock */ 657 for (i = 0; i < clock_max_idx; i++) { 658 ret = zynqmp_get_clock_type(i, &type); 659 if (ret || type != CLK_TYPE_OUTPUT) 660 continue; 661 662 ret = zynqmp_clock_get_topology(i, clock[i].node, 663 &clock[i].num_nodes); 664 if (ret) 665 continue; 666 667 ret = zynqmp_clock_get_parents(i, clock[i].parent, 668 &clock[i].num_parents); 669 if (ret) 670 continue; 671 } 672 } 673 674 /** 675 * zynqmp_clk_setup() - Setup the clock framework and register clocks 676 * @np: Device node 677 * 678 * Return: 0 on success else error code 679 */ 680 static int zynqmp_clk_setup(struct device_node *np) 681 { 682 int ret; 683 684 ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx); 685 if (ret) 686 return ret; 687 688 zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx), 689 GFP_KERNEL); 690 if (!zynqmp_data) 691 return -ENOMEM; 692 693 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL); 694 if (!clock) { 695 kfree(zynqmp_data); 696 return -ENOMEM; 697 } 698 699 zynqmp_get_clock_info(); 700 zynqmp_register_clocks(np); 701 702 zynqmp_data->num = clock_max_idx; 703 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data); 704 705 return 0; 706 } 707 708 static int zynqmp_clock_probe(struct platform_device *pdev) 709 { 710 int ret; 711 struct device *dev = &pdev->dev; 712 713 eemi_ops = zynqmp_pm_get_eemi_ops(); 714 if (!eemi_ops) 715 return -ENXIO; 716 717 ret = zynqmp_clk_setup(dev->of_node); 718 719 return ret; 720 } 721 722 static const struct of_device_id zynqmp_clock_of_match[] = { 723 {.compatible = "xlnx,zynqmp-clk"}, 724 {}, 725 }; 726 MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match); 727 728 static struct platform_driver zynqmp_clock_driver = { 729 .driver = { 730 .name = "zynqmp_clock", 731 .of_match_table = zynqmp_clock_of_match, 732 }, 733 .probe = zynqmp_clock_probe, 734 }; 735 module_platform_driver(zynqmp_clock_driver); 736