1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC clock controller 4 * 5 * Copyright (C) 2016-2019 Xilinx 6 * 7 * Based on drivers/clk/zynq/clkc.c 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/slab.h> 16 #include <linux/string.h> 17 18 #include "clk-zynqmp.h" 19 20 #define MAX_PARENT 100 21 #define MAX_NODES 6 22 #define MAX_NAME_LEN 50 23 24 /* Flags for parents */ 25 #define PARENT_CLK_SELF 0 26 #define PARENT_CLK_NODE1 1 27 #define PARENT_CLK_NODE2 2 28 #define PARENT_CLK_NODE3 3 29 #define PARENT_CLK_NODE4 4 30 #define PARENT_CLK_EXTERNAL 5 31 32 #define END_OF_CLK_NAME "END_OF_CLK" 33 #define END_OF_TOPOLOGY_NODE 1 34 #define END_OF_PARENTS 1 35 #define RESERVED_CLK_NAME "" 36 37 #define CLK_GET_NAME_RESP_LEN 16 38 #define CLK_GET_TOPOLOGY_RESP_WORDS 3 39 #define CLK_GET_PARENTS_RESP_WORDS 3 40 #define CLK_GET_ATTR_RESP_WORDS 1 41 42 enum clk_type { 43 CLK_TYPE_OUTPUT, 44 CLK_TYPE_EXTERNAL, 45 }; 46 47 /** 48 * struct clock_parent - Clock parent 49 * @name: Parent name 50 * @id: Parent clock ID 51 * @flag: Parent flags 52 */ 53 struct clock_parent { 54 char name[MAX_NAME_LEN]; 55 int id; 56 u32 flag; 57 }; 58 59 /** 60 * struct zynqmp_clock - Clock 61 * @clk_name: Clock name 62 * @valid: Validity flag of clock 63 * @type: Clock type (Output/External) 64 * @node: Clock topology nodes 65 * @num_nodes: Number of nodes present in topology 66 * @parent: Parent of clock 67 * @num_parents: Number of parents of clock 68 * @clk_id: Clock id 69 */ 70 struct zynqmp_clock { 71 char clk_name[MAX_NAME_LEN]; 72 u32 valid; 73 enum clk_type type; 74 struct clock_topology node[MAX_NODES]; 75 u32 num_nodes; 76 struct clock_parent parent[MAX_PARENT]; 77 u32 num_parents; 78 u32 clk_id; 79 }; 80 81 struct name_resp { 82 char name[CLK_GET_NAME_RESP_LEN]; 83 }; 84 85 struct topology_resp { 86 #define CLK_TOPOLOGY_TYPE GENMASK(3, 0) 87 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8) 88 #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24) 89 u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS]; 90 }; 91 92 struct parents_resp { 93 #define NA_PARENT 0xFFFFFFFF 94 #define DUMMY_PARENT 0xFFFFFFFE 95 #define CLK_PARENTS_ID GENMASK(15, 0) 96 #define CLK_PARENTS_FLAGS GENMASK(31, 16) 97 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; 98 }; 99 100 struct attr_resp { 101 #define CLK_ATTR_VALID BIT(0) 102 #define CLK_ATTR_TYPE BIT(2) 103 #define CLK_ATTR_NODE_INDEX GENMASK(13, 0) 104 #define CLK_ATTR_NODE_TYPE GENMASK(19, 14) 105 #define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20) 106 #define CLK_ATTR_NODE_CLASS GENMASK(31, 26) 107 u32 attr[CLK_GET_ATTR_RESP_WORDS]; 108 }; 109 110 static const char clk_type_postfix[][10] = { 111 [TYPE_INVALID] = "", 112 [TYPE_MUX] = "_mux", 113 [TYPE_GATE] = "", 114 [TYPE_DIV1] = "_div1", 115 [TYPE_DIV2] = "_div2", 116 [TYPE_FIXEDFACTOR] = "_ff", 117 [TYPE_PLL] = "" 118 }; 119 120 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id, 121 const char * const *parents, 122 u8 num_parents, 123 const struct clock_topology *nodes) 124 = { 125 [TYPE_INVALID] = NULL, 126 [TYPE_MUX] = zynqmp_clk_register_mux, 127 [TYPE_PLL] = zynqmp_clk_register_pll, 128 [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor, 129 [TYPE_DIV1] = zynqmp_clk_register_divider, 130 [TYPE_DIV2] = zynqmp_clk_register_divider, 131 [TYPE_GATE] = zynqmp_clk_register_gate 132 }; 133 134 static struct zynqmp_clock *clock; 135 static struct clk_hw_onecell_data *zynqmp_data; 136 static unsigned int clock_max_idx; 137 138 /** 139 * zynqmp_is_valid_clock() - Check whether clock is valid or not 140 * @clk_id: Clock index 141 * 142 * Return: 1 if clock is valid, 0 if clock is invalid else error code 143 */ 144 static inline int zynqmp_is_valid_clock(u32 clk_id) 145 { 146 if (clk_id >= clock_max_idx) 147 return -ENODEV; 148 149 return clock[clk_id].valid; 150 } 151 152 /** 153 * zynqmp_get_clock_name() - Get name of clock from Clock index 154 * @clk_id: Clock index 155 * @clk_name: Name of clock 156 * 157 * Return: 0 on success else error code 158 */ 159 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) 160 { 161 int ret; 162 163 ret = zynqmp_is_valid_clock(clk_id); 164 if (ret == 1) { 165 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); 166 return 0; 167 } 168 169 return ret == 0 ? -EINVAL : ret; 170 } 171 172 /** 173 * zynqmp_get_clock_type() - Get type of clock 174 * @clk_id: Clock index 175 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL 176 * 177 * Return: 0 on success else error code 178 */ 179 static int zynqmp_get_clock_type(u32 clk_id, u32 *type) 180 { 181 int ret; 182 183 ret = zynqmp_is_valid_clock(clk_id); 184 if (ret == 1) { 185 *type = clock[clk_id].type; 186 return 0; 187 } 188 189 return ret == 0 ? -EINVAL : ret; 190 } 191 192 /** 193 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system 194 * @nclocks: Number of clocks in system/board. 195 * 196 * Call firmware API to get number of clocks. 197 * 198 * Return: 0 on success else error code. 199 */ 200 static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks) 201 { 202 struct zynqmp_pm_query_data qdata = {0}; 203 u32 ret_payload[PAYLOAD_ARG_CNT]; 204 int ret; 205 206 qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS; 207 208 ret = zynqmp_pm_query_data(qdata, ret_payload); 209 *nclocks = ret_payload[1]; 210 211 return ret; 212 } 213 214 /** 215 * zynqmp_pm_clock_get_name() - Get the name of clock for given id 216 * @clock_id: ID of the clock to be queried 217 * @response: Name of the clock with the given id 218 * 219 * This function is used to get name of clock specified by given 220 * clock ID. 221 * 222 * Return: Returns 0 223 */ 224 static int zynqmp_pm_clock_get_name(u32 clock_id, 225 struct name_resp *response) 226 { 227 struct zynqmp_pm_query_data qdata = {0}; 228 u32 ret_payload[PAYLOAD_ARG_CNT]; 229 230 qdata.qid = PM_QID_CLOCK_GET_NAME; 231 qdata.arg1 = clock_id; 232 233 zynqmp_pm_query_data(qdata, ret_payload); 234 memcpy(response, ret_payload, sizeof(*response)); 235 236 return 0; 237 } 238 239 /** 240 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id 241 * @clock_id: ID of the clock to be queried 242 * @index: Node index of clock topology 243 * @response: Buffer used for the topology response 244 * 245 * This function is used to get topology information for the clock 246 * specified by given clock ID. 247 * 248 * This API will return 3 node of topology with a single response. To get 249 * other nodes, master should call same API in loop with new 250 * index till error is returned. E.g First call should have 251 * index 0 which will return nodes 0,1 and 2. Next call, index 252 * should be 3 which will return nodes 3,4 and 5 and so on. 253 * 254 * Return: 0 on success else error+reason 255 */ 256 static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, 257 struct topology_resp *response) 258 { 259 struct zynqmp_pm_query_data qdata = {0}; 260 u32 ret_payload[PAYLOAD_ARG_CNT]; 261 int ret; 262 263 qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY; 264 qdata.arg1 = clock_id; 265 qdata.arg2 = index; 266 267 ret = zynqmp_pm_query_data(qdata, ret_payload); 268 memcpy(response, &ret_payload[1], sizeof(*response)); 269 270 return ret; 271 } 272 273 /** 274 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the 275 * clock framework 276 * @name: Name of this clock 277 * @clk_id: Clock ID 278 * @parents: Name of this clock's parents 279 * @num_parents: Number of parents 280 * @nodes: Clock topology node 281 * 282 * Return: clock hardware to the registered clock 283 */ 284 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, 285 const char * const *parents, 286 u8 num_parents, 287 const struct clock_topology *nodes) 288 { 289 u32 mult, div; 290 struct clk_hw *hw; 291 struct zynqmp_pm_query_data qdata = {0}; 292 u32 ret_payload[PAYLOAD_ARG_CNT]; 293 int ret; 294 295 qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; 296 qdata.arg1 = clk_id; 297 298 ret = zynqmp_pm_query_data(qdata, ret_payload); 299 if (ret) 300 return ERR_PTR(ret); 301 302 mult = ret_payload[1]; 303 div = ret_payload[2]; 304 305 hw = clk_hw_register_fixed_factor(NULL, name, 306 parents[0], 307 nodes->flag, mult, 308 div); 309 310 return hw; 311 } 312 313 /** 314 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id 315 * @clock_id: Clock ID 316 * @index: Parent index 317 * @response: Parents of the given clock 318 * 319 * This function is used to get 3 parents for the clock specified by 320 * given clock ID. 321 * 322 * This API will return 3 parents with a single response. To get 323 * other parents, master should call same API in loop with new 324 * parent index till error is returned. E.g First call should have 325 * index 0 which will return parents 0,1 and 2. Next call, index 326 * should be 3 which will return parent 3,4 and 5 and so on. 327 * 328 * Return: 0 on success else error+reason 329 */ 330 static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, 331 struct parents_resp *response) 332 { 333 struct zynqmp_pm_query_data qdata = {0}; 334 u32 ret_payload[PAYLOAD_ARG_CNT]; 335 int ret; 336 337 qdata.qid = PM_QID_CLOCK_GET_PARENTS; 338 qdata.arg1 = clock_id; 339 qdata.arg2 = index; 340 341 ret = zynqmp_pm_query_data(qdata, ret_payload); 342 memcpy(response, &ret_payload[1], sizeof(*response)); 343 344 return ret; 345 } 346 347 /** 348 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id 349 * @clock_id: Clock ID 350 * @response: Clock attributes response 351 * 352 * This function is used to get clock's attributes(e.g. valid, clock type, etc). 353 * 354 * Return: 0 on success else error+reason 355 */ 356 static int zynqmp_pm_clock_get_attributes(u32 clock_id, 357 struct attr_resp *response) 358 { 359 struct zynqmp_pm_query_data qdata = {0}; 360 u32 ret_payload[PAYLOAD_ARG_CNT]; 361 int ret; 362 363 qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES; 364 qdata.arg1 = clock_id; 365 366 ret = zynqmp_pm_query_data(qdata, ret_payload); 367 memcpy(response, &ret_payload[1], sizeof(*response)); 368 369 return ret; 370 } 371 372 /** 373 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware 374 * response data 375 * @topology: Clock topology 376 * @response: Clock topology data received from firmware 377 * @nnodes: Number of nodes 378 * 379 * Return: 0 on success else error+reason 380 */ 381 static int __zynqmp_clock_get_topology(struct clock_topology *topology, 382 struct topology_resp *response, 383 u32 *nnodes) 384 { 385 int i; 386 u32 type; 387 388 for (i = 0; i < ARRAY_SIZE(response->topology); i++) { 389 type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]); 390 if (type == TYPE_INVALID) 391 return END_OF_TOPOLOGY_NODE; 392 topology[*nnodes].type = type; 393 topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS, 394 response->topology[i]); 395 topology[*nnodes].type_flag = 396 FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS, 397 response->topology[i]); 398 (*nnodes)++; 399 } 400 401 return 0; 402 } 403 404 /** 405 * zynqmp_clock_get_topology() - Get topology of clock from firmware using 406 * PM_API 407 * @clk_id: Clock index 408 * @topology: Clock topology 409 * @num_nodes: Number of nodes 410 * 411 * Return: 0 on success else error+reason 412 */ 413 static int zynqmp_clock_get_topology(u32 clk_id, 414 struct clock_topology *topology, 415 u32 *num_nodes) 416 { 417 int j, ret; 418 struct topology_resp response = { }; 419 420 *num_nodes = 0; 421 for (j = 0; j <= MAX_NODES; j += ARRAY_SIZE(response.topology)) { 422 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j, 423 &response); 424 if (ret) 425 return ret; 426 ret = __zynqmp_clock_get_topology(topology, &response, 427 num_nodes); 428 if (ret == END_OF_TOPOLOGY_NODE) 429 return 0; 430 } 431 432 return 0; 433 } 434 435 /** 436 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware 437 * response data 438 * @parents: Clock parents 439 * @response: Clock parents data received from firmware 440 * @nparent: Number of parent 441 * 442 * Return: 0 on success else error+reason 443 */ 444 static int __zynqmp_clock_get_parents(struct clock_parent *parents, 445 struct parents_resp *response, 446 u32 *nparent) 447 { 448 int i; 449 struct clock_parent *parent; 450 451 for (i = 0; i < ARRAY_SIZE(response->parents); i++) { 452 if (response->parents[i] == NA_PARENT) 453 return END_OF_PARENTS; 454 455 parent = &parents[i]; 456 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]); 457 if (response->parents[i] == DUMMY_PARENT) { 458 strcpy(parent->name, "dummy_name"); 459 parent->flag = 0; 460 } else { 461 parent->flag = FIELD_GET(CLK_PARENTS_FLAGS, 462 response->parents[i]); 463 if (zynqmp_get_clock_name(parent->id, parent->name)) 464 continue; 465 } 466 *nparent += 1; 467 } 468 469 return 0; 470 } 471 472 /** 473 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API 474 * @clk_id: Clock index 475 * @parents: Clock parents 476 * @num_parents: Total number of parents 477 * 478 * Return: 0 on success else error+reason 479 */ 480 static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, 481 u32 *num_parents) 482 { 483 int j = 0, ret; 484 struct parents_resp response = { }; 485 486 *num_parents = 0; 487 do { 488 /* Get parents from firmware */ 489 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j, 490 &response); 491 if (ret) 492 return ret; 493 494 ret = __zynqmp_clock_get_parents(&parents[j], &response, 495 num_parents); 496 if (ret == END_OF_PARENTS) 497 return 0; 498 j += ARRAY_SIZE(response.parents); 499 } while (*num_parents <= MAX_PARENT); 500 501 return 0; 502 } 503 504 /** 505 * zynqmp_get_parent_list() - Create list of parents name 506 * @np: Device node 507 * @clk_id: Clock index 508 * @parent_list: List of parent's name 509 * @num_parents: Total number of parents 510 * 511 * Return: 0 on success else error+reason 512 */ 513 static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id, 514 const char **parent_list, u32 *num_parents) 515 { 516 int i = 0, ret; 517 u32 total_parents = clock[clk_id].num_parents; 518 struct clock_topology *clk_nodes; 519 struct clock_parent *parents; 520 521 clk_nodes = clock[clk_id].node; 522 parents = clock[clk_id].parent; 523 524 for (i = 0; i < total_parents; i++) { 525 if (!parents[i].flag) { 526 parent_list[i] = parents[i].name; 527 } else if (parents[i].flag == PARENT_CLK_EXTERNAL) { 528 ret = of_property_match_string(np, "clock-names", 529 parents[i].name); 530 if (ret < 0) 531 strcpy(parents[i].name, "dummy_name"); 532 parent_list[i] = parents[i].name; 533 } else { 534 strcat(parents[i].name, 535 clk_type_postfix[clk_nodes[parents[i].flag - 1]. 536 type]); 537 parent_list[i] = parents[i].name; 538 } 539 } 540 541 *num_parents = total_parents; 542 return 0; 543 } 544 545 /** 546 * zynqmp_register_clk_topology() - Register clock topology 547 * @clk_id: Clock index 548 * @clk_name: Clock Name 549 * @num_parents: Total number of parents 550 * @parent_names: List of parents name 551 * 552 * Return: Returns either clock hardware or error+reason 553 */ 554 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, 555 int num_parents, 556 const char **parent_names) 557 { 558 int j; 559 u32 num_nodes, clk_dev_id; 560 char *clk_out = NULL; 561 struct clock_topology *nodes; 562 struct clk_hw *hw = NULL; 563 564 nodes = clock[clk_id].node; 565 num_nodes = clock[clk_id].num_nodes; 566 clk_dev_id = clock[clk_id].clk_id; 567 568 for (j = 0; j < num_nodes; j++) { 569 /* 570 * Clock name received from firmware is output clock name. 571 * Intermediate clock names are postfixed with type of clock. 572 */ 573 if (j != (num_nodes - 1)) { 574 clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name, 575 clk_type_postfix[nodes[j].type]); 576 } else { 577 clk_out = kasprintf(GFP_KERNEL, "%s", clk_name); 578 } 579 580 if (!clk_topology[nodes[j].type]) 581 continue; 582 583 hw = (*clk_topology[nodes[j].type])(clk_out, clk_dev_id, 584 parent_names, 585 num_parents, 586 &nodes[j]); 587 if (IS_ERR(hw)) 588 pr_warn_once("%s() 0x%x: %s register fail with %ld\n", 589 __func__, clk_dev_id, clk_name, 590 PTR_ERR(hw)); 591 592 parent_names[0] = clk_out; 593 } 594 kfree(clk_out); 595 return hw; 596 } 597 598 /** 599 * zynqmp_register_clocks() - Register clocks 600 * @np: Device node 601 * 602 * Return: 0 on success else error code 603 */ 604 static int zynqmp_register_clocks(struct device_node *np) 605 { 606 int ret; 607 u32 i, total_parents = 0, type = 0; 608 const char *parent_names[MAX_PARENT]; 609 610 for (i = 0; i < clock_max_idx; i++) { 611 char clk_name[MAX_NAME_LEN]; 612 613 /* get clock name, continue to next clock if name not found */ 614 if (zynqmp_get_clock_name(i, clk_name)) 615 continue; 616 617 /* Check if clock is valid and output clock. 618 * Do not register invalid or external clock. 619 */ 620 ret = zynqmp_get_clock_type(i, &type); 621 if (ret || type != CLK_TYPE_OUTPUT) 622 continue; 623 624 /* Get parents of clock*/ 625 if (zynqmp_get_parent_list(np, i, parent_names, 626 &total_parents)) { 627 WARN_ONCE(1, "No parents found for %s\n", 628 clock[i].clk_name); 629 continue; 630 } 631 632 zynqmp_data->hws[i] = 633 zynqmp_register_clk_topology(i, clk_name, 634 total_parents, 635 parent_names); 636 } 637 638 for (i = 0; i < clock_max_idx; i++) { 639 if (IS_ERR(zynqmp_data->hws[i])) { 640 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", 641 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i])); 642 WARN_ON(1); 643 } 644 } 645 return 0; 646 } 647 648 /** 649 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API 650 */ 651 static void zynqmp_get_clock_info(void) 652 { 653 int i, ret; 654 u32 type = 0; 655 u32 nodetype, subclass, class; 656 struct attr_resp attr; 657 struct name_resp name; 658 659 for (i = 0; i < clock_max_idx; i++) { 660 ret = zynqmp_pm_clock_get_attributes(i, &attr); 661 if (ret) 662 continue; 663 664 clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]); 665 clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ? 666 CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT; 667 668 nodetype = FIELD_GET(CLK_ATTR_NODE_TYPE, attr.attr[0]); 669 subclass = FIELD_GET(CLK_ATTR_NODE_SUBCLASS, attr.attr[0]); 670 class = FIELD_GET(CLK_ATTR_NODE_CLASS, attr.attr[0]); 671 672 clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) | 673 FIELD_PREP(CLK_ATTR_NODE_SUBCLASS, subclass) | 674 FIELD_PREP(CLK_ATTR_NODE_TYPE, nodetype) | 675 FIELD_PREP(CLK_ATTR_NODE_INDEX, i); 676 677 zynqmp_pm_clock_get_name(clock[i].clk_id, &name); 678 if (!strcmp(name.name, RESERVED_CLK_NAME)) 679 continue; 680 strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN); 681 } 682 683 /* Get topology of all clock */ 684 for (i = 0; i < clock_max_idx; i++) { 685 ret = zynqmp_get_clock_type(i, &type); 686 if (ret || type != CLK_TYPE_OUTPUT) 687 continue; 688 689 ret = zynqmp_clock_get_topology(i, clock[i].node, 690 &clock[i].num_nodes); 691 if (ret) 692 continue; 693 694 ret = zynqmp_clock_get_parents(i, clock[i].parent, 695 &clock[i].num_parents); 696 if (ret) 697 continue; 698 } 699 } 700 701 /** 702 * zynqmp_clk_setup() - Setup the clock framework and register clocks 703 * @np: Device node 704 * 705 * Return: 0 on success else error code 706 */ 707 static int zynqmp_clk_setup(struct device_node *np) 708 { 709 int ret; 710 711 ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx); 712 if (ret) 713 return ret; 714 715 zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx), 716 GFP_KERNEL); 717 if (!zynqmp_data) 718 return -ENOMEM; 719 720 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL); 721 if (!clock) { 722 kfree(zynqmp_data); 723 return -ENOMEM; 724 } 725 726 zynqmp_get_clock_info(); 727 zynqmp_register_clocks(np); 728 729 zynqmp_data->num = clock_max_idx; 730 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data); 731 732 return 0; 733 } 734 735 static int zynqmp_clock_probe(struct platform_device *pdev) 736 { 737 int ret; 738 struct device *dev = &pdev->dev; 739 740 ret = zynqmp_clk_setup(dev->of_node); 741 742 return ret; 743 } 744 745 static const struct of_device_id zynqmp_clock_of_match[] = { 746 {.compatible = "xlnx,zynqmp-clk"}, 747 {.compatible = "xlnx,versal-clk"}, 748 {}, 749 }; 750 MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match); 751 752 static struct platform_driver zynqmp_clock_driver = { 753 .driver = { 754 .name = "zynqmp_clock", 755 .of_match_table = zynqmp_clock_of_match, 756 }, 757 .probe = zynqmp_clock_probe, 758 }; 759 module_platform_driver(zynqmp_clock_driver); 760