1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2016-2018 Xilinx 4 */ 5 6 #ifndef __LINUX_CLK_ZYNQMP_H_ 7 #define __LINUX_CLK_ZYNQMP_H_ 8 9 #include <linux/spinlock.h> 10 11 #include <linux/firmware/xlnx-zynqmp.h> 12 13 enum topology_type { 14 TYPE_INVALID, 15 TYPE_MUX, 16 TYPE_PLL, 17 TYPE_FIXEDFACTOR, 18 TYPE_DIV1, 19 TYPE_DIV2, 20 TYPE_GATE, 21 }; 22 23 /** 24 * struct clock_topology - Clock topology 25 * @type: Type of topology 26 * @flag: Topology flags 27 * @type_flag: Topology type specific flag 28 */ 29 struct clock_topology { 30 u32 type; 31 u32 flag; 32 u32 type_flag; 33 }; 34 35 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, 36 const char * const *parents, 37 u8 num_parents, 38 const struct clock_topology *nodes); 39 40 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, 41 const char * const *parents, 42 u8 num_parents, 43 const struct clock_topology *nodes); 44 45 struct clk_hw *zynqmp_clk_register_divider(const char *name, 46 u32 clk_id, 47 const char * const *parents, 48 u8 num_parents, 49 const struct clock_topology *nodes); 50 51 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, 52 const char * const *parents, 53 u8 num_parents, 54 const struct clock_topology *nodes); 55 56 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, 57 u32 clk_id, 58 const char * const *parents, 59 u8 num_parents, 60 const struct clock_topology *nodes); 61 62 #endif 63