1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Zynq UltraScale+ MPSoC mux 4 * 5 * Copyright (C) 2016-2018 Xilinx 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/slab.h> 10 #include "clk-zynqmp.h" 11 12 /* 13 * DOC: basic adjustable multiplexer clock that cannot gate 14 * 15 * Traits of this clock: 16 * prepare - clk_prepare only ensures that parents are prepared 17 * enable - clk_enable only ensures that parents are enabled 18 * rate - rate is only affected by parent switching. No clk_set_rate support 19 * parent - parent is adjustable through clk_set_parent 20 */ 21 22 /** 23 * struct zynqmp_clk_mux - multiplexer clock 24 * 25 * @hw: handle between common and hardware-specific interfaces 26 * @flags: hardware-specific flags 27 * @clk_id: Id of clock 28 */ 29 struct zynqmp_clk_mux { 30 struct clk_hw hw; 31 u8 flags; 32 u32 clk_id; 33 }; 34 35 #define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw) 36 37 /** 38 * zynqmp_clk_mux_get_parent() - Get parent of clock 39 * @hw: handle between common and hardware-specific interfaces 40 * 41 * Return: Parent index 42 */ 43 static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) 44 { 45 struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); 46 const char *clk_name = clk_hw_get_name(hw); 47 u32 clk_id = mux->clk_id; 48 u32 val; 49 int ret; 50 51 ret = zynqmp_pm_clock_getparent(clk_id, &val); 52 53 if (ret) 54 pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n", 55 __func__, clk_name, ret); 56 57 return val; 58 } 59 60 /** 61 * zynqmp_clk_mux_set_parent() - Set parent of clock 62 * @hw: handle between common and hardware-specific interfaces 63 * @index: Parent index 64 * 65 * Return: 0 on success else error+reason 66 */ 67 static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) 68 { 69 struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); 70 const char *clk_name = clk_hw_get_name(hw); 71 u32 clk_id = mux->clk_id; 72 int ret; 73 74 ret = zynqmp_pm_clock_setparent(clk_id, index); 75 76 if (ret) 77 pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n", 78 __func__, clk_name, ret); 79 80 return ret; 81 } 82 83 static const struct clk_ops zynqmp_clk_mux_ops = { 84 .get_parent = zynqmp_clk_mux_get_parent, 85 .set_parent = zynqmp_clk_mux_set_parent, 86 .determine_rate = __clk_mux_determine_rate, 87 }; 88 89 static const struct clk_ops zynqmp_clk_mux_ro_ops = { 90 .get_parent = zynqmp_clk_mux_get_parent, 91 }; 92 93 /** 94 * zynqmp_clk_register_mux() - Register a mux table with the clock 95 * framework 96 * @name: Name of this clock 97 * @clk_id: Id of this clock 98 * @parents: Name of this clock's parents 99 * @num_parents: Number of parents 100 * @nodes: Clock topology node 101 * 102 * Return: clock hardware of the registered clock mux 103 */ 104 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, 105 const char * const *parents, 106 u8 num_parents, 107 const struct clock_topology *nodes) 108 { 109 struct zynqmp_clk_mux *mux; 110 struct clk_hw *hw; 111 struct clk_init_data init; 112 int ret; 113 114 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 115 if (!mux) 116 return ERR_PTR(-ENOMEM); 117 118 init.name = name; 119 if (nodes->type_flag & CLK_MUX_READ_ONLY) 120 init.ops = &zynqmp_clk_mux_ro_ops; 121 else 122 init.ops = &zynqmp_clk_mux_ops; 123 init.flags = nodes->flag; 124 init.parent_names = parents; 125 init.num_parents = num_parents; 126 mux->flags = nodes->type_flag; 127 mux->hw.init = &init; 128 mux->clk_id = clk_id; 129 130 hw = &mux->hw; 131 ret = clk_hw_register(NULL, hw); 132 if (ret) { 133 kfree(hw); 134 hw = ERR_PTR(ret); 135 } 136 137 return hw; 138 } 139