xref: /openbmc/linux/drivers/clk/zynq/clkc.c (revision 92a2c6b2)
1 /*
2  * Zynq clock controller
3  *
4  *  Copyright (C) 2012 - 2013 Xilinx
5  *
6  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
7  *
8  * This program is free software: you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License v2 as published by
10  * the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include <linux/clk/zynq.h>
22 #include <linux/clk-provider.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/io.h>
28 
29 static void __iomem *zynq_clkc_base;
30 
31 #define SLCR_ARMPLL_CTRL		(zynq_clkc_base + 0x00)
32 #define SLCR_DDRPLL_CTRL		(zynq_clkc_base + 0x04)
33 #define SLCR_IOPLL_CTRL			(zynq_clkc_base + 0x08)
34 #define SLCR_PLL_STATUS			(zynq_clkc_base + 0x0c)
35 #define SLCR_ARM_CLK_CTRL		(zynq_clkc_base + 0x20)
36 #define SLCR_DDR_CLK_CTRL		(zynq_clkc_base + 0x24)
37 #define SLCR_DCI_CLK_CTRL		(zynq_clkc_base + 0x28)
38 #define SLCR_APER_CLK_CTRL		(zynq_clkc_base + 0x2c)
39 #define SLCR_GEM0_CLK_CTRL		(zynq_clkc_base + 0x40)
40 #define SLCR_GEM1_CLK_CTRL		(zynq_clkc_base + 0x44)
41 #define SLCR_SMC_CLK_CTRL		(zynq_clkc_base + 0x48)
42 #define SLCR_LQSPI_CLK_CTRL		(zynq_clkc_base + 0x4c)
43 #define SLCR_SDIO_CLK_CTRL		(zynq_clkc_base + 0x50)
44 #define SLCR_UART_CLK_CTRL		(zynq_clkc_base + 0x54)
45 #define SLCR_SPI_CLK_CTRL		(zynq_clkc_base + 0x58)
46 #define SLCR_CAN_CLK_CTRL		(zynq_clkc_base + 0x5c)
47 #define SLCR_CAN_MIOCLK_CTRL		(zynq_clkc_base + 0x60)
48 #define SLCR_DBG_CLK_CTRL		(zynq_clkc_base + 0x64)
49 #define SLCR_PCAP_CLK_CTRL		(zynq_clkc_base + 0x68)
50 #define SLCR_FPGA0_CLK_CTRL		(zynq_clkc_base + 0x70)
51 #define SLCR_621_TRUE			(zynq_clkc_base + 0xc4)
52 #define SLCR_SWDT_CLK_SEL		(zynq_clkc_base + 0x204)
53 
54 #define NUM_MIO_PINS	54
55 
56 #define DBG_CLK_CTRL_CLKACT_TRC		BIT(0)
57 #define DBG_CLK_CTRL_CPU_1XCLKACT	BIT(1)
58 
59 enum zynq_clk {
60 	armpll, ddrpll, iopll,
61 	cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
62 	ddr2x, ddr3x, dci,
63 	lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
64 	sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
65 	usb0_aper, usb1_aper, gem0_aper, gem1_aper,
66 	sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
67 	i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
68 	smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
69 
70 static struct clk *ps_clk;
71 static struct clk *clks[clk_max];
72 static struct clk_onecell_data clk_data;
73 
74 static DEFINE_SPINLOCK(armpll_lock);
75 static DEFINE_SPINLOCK(ddrpll_lock);
76 static DEFINE_SPINLOCK(iopll_lock);
77 static DEFINE_SPINLOCK(armclk_lock);
78 static DEFINE_SPINLOCK(swdtclk_lock);
79 static DEFINE_SPINLOCK(ddrclk_lock);
80 static DEFINE_SPINLOCK(dciclk_lock);
81 static DEFINE_SPINLOCK(gem0clk_lock);
82 static DEFINE_SPINLOCK(gem1clk_lock);
83 static DEFINE_SPINLOCK(canclk_lock);
84 static DEFINE_SPINLOCK(canmioclk_lock);
85 static DEFINE_SPINLOCK(dbgclk_lock);
86 static DEFINE_SPINLOCK(aperclk_lock);
87 
88 static const char *armpll_parents[] __initconst = {"armpll_int", "ps_clk"};
89 static const char *ddrpll_parents[] __initconst = {"ddrpll_int", "ps_clk"};
90 static const char *iopll_parents[] __initconst = {"iopll_int", "ps_clk"};
91 static const char *gem0_mux_parents[] __initconst = {"gem0_div1", "dummy_name"};
92 static const char *gem1_mux_parents[] __initconst = {"gem1_div1", "dummy_name"};
93 static const char *can0_mio_mux2_parents[] __initconst = {"can0_gate",
94 	"can0_mio_mux"};
95 static const char *can1_mio_mux2_parents[] __initconst = {"can1_gate",
96 	"can1_mio_mux"};
97 static const char *dbg_emio_mux_parents[] __initconst = {"dbg_div",
98 	"dummy_name"};
99 
100 static const char *dbgtrc_emio_input_names[] __initconst = {"trace_emio_clk"};
101 static const char *gem0_emio_input_names[] __initconst = {"gem0_emio_clk"};
102 static const char *gem1_emio_input_names[] __initconst = {"gem1_emio_clk"};
103 static const char *swdt_ext_clk_input_names[] __initconst = {"swdt_ext_clk"};
104 
105 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
106 		const char *clk_name, void __iomem *fclk_ctrl_reg,
107 		const char **parents, int enable)
108 {
109 	struct clk *clk;
110 	u32 enable_reg;
111 	char *mux_name;
112 	char *div0_name;
113 	char *div1_name;
114 	spinlock_t *fclk_lock;
115 	spinlock_t *fclk_gate_lock;
116 	void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
117 
118 	fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
119 	if (!fclk_lock)
120 		goto err;
121 	fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
122 	if (!fclk_gate_lock)
123 		goto err_fclk_gate_lock;
124 	spin_lock_init(fclk_lock);
125 	spin_lock_init(fclk_gate_lock);
126 
127 	mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
128 	if (!mux_name)
129 		goto err_mux_name;
130 	div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
131 	if (!div0_name)
132 		goto err_div0_name;
133 	div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
134 	if (!div1_name)
135 		goto err_div1_name;
136 
137 	clk = clk_register_mux(NULL, mux_name, parents, 4,
138 			CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
139 			fclk_lock);
140 
141 	clk = clk_register_divider(NULL, div0_name, mux_name,
142 			0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
143 			CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
144 
145 	clk = clk_register_divider(NULL, div1_name, div0_name,
146 			CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
147 			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
148 			fclk_lock);
149 
150 	clks[fclk] = clk_register_gate(NULL, clk_name,
151 			div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
152 			0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
153 	enable_reg = clk_readl(fclk_gate_reg) & 1;
154 	if (enable && !enable_reg) {
155 		if (clk_prepare_enable(clks[fclk]))
156 			pr_warn("%s: FCLK%u enable failed\n", __func__,
157 					fclk - fclk0);
158 	}
159 	kfree(mux_name);
160 	kfree(div0_name);
161 	kfree(div1_name);
162 
163 	return;
164 
165 err_div1_name:
166 	kfree(div0_name);
167 err_div0_name:
168 	kfree(mux_name);
169 err_mux_name:
170 	kfree(fclk_gate_lock);
171 err_fclk_gate_lock:
172 	kfree(fclk_lock);
173 err:
174 	clks[fclk] = ERR_PTR(-ENOMEM);
175 }
176 
177 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
178 		enum zynq_clk clk1, const char *clk_name0,
179 		const char *clk_name1, void __iomem *clk_ctrl,
180 		const char **parents, unsigned int two_gates)
181 {
182 	struct clk *clk;
183 	char *mux_name;
184 	char *div_name;
185 	spinlock_t *lock;
186 
187 	lock = kmalloc(sizeof(*lock), GFP_KERNEL);
188 	if (!lock)
189 		goto err;
190 	spin_lock_init(lock);
191 
192 	mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
193 	div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
194 
195 	clk = clk_register_mux(NULL, mux_name, parents, 4,
196 			CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
197 
198 	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
199 			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
200 
201 	clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
202 			CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
203 	if (two_gates)
204 		clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
205 				CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
206 
207 	kfree(mux_name);
208 	kfree(div_name);
209 
210 	return;
211 
212 err:
213 	clks[clk0] = ERR_PTR(-ENOMEM);
214 	if (two_gates)
215 		clks[clk1] = ERR_PTR(-ENOMEM);
216 }
217 
218 static void __init zynq_clk_setup(struct device_node *np)
219 {
220 	int i;
221 	u32 tmp;
222 	int ret;
223 	struct clk *clk;
224 	char *clk_name;
225 	unsigned int fclk_enable = 0;
226 	const char *clk_output_name[clk_max];
227 	const char *cpu_parents[4];
228 	const char *periph_parents[4];
229 	const char *swdt_ext_clk_mux_parents[2];
230 	const char *can_mio_mux_parents[NUM_MIO_PINS];
231 	const char *dummy_nm = "dummy_name";
232 
233 	pr_info("Zynq clock init\n");
234 
235 	/* get clock output names from DT */
236 	for (i = 0; i < clk_max; i++) {
237 		if (of_property_read_string_index(np, "clock-output-names",
238 				  i, &clk_output_name[i])) {
239 			pr_err("%s: clock output name not in DT\n", __func__);
240 			BUG();
241 		}
242 	}
243 	cpu_parents[0] = clk_output_name[armpll];
244 	cpu_parents[1] = clk_output_name[armpll];
245 	cpu_parents[2] = clk_output_name[ddrpll];
246 	cpu_parents[3] = clk_output_name[iopll];
247 	periph_parents[0] = clk_output_name[iopll];
248 	periph_parents[1] = clk_output_name[iopll];
249 	periph_parents[2] = clk_output_name[armpll];
250 	periph_parents[3] = clk_output_name[ddrpll];
251 
252 	of_property_read_u32(np, "fclk-enable", &fclk_enable);
253 
254 	/* ps_clk */
255 	ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
256 	if (ret) {
257 		pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
258 		tmp = 33333333;
259 	}
260 	ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
261 			tmp);
262 
263 	/* PLLs */
264 	clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
265 			SLCR_PLL_STATUS, 0, &armpll_lock);
266 	clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
267 			armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
268 			SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
269 
270 	clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
271 			SLCR_PLL_STATUS, 1, &ddrpll_lock);
272 	clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
273 			ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
274 			SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
275 
276 	clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
277 			SLCR_PLL_STATUS, 2, &iopll_lock);
278 	clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
279 			iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
280 			SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
281 
282 	/* CPU clocks */
283 	tmp = clk_readl(SLCR_621_TRUE) & 1;
284 	clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
285 			CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
286 			&armclk_lock);
287 	clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
288 			SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
289 			CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
290 
291 	clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
292 			"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
293 			SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
294 
295 	clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
296 			1, 2);
297 	clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
298 			"cpu_3or2x_div", CLK_IGNORE_UNUSED,
299 			SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
300 
301 	clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
302 			2 + tmp);
303 	clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
304 			"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
305 			26, 0, &armclk_lock);
306 	clk_prepare_enable(clks[cpu_2x]);
307 
308 	clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
309 			4 + 2 * tmp);
310 	clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
311 			"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
312 			0, &armclk_lock);
313 
314 	/* Timers */
315 	swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
316 	for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
317 		int idx = of_property_match_string(np, "clock-names",
318 				swdt_ext_clk_input_names[i]);
319 		if (idx >= 0)
320 			swdt_ext_clk_mux_parents[i + 1] =
321 				of_clk_get_parent_name(np, idx);
322 		else
323 			swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
324 	}
325 	clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
326 			swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
327 			CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
328 			&swdtclk_lock);
329 
330 	/* DDR clocks */
331 	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
332 			SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
333 			CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
334 	clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
335 			"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
336 	clk_prepare_enable(clks[ddr2x]);
337 	clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
338 			SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
339 			CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
340 	clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
341 			"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
342 	clk_prepare_enable(clks[ddr3x]);
343 
344 	clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
345 			SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
346 			CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
347 	clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
348 			CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
349 			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
350 			&dciclk_lock);
351 	clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
352 			CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
353 			&dciclk_lock);
354 	clk_prepare_enable(clks[dci]);
355 
356 	/* Peripheral clocks */
357 	for (i = fclk0; i <= fclk3; i++) {
358 		int enable = !!(fclk_enable & BIT(i - fclk0));
359 		zynq_clk_register_fclk(i, clk_output_name[i],
360 				SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
361 				periph_parents, enable);
362 	}
363 
364 	zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
365 			SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
366 
367 	zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
368 			SLCR_SMC_CLK_CTRL, periph_parents, 0);
369 
370 	zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
371 			SLCR_PCAP_CLK_CTRL, periph_parents, 0);
372 
373 	zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
374 			clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
375 			periph_parents, 1);
376 
377 	zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
378 			clk_output_name[uart1], SLCR_UART_CLK_CTRL,
379 			periph_parents, 1);
380 
381 	zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
382 			clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
383 			periph_parents, 1);
384 
385 	for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
386 		int idx = of_property_match_string(np, "clock-names",
387 				gem0_emio_input_names[i]);
388 		if (idx >= 0)
389 			gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
390 					idx);
391 	}
392 	clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
393 			CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
394 			&gem0clk_lock);
395 	clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
396 			SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
397 			CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
398 	clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
399 			CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
400 			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
401 			&gem0clk_lock);
402 	clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
403 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
404 			SLCR_GEM0_CLK_CTRL, 6, 1, 0,
405 			&gem0clk_lock);
406 	clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
407 			"gem0_emio_mux", CLK_SET_RATE_PARENT,
408 			SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
409 
410 	for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
411 		int idx = of_property_match_string(np, "clock-names",
412 				gem1_emio_input_names[i]);
413 		if (idx >= 0)
414 			gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
415 					idx);
416 	}
417 	clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
418 			CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
419 			&gem1clk_lock);
420 	clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
421 			SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
422 			CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
423 	clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
424 			CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
425 			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
426 			&gem1clk_lock);
427 	clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
428 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
429 			SLCR_GEM1_CLK_CTRL, 6, 1, 0,
430 			&gem1clk_lock);
431 	clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
432 			"gem1_emio_mux", CLK_SET_RATE_PARENT,
433 			SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
434 
435 	tmp = strlen("mio_clk_00x");
436 	clk_name = kmalloc(tmp, GFP_KERNEL);
437 	for (i = 0; i < NUM_MIO_PINS; i++) {
438 		int idx;
439 
440 		snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
441 		idx = of_property_match_string(np, "clock-names", clk_name);
442 		if (idx >= 0)
443 			can_mio_mux_parents[i] = of_clk_get_parent_name(np,
444 						idx);
445 		else
446 			can_mio_mux_parents[i] = dummy_nm;
447 	}
448 	kfree(clk_name);
449 	clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
450 			CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
451 			&canclk_lock);
452 	clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
453 			SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
454 			CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
455 	clk = clk_register_divider(NULL, "can_div1", "can_div0",
456 			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
457 			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
458 			&canclk_lock);
459 	clk = clk_register_gate(NULL, "can0_gate", "can_div1",
460 			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
461 			&canclk_lock);
462 	clk = clk_register_gate(NULL, "can1_gate", "can_div1",
463 			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
464 			&canclk_lock);
465 	clk = clk_register_mux(NULL, "can0_mio_mux",
466 			can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
467 			CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
468 			&canmioclk_lock);
469 	clk = clk_register_mux(NULL, "can1_mio_mux",
470 			can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
471 			CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
472 			0, &canmioclk_lock);
473 	clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
474 			can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
475 			CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
476 			&canmioclk_lock);
477 	clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
478 			can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
479 			CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
480 			0, &canmioclk_lock);
481 
482 	for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
483 		int idx = of_property_match_string(np, "clock-names",
484 				dbgtrc_emio_input_names[i]);
485 		if (idx >= 0)
486 			dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
487 					idx);
488 	}
489 	clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
490 			CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
491 			&dbgclk_lock);
492 	clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
493 			SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
494 			CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
495 	clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
496 			CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
497 			&dbgclk_lock);
498 	clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
499 			"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
500 			0, 0, &dbgclk_lock);
501 	clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
502 			clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
503 			&dbgclk_lock);
504 
505 	/* leave debug clocks in the state the bootloader set them up to */
506 	tmp = clk_readl(SLCR_DBG_CLK_CTRL);
507 	if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
508 		if (clk_prepare_enable(clks[dbg_trc]))
509 			pr_warn("%s: trace clk enable failed\n", __func__);
510 	if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
511 		if (clk_prepare_enable(clks[dbg_apb]))
512 			pr_warn("%s: debug APB clk enable failed\n", __func__);
513 
514 	/* One gated clock for all APER clocks. */
515 	clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
516 			clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
517 			&aperclk_lock);
518 	clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
519 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
520 			&aperclk_lock);
521 	clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
522 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
523 			&aperclk_lock);
524 	clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
525 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
526 			&aperclk_lock);
527 	clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
528 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
529 			&aperclk_lock);
530 	clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
531 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
532 			&aperclk_lock);
533 	clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
534 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
535 			&aperclk_lock);
536 	clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
537 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
538 			&aperclk_lock);
539 	clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
540 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
541 			&aperclk_lock);
542 	clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
543 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
544 			&aperclk_lock);
545 	clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
546 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
547 			&aperclk_lock);
548 	clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
549 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
550 			&aperclk_lock);
551 	clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
552 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
553 			&aperclk_lock);
554 	clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
555 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
556 			&aperclk_lock);
557 	clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
558 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
559 			&aperclk_lock);
560 	clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
561 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
562 			&aperclk_lock);
563 	clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
564 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
565 			&aperclk_lock);
566 	clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
567 			clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
568 			&aperclk_lock);
569 
570 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
571 		if (IS_ERR(clks[i])) {
572 			pr_err("Zynq clk %d: register failed with %ld\n",
573 			       i, PTR_ERR(clks[i]));
574 			BUG();
575 		}
576 	}
577 
578 	clk_data.clks = clks;
579 	clk_data.clk_num = ARRAY_SIZE(clks);
580 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
581 }
582 
583 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
584 
585 void __init zynq_clock_init(void)
586 {
587 	struct device_node *np;
588 	struct device_node *slcr;
589 	struct resource res;
590 
591 	np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
592 	if (!np) {
593 		pr_err("%s: clkc node not found\n", __func__);
594 		goto np_err;
595 	}
596 
597 	if (of_address_to_resource(np, 0, &res)) {
598 		pr_err("%s: failed to get resource\n", np->name);
599 		goto np_err;
600 	}
601 
602 	slcr = of_get_parent(np);
603 
604 	if (slcr->data) {
605 		zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
606 	} else {
607 		pr_err("%s: Unable to get I/O memory\n", np->name);
608 		of_node_put(slcr);
609 		goto np_err;
610 	}
611 
612 	pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
613 
614 	of_node_put(slcr);
615 	of_node_put(np);
616 
617 	return;
618 
619 np_err:
620 	of_node_put(np);
621 	BUG();
622 }
623