1 /* 2 * Zynq clock controller 3 * 4 * Copyright (C) 2012 - 2013 Xilinx 5 * 6 * Sören Brinkmann <soren.brinkmann@xilinx.com> 7 * 8 * This program is free software: you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License v2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/clk/zynq.h> 22 #include <linux/clk-provider.h> 23 #include <linux/of.h> 24 #include <linux/slab.h> 25 #include <linux/string.h> 26 #include <linux/io.h> 27 28 static void __iomem *zynq_slcr_base_priv; 29 30 #define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) 31 #define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) 32 #define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) 33 #define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) 34 #define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) 35 #define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) 36 #define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) 37 #define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) 38 #define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) 39 #define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) 40 #define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) 41 #define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) 42 #define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) 43 #define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) 44 #define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) 45 #define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) 46 #define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) 47 #define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) 48 #define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) 49 #define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) 50 #define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) 51 #define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) 52 53 #define NUM_MIO_PINS 54 54 55 enum zynq_clk { 56 armpll, ddrpll, iopll, 57 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 58 ddr2x, ddr3x, dci, 59 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, 60 sdio0, sdio1, uart0, uart1, spi0, spi1, dma, 61 usb0_aper, usb1_aper, gem0_aper, gem1_aper, 62 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, 63 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, 64 smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; 65 66 static struct clk *ps_clk; 67 static struct clk *clks[clk_max]; 68 static struct clk_onecell_data clk_data; 69 70 static DEFINE_SPINLOCK(armpll_lock); 71 static DEFINE_SPINLOCK(ddrpll_lock); 72 static DEFINE_SPINLOCK(iopll_lock); 73 static DEFINE_SPINLOCK(armclk_lock); 74 static DEFINE_SPINLOCK(ddrclk_lock); 75 static DEFINE_SPINLOCK(dciclk_lock); 76 static DEFINE_SPINLOCK(gem0clk_lock); 77 static DEFINE_SPINLOCK(gem1clk_lock); 78 static DEFINE_SPINLOCK(canclk_lock); 79 static DEFINE_SPINLOCK(canmioclk_lock); 80 static DEFINE_SPINLOCK(dbgclk_lock); 81 static DEFINE_SPINLOCK(aperclk_lock); 82 83 static const char dummy_nm[] __initconst = "dummy_name"; 84 85 static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; 86 static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; 87 static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; 88 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm}; 89 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm}; 90 static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", 91 "can0_mio_mux"}; 92 static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", 93 "can1_mio_mux"}; 94 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", 95 dummy_nm}; 96 97 static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; 98 static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; 99 static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; 100 static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; 101 102 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 103 const char *clk_name, void __iomem *fclk_ctrl_reg, 104 const char **parents) 105 { 106 struct clk *clk; 107 char *mux_name; 108 char *div0_name; 109 char *div1_name; 110 spinlock_t *fclk_lock; 111 spinlock_t *fclk_gate_lock; 112 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; 113 114 fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); 115 if (!fclk_lock) 116 goto err; 117 fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); 118 if (!fclk_gate_lock) 119 goto err; 120 spin_lock_init(fclk_lock); 121 spin_lock_init(fclk_gate_lock); 122 123 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); 124 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 125 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 126 127 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 128 fclk_ctrl_reg, 4, 2, 0, fclk_lock); 129 130 clk = clk_register_divider(NULL, div0_name, mux_name, 131 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 132 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); 133 134 clk = clk_register_divider(NULL, div1_name, div0_name, 135 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, 136 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 137 fclk_lock); 138 139 clks[fclk] = clk_register_gate(NULL, clk_name, 140 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 141 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 142 kfree(mux_name); 143 kfree(div0_name); 144 kfree(div1_name); 145 146 return; 147 148 err: 149 clks[fclk] = ERR_PTR(-ENOMEM); 150 } 151 152 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, 153 enum zynq_clk clk1, const char *clk_name0, 154 const char *clk_name1, void __iomem *clk_ctrl, 155 const char **parents, unsigned int two_gates) 156 { 157 struct clk *clk; 158 char *mux_name; 159 char *div_name; 160 spinlock_t *lock; 161 162 lock = kmalloc(sizeof(*lock), GFP_KERNEL); 163 if (!lock) 164 goto err; 165 spin_lock_init(lock); 166 167 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 168 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 169 170 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 171 clk_ctrl, 4, 2, 0, lock); 172 173 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 174 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 175 176 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, 177 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); 178 if (two_gates) 179 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, 180 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); 181 182 kfree(mux_name); 183 kfree(div_name); 184 185 return; 186 187 err: 188 clks[clk0] = ERR_PTR(-ENOMEM); 189 if (two_gates) 190 clks[clk1] = ERR_PTR(-ENOMEM); 191 } 192 193 static void __init zynq_clk_setup(struct device_node *np) 194 { 195 int i; 196 u32 tmp; 197 int ret; 198 struct clk *clk; 199 char *clk_name; 200 const char *clk_output_name[clk_max]; 201 const char *cpu_parents[4]; 202 const char *periph_parents[4]; 203 const char *swdt_ext_clk_mux_parents[2]; 204 const char *can_mio_mux_parents[NUM_MIO_PINS]; 205 206 pr_info("Zynq clock init\n"); 207 208 /* get clock output names from DT */ 209 for (i = 0; i < clk_max; i++) { 210 if (of_property_read_string_index(np, "clock-output-names", 211 i, &clk_output_name[i])) { 212 pr_err("%s: clock output name not in DT\n", __func__); 213 BUG(); 214 } 215 } 216 cpu_parents[0] = clk_output_name[armpll]; 217 cpu_parents[1] = clk_output_name[armpll]; 218 cpu_parents[2] = clk_output_name[ddrpll]; 219 cpu_parents[3] = clk_output_name[iopll]; 220 periph_parents[0] = clk_output_name[iopll]; 221 periph_parents[1] = clk_output_name[iopll]; 222 periph_parents[2] = clk_output_name[armpll]; 223 periph_parents[3] = clk_output_name[ddrpll]; 224 225 /* ps_clk */ 226 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 227 if (ret) { 228 pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); 229 tmp = 33333333; 230 } 231 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, 232 tmp); 233 234 /* PLLs */ 235 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 236 SLCR_PLL_STATUS, 0, &armpll_lock); 237 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 238 armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0, 239 &armpll_lock); 240 241 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 242 SLCR_PLL_STATUS, 1, &ddrpll_lock); 243 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 244 ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0, 245 &ddrpll_lock); 246 247 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 248 SLCR_PLL_STATUS, 2, &iopll_lock); 249 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 250 iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0, 251 &iopll_lock); 252 253 /* CPU clocks */ 254 tmp = readl(SLCR_621_TRUE) & 1; 255 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0, 256 SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); 257 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 258 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 259 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 260 261 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], 262 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 263 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); 264 265 clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 266 1, 2); 267 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], 268 "cpu_3or2x_div", CLK_IGNORE_UNUSED, 269 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); 270 271 clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 272 2 + tmp); 273 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 274 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 275 26, 0, &armclk_lock); 276 277 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 278 4 + 2 * tmp); 279 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], 280 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 281 0, &armclk_lock); 282 283 /* Timers */ 284 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; 285 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { 286 int idx = of_property_match_string(np, "clock-names", 287 swdt_ext_clk_input_names[i]); 288 if (idx >= 0) 289 swdt_ext_clk_mux_parents[i + 1] = 290 of_clk_get_parent_name(np, idx); 291 else 292 swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 293 } 294 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 295 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, 296 SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock); 297 298 /* DDR clocks */ 299 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 300 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | 301 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 302 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], 303 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); 304 clk_prepare_enable(clks[ddr2x]); 305 clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, 306 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | 307 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 308 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], 309 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); 310 clk_prepare_enable(clks[ddr3x]); 311 312 clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, 313 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 314 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); 315 clk = clk_register_divider(NULL, "dci_div1", "dci_div0", 316 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, 317 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 318 &dciclk_lock); 319 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", 320 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, 321 &dciclk_lock); 322 clk_prepare_enable(clks[dci]); 323 324 /* Peripheral clocks */ 325 for (i = fclk0; i <= fclk3; i++) 326 zynq_clk_register_fclk(i, clk_output_name[i], 327 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 328 periph_parents); 329 330 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, 331 SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 332 333 zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, 334 SLCR_SMC_CLK_CTRL, periph_parents, 0); 335 336 zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, 337 SLCR_PCAP_CLK_CTRL, periph_parents, 0); 338 339 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], 340 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, 341 periph_parents, 1); 342 343 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], 344 clk_output_name[uart1], SLCR_UART_CLK_CTRL, 345 periph_parents, 1); 346 347 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], 348 clk_output_name[spi1], SLCR_SPI_CLK_CTRL, 349 periph_parents, 1); 350 351 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { 352 int idx = of_property_match_string(np, "clock-names", 353 gem0_emio_input_names[i]); 354 if (idx >= 0) 355 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 356 idx); 357 } 358 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0, 359 SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); 360 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 361 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 362 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 363 clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", 364 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 365 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 366 &gem0clk_lock); 367 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0, 368 SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock); 369 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 370 "gem0_emio_mux", CLK_SET_RATE_PARENT, 371 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 372 373 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { 374 int idx = of_property_match_string(np, "clock-names", 375 gem1_emio_input_names[i]); 376 if (idx >= 0) 377 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 378 idx); 379 } 380 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0, 381 SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); 382 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 383 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 384 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 385 clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", 386 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 387 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 388 &gem1clk_lock); 389 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0, 390 SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock); 391 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 392 "gem1_emio_mux", CLK_SET_RATE_PARENT, 393 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 394 395 tmp = strlen("mio_clk_00x"); 396 clk_name = kmalloc(tmp, GFP_KERNEL); 397 for (i = 0; i < NUM_MIO_PINS; i++) { 398 int idx; 399 400 snprintf(clk_name, tmp, "mio_clk_%2.2d", i); 401 idx = of_property_match_string(np, "clock-names", clk_name); 402 if (idx >= 0) 403 can_mio_mux_parents[i] = of_clk_get_parent_name(np, 404 idx); 405 else 406 can_mio_mux_parents[i] = dummy_nm; 407 } 408 kfree(clk_name); 409 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0, 410 SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); 411 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 412 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 413 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 414 clk = clk_register_divider(NULL, "can_div1", "can_div0", 415 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, 416 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 417 &canclk_lock); 418 clk = clk_register_gate(NULL, "can0_gate", "can_div1", 419 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, 420 &canclk_lock); 421 clk = clk_register_gate(NULL, "can1_gate", "can_div1", 422 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 423 &canclk_lock); 424 clk = clk_register_mux(NULL, "can0_mio_mux", 425 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 426 SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); 427 clk = clk_register_mux(NULL, "can1_mio_mux", 428 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 429 SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); 430 clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 431 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 432 SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); 433 clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 434 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 435 SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); 436 437 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 438 int idx = of_property_match_string(np, "clock-names", 439 dbgtrc_emio_input_names[i]); 440 if (idx >= 0) 441 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 442 idx); 443 } 444 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0, 445 SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); 446 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 447 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 448 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 449 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0, 450 SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); 451 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 452 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 453 0, 0, &dbgclk_lock); 454 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], 455 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 456 &dbgclk_lock); 457 458 /* One gated clock for all APER clocks. */ 459 clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 460 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 461 &aperclk_lock); 462 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], 463 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, 464 &aperclk_lock); 465 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], 466 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, 467 &aperclk_lock); 468 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], 469 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, 470 &aperclk_lock); 471 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], 472 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, 473 &aperclk_lock); 474 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], 475 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, 476 &aperclk_lock); 477 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], 478 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, 479 &aperclk_lock); 480 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], 481 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, 482 &aperclk_lock); 483 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], 484 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, 485 &aperclk_lock); 486 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], 487 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, 488 &aperclk_lock); 489 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], 490 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, 491 &aperclk_lock); 492 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], 493 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, 494 &aperclk_lock); 495 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], 496 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, 497 &aperclk_lock); 498 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], 499 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, 500 &aperclk_lock); 501 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], 502 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, 503 &aperclk_lock); 504 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], 505 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, 506 &aperclk_lock); 507 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], 508 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, 509 &aperclk_lock); 510 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], 511 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, 512 &aperclk_lock); 513 514 for (i = 0; i < ARRAY_SIZE(clks); i++) { 515 if (IS_ERR(clks[i])) { 516 pr_err("Zynq clk %d: register failed with %ld\n", 517 i, PTR_ERR(clks[i])); 518 BUG(); 519 } 520 } 521 522 clk_data.clks = clks; 523 clk_data.clk_num = ARRAY_SIZE(clks); 524 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 525 } 526 527 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); 528 529 void __init zynq_clock_init(void __iomem *slcr_base) 530 { 531 zynq_slcr_base_priv = slcr_base; 532 of_clk_init(NULL); 533 } 534