1dc1a8bc1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20ee52b15SSoren Brinkmann /* 30ee52b15SSoren Brinkmann * Zynq clock controller 40ee52b15SSoren Brinkmann * 50ee52b15SSoren Brinkmann * Copyright (C) 2012 - 2013 Xilinx 60ee52b15SSoren Brinkmann * 70ee52b15SSoren Brinkmann * Sören Brinkmann <soren.brinkmann@xilinx.com> 80ee52b15SSoren Brinkmann */ 90ee52b15SSoren Brinkmann 100ee52b15SSoren Brinkmann #include <linux/clk/zynq.h> 115402494fSStephen Boyd #include <linux/clk.h> 120ee52b15SSoren Brinkmann #include <linux/clk-provider.h> 130ee52b15SSoren Brinkmann #include <linux/of.h> 14b0504e39SMichal Simek #include <linux/of_address.h> 150ee52b15SSoren Brinkmann #include <linux/slab.h> 160ee52b15SSoren Brinkmann #include <linux/string.h> 170ee52b15SSoren Brinkmann #include <linux/io.h> 180ee52b15SSoren Brinkmann 19b0504e39SMichal Simek static void __iomem *zynq_clkc_base; 200ee52b15SSoren Brinkmann 21b0504e39SMichal Simek #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) 22b0504e39SMichal Simek #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) 23b0504e39SMichal Simek #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) 24b0504e39SMichal Simek #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) 25b0504e39SMichal Simek #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) 26b0504e39SMichal Simek #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) 27b0504e39SMichal Simek #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) 28b0504e39SMichal Simek #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) 29b0504e39SMichal Simek #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) 30b0504e39SMichal Simek #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) 31b0504e39SMichal Simek #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) 32b0504e39SMichal Simek #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) 33b0504e39SMichal Simek #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) 34b0504e39SMichal Simek #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) 35b0504e39SMichal Simek #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) 36b0504e39SMichal Simek #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) 37b0504e39SMichal Simek #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) 38b0504e39SMichal Simek #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) 39b0504e39SMichal Simek #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) 40b0504e39SMichal Simek #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) 41b0504e39SMichal Simek #define SLCR_621_TRUE (zynq_clkc_base + 0xc4) 42b0504e39SMichal Simek #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) 430ee52b15SSoren Brinkmann 440ee52b15SSoren Brinkmann #define NUM_MIO_PINS 54 450ee52b15SSoren Brinkmann 469268beb5SSoren Brinkmann #define DBG_CLK_CTRL_CLKACT_TRC BIT(0) 479268beb5SSoren Brinkmann #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) 489268beb5SSoren Brinkmann 490ee52b15SSoren Brinkmann enum zynq_clk { 500ee52b15SSoren Brinkmann armpll, ddrpll, iopll, 510ee52b15SSoren Brinkmann cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 520ee52b15SSoren Brinkmann ddr2x, ddr3x, dci, 530ee52b15SSoren Brinkmann lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, 540ee52b15SSoren Brinkmann sdio0, sdio1, uart0, uart1, spi0, spi1, dma, 550ee52b15SSoren Brinkmann usb0_aper, usb1_aper, gem0_aper, gem1_aper, 560ee52b15SSoren Brinkmann sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, 570ee52b15SSoren Brinkmann i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, 580ee52b15SSoren Brinkmann smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; 590ee52b15SSoren Brinkmann 600ee52b15SSoren Brinkmann static struct clk *ps_clk; 610ee52b15SSoren Brinkmann static struct clk *clks[clk_max]; 620ee52b15SSoren Brinkmann static struct clk_onecell_data clk_data; 630ee52b15SSoren Brinkmann 640ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(armpll_lock); 650ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(ddrpll_lock); 660ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(iopll_lock); 670ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(armclk_lock); 68252957ccSSoren Brinkmann static DEFINE_SPINLOCK(swdtclk_lock); 690ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(ddrclk_lock); 700ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(dciclk_lock); 710ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(gem0clk_lock); 720ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(gem1clk_lock); 730ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(canclk_lock); 740ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(canmioclk_lock); 750ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(dbgclk_lock); 760ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(aperclk_lock); 770ee52b15SSoren Brinkmann 784a1caed3SUwe Kleine-König static const char *const armpll_parents[] __initconst = {"armpll_int", 794a1caed3SUwe Kleine-König "ps_clk"}; 804a1caed3SUwe Kleine-König static const char *const ddrpll_parents[] __initconst = {"ddrpll_int", 814a1caed3SUwe Kleine-König "ps_clk"}; 824a1caed3SUwe Kleine-König static const char *const iopll_parents[] __initconst = {"iopll_int", 834a1caed3SUwe Kleine-König "ps_clk"}; 84692d8328SUwe Kleine-König static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"}; 85692d8328SUwe Kleine-König static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"}; 864a1caed3SUwe Kleine-König static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate", 870ee52b15SSoren Brinkmann "can0_mio_mux"}; 884a1caed3SUwe Kleine-König static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate", 890ee52b15SSoren Brinkmann "can1_mio_mux"}; 90692d8328SUwe Kleine-König static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", 918eaf5034SSoren Brinkmann "dummy_name"}; 920ee52b15SSoren Brinkmann 934a1caed3SUwe Kleine-König static const char *const dbgtrc_emio_input_names[] __initconst = { 944a1caed3SUwe Kleine-König "trace_emio_clk"}; 954a1caed3SUwe Kleine-König static const char *const gem0_emio_input_names[] __initconst = { 964a1caed3SUwe Kleine-König "gem0_emio_clk"}; 974a1caed3SUwe Kleine-König static const char *const gem1_emio_input_names[] __initconst = { 984a1caed3SUwe Kleine-König "gem1_emio_clk"}; 994a1caed3SUwe Kleine-König static const char *const swdt_ext_clk_input_names[] __initconst = { 1004a1caed3SUwe Kleine-König "swdt_ext_clk"}; 1010ee52b15SSoren Brinkmann 1020ee52b15SSoren Brinkmann static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 1030ee52b15SSoren Brinkmann const char *clk_name, void __iomem *fclk_ctrl_reg, 104ba52f8a9SSoren Brinkmann const char **parents, int enable) 1050ee52b15SSoren Brinkmann { 106ba52f8a9SSoren Brinkmann u32 enable_reg; 1070ee52b15SSoren Brinkmann char *mux_name; 1080ee52b15SSoren Brinkmann char *div0_name; 1090ee52b15SSoren Brinkmann char *div1_name; 1100ee52b15SSoren Brinkmann spinlock_t *fclk_lock; 1110ee52b15SSoren Brinkmann spinlock_t *fclk_gate_lock; 1120ee52b15SSoren Brinkmann void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; 1130ee52b15SSoren Brinkmann 1140ee52b15SSoren Brinkmann fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); 1150ee52b15SSoren Brinkmann if (!fclk_lock) 1160ee52b15SSoren Brinkmann goto err; 1170ee52b15SSoren Brinkmann fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); 1180ee52b15SSoren Brinkmann if (!fclk_gate_lock) 119f8fe36f6SFelipe Pena goto err_fclk_gate_lock; 1200ee52b15SSoren Brinkmann spin_lock_init(fclk_lock); 1210ee52b15SSoren Brinkmann spin_lock_init(fclk_gate_lock); 1220ee52b15SSoren Brinkmann 1230ee52b15SSoren Brinkmann mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); 124f8fe36f6SFelipe Pena if (!mux_name) 125f8fe36f6SFelipe Pena goto err_mux_name; 1260ee52b15SSoren Brinkmann div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 127f8fe36f6SFelipe Pena if (!div0_name) 128f8fe36f6SFelipe Pena goto err_div0_name; 1290ee52b15SSoren Brinkmann div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 130f8fe36f6SFelipe Pena if (!div1_name) 131f8fe36f6SFelipe Pena goto err_div1_name; 1320ee52b15SSoren Brinkmann 133bf2244baSLee Jones clk_register_mux(NULL, mux_name, parents, 4, 134819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, 135819c1de3SJames Hogan fclk_lock); 1360ee52b15SSoren Brinkmann 137bf2244baSLee Jones clk_register_divider(NULL, div0_name, mux_name, 1380ee52b15SSoren Brinkmann 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 1390ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, fclk_lock); 1400ee52b15SSoren Brinkmann 141bf2244baSLee Jones clk_register_divider(NULL, div1_name, div0_name, 1420ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, 1430ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 1440ee52b15SSoren Brinkmann fclk_lock); 1450ee52b15SSoren Brinkmann 1460ee52b15SSoren Brinkmann clks[fclk] = clk_register_gate(NULL, clk_name, 1470ee52b15SSoren Brinkmann div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 1480ee52b15SSoren Brinkmann 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 1495834fd75SJonas Gorski enable_reg = readl(fclk_gate_reg) & 1; 150ba52f8a9SSoren Brinkmann if (enable && !enable_reg) { 151ba52f8a9SSoren Brinkmann if (clk_prepare_enable(clks[fclk])) 152ba52f8a9SSoren Brinkmann pr_warn("%s: FCLK%u enable failed\n", __func__, 153ba52f8a9SSoren Brinkmann fclk - fclk0); 154ba52f8a9SSoren Brinkmann } 1550ee52b15SSoren Brinkmann kfree(mux_name); 1560ee52b15SSoren Brinkmann kfree(div0_name); 1570ee52b15SSoren Brinkmann kfree(div1_name); 1580ee52b15SSoren Brinkmann 1590ee52b15SSoren Brinkmann return; 1600ee52b15SSoren Brinkmann 161f8fe36f6SFelipe Pena err_div1_name: 162f8fe36f6SFelipe Pena kfree(div0_name); 163f8fe36f6SFelipe Pena err_div0_name: 164f8fe36f6SFelipe Pena kfree(mux_name); 165f8fe36f6SFelipe Pena err_mux_name: 166f8fe36f6SFelipe Pena kfree(fclk_gate_lock); 167f8fe36f6SFelipe Pena err_fclk_gate_lock: 168f8fe36f6SFelipe Pena kfree(fclk_lock); 1690ee52b15SSoren Brinkmann err: 1700ee52b15SSoren Brinkmann clks[fclk] = ERR_PTR(-ENOMEM); 1710ee52b15SSoren Brinkmann } 1720ee52b15SSoren Brinkmann 1730ee52b15SSoren Brinkmann static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, 1740ee52b15SSoren Brinkmann enum zynq_clk clk1, const char *clk_name0, 1750ee52b15SSoren Brinkmann const char *clk_name1, void __iomem *clk_ctrl, 1760ee52b15SSoren Brinkmann const char **parents, unsigned int two_gates) 1770ee52b15SSoren Brinkmann { 1780ee52b15SSoren Brinkmann char *mux_name; 1790ee52b15SSoren Brinkmann char *div_name; 1800ee52b15SSoren Brinkmann spinlock_t *lock; 1810ee52b15SSoren Brinkmann 1820ee52b15SSoren Brinkmann lock = kmalloc(sizeof(*lock), GFP_KERNEL); 1830ee52b15SSoren Brinkmann if (!lock) 1840ee52b15SSoren Brinkmann goto err; 1850ee52b15SSoren Brinkmann spin_lock_init(lock); 1860ee52b15SSoren Brinkmann 1870ee52b15SSoren Brinkmann mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 1880ee52b15SSoren Brinkmann div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 1890ee52b15SSoren Brinkmann 190bf2244baSLee Jones clk_register_mux(NULL, mux_name, parents, 4, 191819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); 1920ee52b15SSoren Brinkmann 193bf2244baSLee Jones clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 1940ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 1950ee52b15SSoren Brinkmann 1960ee52b15SSoren Brinkmann clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, 1970ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); 1980ee52b15SSoren Brinkmann if (two_gates) 1990ee52b15SSoren Brinkmann clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, 2000ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); 2010ee52b15SSoren Brinkmann 2020ee52b15SSoren Brinkmann kfree(mux_name); 2030ee52b15SSoren Brinkmann kfree(div_name); 2040ee52b15SSoren Brinkmann 2050ee52b15SSoren Brinkmann return; 2060ee52b15SSoren Brinkmann 2070ee52b15SSoren Brinkmann err: 2080ee52b15SSoren Brinkmann clks[clk0] = ERR_PTR(-ENOMEM); 2090ee52b15SSoren Brinkmann if (two_gates) 2100ee52b15SSoren Brinkmann clks[clk1] = ERR_PTR(-ENOMEM); 2110ee52b15SSoren Brinkmann } 2120ee52b15SSoren Brinkmann 2130ee52b15SSoren Brinkmann static void __init zynq_clk_setup(struct device_node *np) 2140ee52b15SSoren Brinkmann { 2150ee52b15SSoren Brinkmann int i; 2160ee52b15SSoren Brinkmann u32 tmp; 2170ee52b15SSoren Brinkmann int ret; 2180ee52b15SSoren Brinkmann char *clk_name; 219ba52f8a9SSoren Brinkmann unsigned int fclk_enable = 0; 2200ee52b15SSoren Brinkmann const char *clk_output_name[clk_max]; 2210ee52b15SSoren Brinkmann const char *cpu_parents[4]; 2220ee52b15SSoren Brinkmann const char *periph_parents[4]; 2230ee52b15SSoren Brinkmann const char *swdt_ext_clk_mux_parents[2]; 2240ee52b15SSoren Brinkmann const char *can_mio_mux_parents[NUM_MIO_PINS]; 2258eaf5034SSoren Brinkmann const char *dummy_nm = "dummy_name"; 2260ee52b15SSoren Brinkmann 2270ee52b15SSoren Brinkmann pr_info("Zynq clock init\n"); 2280ee52b15SSoren Brinkmann 2290ee52b15SSoren Brinkmann /* get clock output names from DT */ 2300ee52b15SSoren Brinkmann for (i = 0; i < clk_max; i++) { 2310ee52b15SSoren Brinkmann if (of_property_read_string_index(np, "clock-output-names", 2320ee52b15SSoren Brinkmann i, &clk_output_name[i])) { 2330ee52b15SSoren Brinkmann pr_err("%s: clock output name not in DT\n", __func__); 2340ee52b15SSoren Brinkmann BUG(); 2350ee52b15SSoren Brinkmann } 2360ee52b15SSoren Brinkmann } 2370ee52b15SSoren Brinkmann cpu_parents[0] = clk_output_name[armpll]; 2380ee52b15SSoren Brinkmann cpu_parents[1] = clk_output_name[armpll]; 2390ee52b15SSoren Brinkmann cpu_parents[2] = clk_output_name[ddrpll]; 2400ee52b15SSoren Brinkmann cpu_parents[3] = clk_output_name[iopll]; 2410ee52b15SSoren Brinkmann periph_parents[0] = clk_output_name[iopll]; 2420ee52b15SSoren Brinkmann periph_parents[1] = clk_output_name[iopll]; 2430ee52b15SSoren Brinkmann periph_parents[2] = clk_output_name[armpll]; 2440ee52b15SSoren Brinkmann periph_parents[3] = clk_output_name[ddrpll]; 2450ee52b15SSoren Brinkmann 246ba52f8a9SSoren Brinkmann of_property_read_u32(np, "fclk-enable", &fclk_enable); 247ba52f8a9SSoren Brinkmann 2480ee52b15SSoren Brinkmann /* ps_clk */ 2490ee52b15SSoren Brinkmann ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 2500ee52b15SSoren Brinkmann if (ret) { 2510ee52b15SSoren Brinkmann pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); 2520ee52b15SSoren Brinkmann tmp = 33333333; 2530ee52b15SSoren Brinkmann } 2540b4d613aSStephen Boyd ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp); 2550ee52b15SSoren Brinkmann 2560ee52b15SSoren Brinkmann /* PLLs */ 257bf2244baSLee Jones clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 2580ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 0, &armpll_lock); 2590ee52b15SSoren Brinkmann clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 260819c1de3SJames Hogan armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 261819c1de3SJames Hogan SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); 2620ee52b15SSoren Brinkmann 263bf2244baSLee Jones clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 2640ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 1, &ddrpll_lock); 2650ee52b15SSoren Brinkmann clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 266819c1de3SJames Hogan ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 267819c1de3SJames Hogan SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); 2680ee52b15SSoren Brinkmann 269bf2244baSLee Jones clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 2700ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 2, &iopll_lock); 2710ee52b15SSoren Brinkmann clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 272819c1de3SJames Hogan iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, 273819c1de3SJames Hogan SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); 2740ee52b15SSoren Brinkmann 2750ee52b15SSoren Brinkmann /* CPU clocks */ 2765834fd75SJonas Gorski tmp = readl(SLCR_621_TRUE) & 1; 277bf2244baSLee Jones clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 278819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, 279819c1de3SJames Hogan &armclk_lock); 280bf2244baSLee Jones clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 2810ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 2820ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 2830ee52b15SSoren Brinkmann 2840ee52b15SSoren Brinkmann clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], 2850ee52b15SSoren Brinkmann "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2860ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); 2870ee52b15SSoren Brinkmann 288bf2244baSLee Jones clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 2890ee52b15SSoren Brinkmann 1, 2); 2900ee52b15SSoren Brinkmann clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], 2910ee52b15SSoren Brinkmann "cpu_3or2x_div", CLK_IGNORE_UNUSED, 2920ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); 2930ee52b15SSoren Brinkmann 294bf2244baSLee Jones clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 2950ee52b15SSoren Brinkmann 2 + tmp); 2960ee52b15SSoren Brinkmann clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 2970ee52b15SSoren Brinkmann "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 2980ee52b15SSoren Brinkmann 26, 0, &armclk_lock); 2993dccfecdSSoren Brinkmann clk_prepare_enable(clks[cpu_2x]); 3000ee52b15SSoren Brinkmann 301bf2244baSLee Jones clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 3020ee52b15SSoren Brinkmann 4 + 2 * tmp); 3030ee52b15SSoren Brinkmann clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], 3040ee52b15SSoren Brinkmann "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 3050ee52b15SSoren Brinkmann 0, &armclk_lock); 3060ee52b15SSoren Brinkmann 3070ee52b15SSoren Brinkmann /* Timers */ 3080ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; 3090ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { 3100ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 3110ee52b15SSoren Brinkmann swdt_ext_clk_input_names[i]); 3120ee52b15SSoren Brinkmann if (idx >= 0) 3130ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[i + 1] = 3140ee52b15SSoren Brinkmann of_clk_get_parent_name(np, idx); 3150ee52b15SSoren Brinkmann else 3160ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 3170ee52b15SSoren Brinkmann } 3180ee52b15SSoren Brinkmann clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 319819c1de3SJames Hogan swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | 320819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, 321bef4a0abSLinus Torvalds &swdtclk_lock); 3220ee52b15SSoren Brinkmann 3230ee52b15SSoren Brinkmann /* DDR clocks */ 324bf2244baSLee Jones clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 3250ee52b15SSoren Brinkmann SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | 3260ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 3270ee52b15SSoren Brinkmann clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], 3280ee52b15SSoren Brinkmann "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); 3290ee52b15SSoren Brinkmann clk_prepare_enable(clks[ddr2x]); 330bf2244baSLee Jones clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, 3310ee52b15SSoren Brinkmann SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | 3320ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 3330ee52b15SSoren Brinkmann clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], 3340ee52b15SSoren Brinkmann "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); 3350ee52b15SSoren Brinkmann clk_prepare_enable(clks[ddr3x]); 3360ee52b15SSoren Brinkmann 337bf2244baSLee Jones clk_register_divider(NULL, "dci_div0", "ddrpll", 0, 3380ee52b15SSoren Brinkmann SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 3390ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); 340bf2244baSLee Jones clk_register_divider(NULL, "dci_div1", "dci_div0", 3410ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, 3420ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 3430ee52b15SSoren Brinkmann &dciclk_lock); 3440ee52b15SSoren Brinkmann clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", 3450ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, 3460ee52b15SSoren Brinkmann &dciclk_lock); 3470ee52b15SSoren Brinkmann clk_prepare_enable(clks[dci]); 3480ee52b15SSoren Brinkmann 3490ee52b15SSoren Brinkmann /* Peripheral clocks */ 350ba52f8a9SSoren Brinkmann for (i = fclk0; i <= fclk3; i++) { 351ba52f8a9SSoren Brinkmann int enable = !!(fclk_enable & BIT(i - fclk0)); 352*d583804cSShubhrajyoti Datta 3530ee52b15SSoren Brinkmann zynq_clk_register_fclk(i, clk_output_name[i], 3540ee52b15SSoren Brinkmann SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 355ba52f8a9SSoren Brinkmann periph_parents, enable); 356ba52f8a9SSoren Brinkmann } 3570ee52b15SSoren Brinkmann 3580ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, 3590ee52b15SSoren Brinkmann SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 3600ee52b15SSoren Brinkmann 3610ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, 3620ee52b15SSoren Brinkmann SLCR_SMC_CLK_CTRL, periph_parents, 0); 3630ee52b15SSoren Brinkmann 3640ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, 3650ee52b15SSoren Brinkmann SLCR_PCAP_CLK_CTRL, periph_parents, 0); 3660ee52b15SSoren Brinkmann 3670ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], 3680ee52b15SSoren Brinkmann clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, 3690ee52b15SSoren Brinkmann periph_parents, 1); 3700ee52b15SSoren Brinkmann 3710ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], 3720ee52b15SSoren Brinkmann clk_output_name[uart1], SLCR_UART_CLK_CTRL, 3730ee52b15SSoren Brinkmann periph_parents, 1); 3740ee52b15SSoren Brinkmann 3750ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], 3760ee52b15SSoren Brinkmann clk_output_name[spi1], SLCR_SPI_CLK_CTRL, 3770ee52b15SSoren Brinkmann periph_parents, 1); 3780ee52b15SSoren Brinkmann 3790ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { 3800ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 3810ee52b15SSoren Brinkmann gem0_emio_input_names[i]); 3820ee52b15SSoren Brinkmann if (idx >= 0) 3830ee52b15SSoren Brinkmann gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 3840ee52b15SSoren Brinkmann idx); 3850ee52b15SSoren Brinkmann } 386bf2244baSLee Jones clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 387819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, 388819c1de3SJames Hogan &gem0clk_lock); 389bf2244baSLee Jones clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 3900ee52b15SSoren Brinkmann SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 3910ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 392bf2244baSLee Jones clk_register_divider(NULL, "gem0_div1", "gem0_div0", 3930ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 3940ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 3950ee52b15SSoren Brinkmann &gem0clk_lock); 396bf2244baSLee Jones clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 397bef4a0abSLinus Torvalds CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 398bef4a0abSLinus Torvalds SLCR_GEM0_CLK_CTRL, 6, 1, 0, 399765b7d4cSSoren Brinkmann &gem0clk_lock); 4000ee52b15SSoren Brinkmann clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 4010ee52b15SSoren Brinkmann "gem0_emio_mux", CLK_SET_RATE_PARENT, 4020ee52b15SSoren Brinkmann SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 4030ee52b15SSoren Brinkmann 4040ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { 4050ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 4060ee52b15SSoren Brinkmann gem1_emio_input_names[i]); 4070ee52b15SSoren Brinkmann if (idx >= 0) 4080ee52b15SSoren Brinkmann gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 4090ee52b15SSoren Brinkmann idx); 4100ee52b15SSoren Brinkmann } 411bf2244baSLee Jones clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 412819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, 413819c1de3SJames Hogan &gem1clk_lock); 414bf2244baSLee Jones clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 4150ee52b15SSoren Brinkmann SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4160ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 417bf2244baSLee Jones clk_register_divider(NULL, "gem1_div1", "gem1_div0", 4180ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 4190ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4200ee52b15SSoren Brinkmann &gem1clk_lock); 421bf2244baSLee Jones clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 422bef4a0abSLinus Torvalds CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 423bef4a0abSLinus Torvalds SLCR_GEM1_CLK_CTRL, 6, 1, 0, 424765b7d4cSSoren Brinkmann &gem1clk_lock); 4250ee52b15SSoren Brinkmann clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 4260ee52b15SSoren Brinkmann "gem1_emio_mux", CLK_SET_RATE_PARENT, 4270ee52b15SSoren Brinkmann SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 4280ee52b15SSoren Brinkmann 4290ee52b15SSoren Brinkmann tmp = strlen("mio_clk_00x"); 4300ee52b15SSoren Brinkmann clk_name = kmalloc(tmp, GFP_KERNEL); 4310ee52b15SSoren Brinkmann for (i = 0; i < NUM_MIO_PINS; i++) { 4320ee52b15SSoren Brinkmann int idx; 4330ee52b15SSoren Brinkmann 4340ee52b15SSoren Brinkmann snprintf(clk_name, tmp, "mio_clk_%2.2d", i); 4350ee52b15SSoren Brinkmann idx = of_property_match_string(np, "clock-names", clk_name); 4360ee52b15SSoren Brinkmann if (idx >= 0) 4370ee52b15SSoren Brinkmann can_mio_mux_parents[i] = of_clk_get_parent_name(np, 4380ee52b15SSoren Brinkmann idx); 4390ee52b15SSoren Brinkmann else 4400ee52b15SSoren Brinkmann can_mio_mux_parents[i] = dummy_nm; 4410ee52b15SSoren Brinkmann } 4420ee52b15SSoren Brinkmann kfree(clk_name); 443bf2244baSLee Jones clk_register_mux(NULL, "can_mux", periph_parents, 4, 444819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, 445819c1de3SJames Hogan &canclk_lock); 446bf2244baSLee Jones clk_register_divider(NULL, "can_div0", "can_mux", 0, 4470ee52b15SSoren Brinkmann SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4480ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 449bf2244baSLee Jones clk_register_divider(NULL, "can_div1", "can_div0", 4500ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, 4510ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4520ee52b15SSoren Brinkmann &canclk_lock); 453bf2244baSLee Jones clk_register_gate(NULL, "can0_gate", "can_div1", 4540ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, 4550ee52b15SSoren Brinkmann &canclk_lock); 456bf2244baSLee Jones clk_register_gate(NULL, "can1_gate", "can_div1", 4570ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 4580ee52b15SSoren Brinkmann &canclk_lock); 459bf2244baSLee Jones clk_register_mux(NULL, "can0_mio_mux", 460819c1de3SJames Hogan can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 461819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, 462819c1de3SJames Hogan &canmioclk_lock); 463bf2244baSLee Jones clk_register_mux(NULL, "can1_mio_mux", 464819c1de3SJames Hogan can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 465819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, 466819c1de3SJames Hogan 0, &canmioclk_lock); 4670ee52b15SSoren Brinkmann clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 468819c1de3SJames Hogan can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 469819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, 470819c1de3SJames Hogan &canmioclk_lock); 4710ee52b15SSoren Brinkmann clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 472819c1de3SJames Hogan can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 473819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, 474819c1de3SJames Hogan 0, &canmioclk_lock); 4750ee52b15SSoren Brinkmann 4760ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 4770ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 4780ee52b15SSoren Brinkmann dbgtrc_emio_input_names[i]); 4790ee52b15SSoren Brinkmann if (idx >= 0) 4800ee52b15SSoren Brinkmann dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 4810ee52b15SSoren Brinkmann idx); 4820ee52b15SSoren Brinkmann } 483bf2244baSLee Jones clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 484819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, 485819c1de3SJames Hogan &dbgclk_lock); 486bf2244baSLee Jones clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 4870ee52b15SSoren Brinkmann SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4880ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 489bf2244baSLee Jones clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 490819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, 491819c1de3SJames Hogan &dbgclk_lock); 4920ee52b15SSoren Brinkmann clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 4930ee52b15SSoren Brinkmann "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 4940ee52b15SSoren Brinkmann 0, 0, &dbgclk_lock); 4950ee52b15SSoren Brinkmann clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], 4960ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 4970ee52b15SSoren Brinkmann &dbgclk_lock); 4980ee52b15SSoren Brinkmann 4999268beb5SSoren Brinkmann /* leave debug clocks in the state the bootloader set them up to */ 5005834fd75SJonas Gorski tmp = readl(SLCR_DBG_CLK_CTRL); 5019268beb5SSoren Brinkmann if (tmp & DBG_CLK_CTRL_CLKACT_TRC) 5029268beb5SSoren Brinkmann if (clk_prepare_enable(clks[dbg_trc])) 5039268beb5SSoren Brinkmann pr_warn("%s: trace clk enable failed\n", __func__); 5049268beb5SSoren Brinkmann if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) 5059268beb5SSoren Brinkmann if (clk_prepare_enable(clks[dbg_apb])) 5069268beb5SSoren Brinkmann pr_warn("%s: debug APB clk enable failed\n", __func__); 5079268beb5SSoren Brinkmann 5080ee52b15SSoren Brinkmann /* One gated clock for all APER clocks. */ 5090ee52b15SSoren Brinkmann clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 5100ee52b15SSoren Brinkmann clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 5110ee52b15SSoren Brinkmann &aperclk_lock); 5120ee52b15SSoren Brinkmann clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], 5130ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, 5140ee52b15SSoren Brinkmann &aperclk_lock); 5150ee52b15SSoren Brinkmann clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], 5160ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, 5170ee52b15SSoren Brinkmann &aperclk_lock); 5180ee52b15SSoren Brinkmann clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], 5190ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, 5200ee52b15SSoren Brinkmann &aperclk_lock); 5210ee52b15SSoren Brinkmann clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], 5220ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, 5230ee52b15SSoren Brinkmann &aperclk_lock); 5240ee52b15SSoren Brinkmann clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], 5250ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, 5260ee52b15SSoren Brinkmann &aperclk_lock); 5270ee52b15SSoren Brinkmann clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], 5280ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, 5290ee52b15SSoren Brinkmann &aperclk_lock); 5300ee52b15SSoren Brinkmann clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], 5310ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, 5320ee52b15SSoren Brinkmann &aperclk_lock); 5330ee52b15SSoren Brinkmann clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], 5340ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, 5350ee52b15SSoren Brinkmann &aperclk_lock); 5360ee52b15SSoren Brinkmann clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], 5370ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, 5380ee52b15SSoren Brinkmann &aperclk_lock); 5390ee52b15SSoren Brinkmann clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], 5400ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, 5410ee52b15SSoren Brinkmann &aperclk_lock); 5420ee52b15SSoren Brinkmann clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], 5430ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, 5440ee52b15SSoren Brinkmann &aperclk_lock); 5450ee52b15SSoren Brinkmann clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], 5460ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, 5470ee52b15SSoren Brinkmann &aperclk_lock); 5480ee52b15SSoren Brinkmann clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], 5490ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, 5500ee52b15SSoren Brinkmann &aperclk_lock); 5510ee52b15SSoren Brinkmann clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], 5520ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, 5530ee52b15SSoren Brinkmann &aperclk_lock); 5540ee52b15SSoren Brinkmann clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], 5550ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, 5560ee52b15SSoren Brinkmann &aperclk_lock); 5570ee52b15SSoren Brinkmann clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], 5580ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, 5590ee52b15SSoren Brinkmann &aperclk_lock); 5600ee52b15SSoren Brinkmann clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], 5610ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, 5620ee52b15SSoren Brinkmann &aperclk_lock); 5630ee52b15SSoren Brinkmann 5640ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(clks); i++) { 5650ee52b15SSoren Brinkmann if (IS_ERR(clks[i])) { 5660ee52b15SSoren Brinkmann pr_err("Zynq clk %d: register failed with %ld\n", 5670ee52b15SSoren Brinkmann i, PTR_ERR(clks[i])); 5680ee52b15SSoren Brinkmann BUG(); 5690ee52b15SSoren Brinkmann } 5700ee52b15SSoren Brinkmann } 5710ee52b15SSoren Brinkmann 5720ee52b15SSoren Brinkmann clk_data.clks = clks; 5730ee52b15SSoren Brinkmann clk_data.clk_num = ARRAY_SIZE(clks); 5740ee52b15SSoren Brinkmann of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 5750ee52b15SSoren Brinkmann } 5760ee52b15SSoren Brinkmann 5770ee52b15SSoren Brinkmann CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); 5780ee52b15SSoren Brinkmann 579b0504e39SMichal Simek void __init zynq_clock_init(void) 5800ee52b15SSoren Brinkmann { 581b0504e39SMichal Simek struct device_node *np; 582b0504e39SMichal Simek struct device_node *slcr; 583b0504e39SMichal Simek struct resource res; 584b0504e39SMichal Simek 585b0504e39SMichal Simek np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); 586b0504e39SMichal Simek if (!np) { 587b0504e39SMichal Simek pr_err("%s: clkc node not found\n", __func__); 588b0504e39SMichal Simek goto np_err; 589b0504e39SMichal Simek } 590b0504e39SMichal Simek 591b0504e39SMichal Simek if (of_address_to_resource(np, 0, &res)) { 592e665f029SRob Herring pr_err("%pOFn: failed to get resource\n", np); 593b0504e39SMichal Simek goto np_err; 594b0504e39SMichal Simek } 595b0504e39SMichal Simek 596b0504e39SMichal Simek slcr = of_get_parent(np); 597b0504e39SMichal Simek 598b0504e39SMichal Simek if (slcr->data) { 599b0504e39SMichal Simek zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; 600b0504e39SMichal Simek } else { 601e665f029SRob Herring pr_err("%pOFn: Unable to get I/O memory\n", np); 602b0504e39SMichal Simek of_node_put(slcr); 603b0504e39SMichal Simek goto np_err; 604b0504e39SMichal Simek } 605b0504e39SMichal Simek 606b0504e39SMichal Simek pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); 607b0504e39SMichal Simek 608b0504e39SMichal Simek of_node_put(slcr); 609b0504e39SMichal Simek of_node_put(np); 610b0504e39SMichal Simek 611b0504e39SMichal Simek return; 612b0504e39SMichal Simek 613b0504e39SMichal Simek np_err: 614b0504e39SMichal Simek of_node_put(np); 615b0504e39SMichal Simek BUG(); 6160ee52b15SSoren Brinkmann } 617